Challenges of MOS Analog Circuit Simulation with SPICE

Andrei Vladimirescu and Jean-Jacques Charlot

Cadence Design Systems 555 River Oaks Pkwy, San Jose, CA 95134, USA.

E o l e Nationale Superieure de Telecommunications 46, rue Barrault, 75634 Paris, France.

Abstract

This paper describes SPICE MOSFET implementation details, known model imperfections and MOS circuit techniques that contribute to simulation convergence failure of CMOS andog circuits. Discontinuities in the MOS Level 2 and 3 Drain-Source conductance and Gate-Drain transconductance and the relation to model parameters are highlighted. Convergence difficulties are exemplified by the simulation of a CMOS Merentid amplifier with active cpseode loads. Solutions for convergence are described based on model- parmeter/physical+ffect selection, options specification, initialization techniques and algorithmic choices.

1. Introduction

Designers of CMOS or BiCMOS analog circuits face more difficulties than their bipolar counterparts when they simulate their circuits with SPICE2, SPICE3 and commercial derivatives of the programs. Accuracy problems in modeling MOS analog circuits have been already documented in the past. The widespread use of SPICE MOSFET models Level 2 and 323 requires a better knowledge of the imperfextions and the best ways to avoid them.

Model imperfections can lead to numeric oscillations between two regions during the nonlinear solution process. In such situations altering the model can lead to an initial solution. The significance of including or deleting physical effects in a model through the parameters which are specified is described in Section 2. Charcteristics of the Drain-Source conductance g, and the Gate-Drain transconductance g, are traced for different sets of model parameters.

Some circuit configurations used in CMOS designs such as cascode current sources and gain stages introduce high-impedance nodes; such nodes contribute very low conductances in the circuit matrix leading to numeric instability. In search for high gains and low power consumption CMOS stages are often biased close to the limit between linear, saturation and cut-off regions. A differential amplifier is used in Section 3 to exemplify difficulties encountered in simulation.

A user of circuit simulation can improve the rate of success of SPICE runs by following a number of steps which are described in Section 4.

Commercial SPICE programs may have corrected or improved some of the issues presented in this paper. A number of new models, e.g., the BSIM14 and BSIM2 models, have been added to present-day SPICE simulators to overcome discontinuities at the transition between different regions of operation. The wide use of MOSFET models Level 1, 2, and 3, is due to their universal availability and it is important that designers understand the imperfections and limitations of these models in the SPICE version they use.

2. SPICE MOSFET Model Specifics

MOSFET circuits have been observed to have more convergence problems than bipolar circuits due to a number of differences between the two device types. First, the physical structure of the two devices is different. The gate terminal of a MOSFET is insulated, i.e., it is an open-circuit in DC. The self-conductance of the gate is therefore zero in DC which can often lead to ill-conditioned circuit matrices, and, subsequently, to a SPICE failure to find a

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solution. By contrast, there is continuous current flowing in or out of the base terminal of a bipolar transistor, independent of region of operation and analysis mode.

Second, the generality of analytical models used in SPICE to describe the two devices is not the same. While the Ebers-Moll or Gummel-Poon formulation for the BJT transistor applies to all regions of operation the MOSFET models combine different equations to describe distinct regions of operations and various secondader effects. The different formulations have varying levels of continuity for the equivalent conductance at the @ansition points. The continuity of the conductance, which is the first derivative of the function, is important for the convergence of the iterative process.

Third, the implementation details in SPICE also affect convergence. The presence of specific parameters result in given physical behaviors being modeled, e.g.. the presence of h'FS triggers a subthreshold current to flow at values of gate-source voltage, V , which are less than the threshold voltage VTO. Subthreshold current modeling can cure problems related to device current convergence by avoiding the I,, discontinuity at the threshold voltage. This discontinuity is an important departure from bipolar device operation where the current varies continuously starting from the junction reverse current

Similar issues and conductance discontinuities are related to the type of saturation mechanism selected, channel pinch-off or velocity-limited saturation. The I,, characteristic as a funtion of V , is shown in Fig. 1 for a Level 2 model; the transition from subthreshold conduction to strong inversion is not smooth which leads to a discontinuity in the g, characteristic which can be seen clearly in Fig. 2. Both characteristics are plotted for V,, equal 1V. Another discontinuity in the conductance characteristics occurs at the transition from saturation into the linear region. The first g, curve corresponds to a model with subthreshold conduction and velocity-limited saturation while the second curve corresponds to a model with no weak inversion conduction, NFS is not specified, and channel- pinch-off saturation, VMAX and NEFF are not specified. Another set g, graphs are shown in Fig. 3 for V,, equal to 0.1V. Another important characteristic of a MOS transistor is the g, conductance which is represented as a function of V,, in Fig. 4.

3.

In addition to physical and model differences between bipolar transistors and MOSFETs there are differences in the way SPICE processes the two types of devices. Thus, operating points in which the program initializes the two types of devices differ and so does the selection procedure ofnew operating points at each iteration. In the first iteration an important difference between BJTs and MOSFETs is that by default the former are initialized conducting whereas, generally, MOSFETs are initialized cut off. MOSFETs are initialized with V,, = VTO and the difficulty with MOSFETs is that the actual threshold voltage, V,, is usually increased by back-gate bias to a higher value than the zero-bias threshold voltage, W O . Only MOSFET devices with subthreshold current, defined by model parameter NFS, a~ initially in the conduction state. This is one example where convergence can be improved by changing model parameters.

The default initialization of transistors has a different impact on convergence depending on the operation of the circuit. A smaller number of iterations have been noticed for analog (linear) bipolar circuits as compared to digital (logic) bipolar circuits due to the fact that BJTs are initialized as conducting in SPICE. The explanation can be found in the mode of operation of analog circuits which have the majority of the transistors turned on in contrast with digital circuits which have an important percentage of the devices turned off. Experiments in the SPICE code which initialized all MOSFETs in the conduction state have proven to speed up the convergence of analog circuits. A user cao gain access to initialization through the device initial conditions, IC=v,,v,,v,, which are activated only in transient analysis in conjunction with the UIC option. The OFF sta te can also be specified for individual devices.

The importance of initialization and device specifics for the convergence of MOS analog circuits especially those with high-impedance nodes often present in cascode loads, can be exemplified by a CMOS differential amplifiep shown in Fig. 5. The following MOS parameters have'been used in the simulation:

Simulation of Analog MOS Circuits

* + N-CHANNEL TRANSISTOR + .MODEL N NMOS LEvEL=2 + U0=600 VTO=700E-3 TPG=1.000 TOX=25.OE-9 NSUB=5.OE+16 UCRIT=IE+I UEXP=o.1 + XJ=lE-lO LD=100E-9 PB=0.8 JS=100.OE-6 RSH=100 NFS=200E+9 VMAX=6OE+3 NEFF=2.5

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DELTA=3 + CJ=400E-6 MJ=300E-3 CJSW=2.00E-9 MJSW=l.O CGSO=2.0E-10 CGDO=2.OE-10 CGBO=3.0E-10

P-CHANNEL TRANSISTOR

.MODEL P PMOS LEVEL=2 + U0=200 VTO=-700E-3 TPG=-1.000 TOX=25.OE-9 NSUB=2.OE+16 UCRIT=ZE+4 UEXP=O.1 + XJ=lE-lO PBz0.8 JS=100.OE-6 RSH=200 NFS=100E+9 VMAX=20.00E+3 NEFFz.9 DELTA=l + CJ=400E-6 W=300E-3 CJSW=2.00E-9 WSW=l.O CGSO=2.OE-10 CGW=2.OE-10 CGBO=3.0E-10 *

This circuit is a differential amplifier in a unity feedback loop; the conversion from double to singleended output is achieved by PMOS transistors &-MV The state of this circuit is defined by connecting the appropriate bias transistors MI,-MI, to the gates of transistors M5, differential pair transistor M,, the gates of load transistors M,, M,,

The fust challenge comes with the DC solution. Based on knowledge of electric networks one can see the difficulty associated with solving the nodal equations of this circuits due to a number of very low-conductance nodes; nodes 3 and 4 have very high impedance defined by the cascode connection, and, in addition, all transistors are biased very close to the threshold voltage on one hand, and at the limit between saturation and linear region, on the other hand. This approach to biasing is common in analog CMOS circuits.

and &. M,.

4. Convergence Guidelines

The attempt to find the DC operating point of the circuit as is, Fig. 5 fails in SPICE2 but succeeds in PSpice and SPICE3, after source ramping. Addition of the option I T L W to the SPICE2 input does not help for this circuit. It is important to note that SPICE2 which provides more feedback related to a solution failure, encounters problems in the matrix solution: the messages PIVOT CHANGE ON THE FLY and *ERROR* : MAXIMUM ENTRY . . . IS LESS THAN PIVTOL can be found in the output file.

When ramping methods fail for this type of difficult circuits running a transient analysis while ramping the supplies from 0 to the DC value or leaving them unchanged may lead to a solution. If the supplies are ramped for part of the time interval, it is advised to preserve the DC value for the rest of the timedomain analysis in order to allow the circuit to settle. A timedomain analysis of an MOS circuit has the additional advantage of a well- conditioned matrix because charge-storage elements provide a finite conductance at the gates of MOSFETs. Transient ramping of the CMOS differential amplifier in Fig. 5 is performed when the .TRAN and .PRINT lines are added. Note that a DC solution should be avoided by using the UIC keyword on the .TRAN line.

Several options can be modified for this circuit; based on the observation of the condition of the circuit matrix a first approach is to tighten the pivot selection criterion by increasing the value of PIVREL to lo-*. Second due to the possible operation near threshold of some transistors the absolute cunrent tolerance ABSTOL can

These two options contribute to a successful timedomain solution in SPICEZ. An average value of the last time-points is chosen to initialize the node voltages with a .NODESET statement. The DC operating point is obtained easily for this circuit when the node voltages are initialized.

The solution verifies that the bias point of the transistors in this circuit is very close to the boundary between subthreshold conduction, linear and saturation regions. The location of the bias point is the main cause for the convergence difficulty.

An alternate way to find a solution for this circuit and for amplifiers in general is to cut the feedback loop and fmd a DC solution of the open loop amplifier. Then, the node voltages obtained from the open-loop circuit can be used in a .NODESET statement to initialize the closed-loop amplifier. The open-loop solution for this circuit proves non-trivial.

The complexity of a model has an impact on convergence. An alternate approach to overcome model imperfections and convergence failure is to simplify the model down to a basic LEVEbl . This model is described by a single function which is continuous along with the first derivative. This approach alone or combined with a higher value of the ABSTOL option parameter to overcome the current discontinuity at the threshold voltage, can lead to a solution. The results of this solution can then be used to initialize a simulation using more complex models.

be raised to 1 pA.

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5. Conclusion

This paper has described the shortcomings of SPICE MOS models Level 2 and 3. The added accuracy in describing second-order physical effects has a negative impact on simulation convergence. Wile bem models are available in some commercial SPICE pmgrams it is important for designers to understand how to overcome imperfections in the standard SPICE2 MOSFET models. k models a~ still the most commonly used

A common CMOS circuit has been presented to exemplify the convergence difficulties that a user can encounter. In spite impufections in the modcl a correct solution can be found by following a number of convergence guidelines ennumerated in the last part of this paper.

References

1. Y. Tsividis and G. Masetti, "Problems in Recision Modeling of the MOS Transistor in Analog ApplicXtiom," IEEE Trans. Computer-Aided Design. Vol. CAD-3. pp. 72-19. Jan. 1984.

2. A. Vladimirescu and S. Liu, The Simulation of MOS Integrated Circuits Using SPICE2, University of Califomia, Memo UCBERL M80/7, Berkeley. March 1981.

3. P. Antognetti and G. Massobrio. Semiwnductor Device Modeling with SPICE, Mc.Graw Hill, New York, 1988.

4. B.J. Sku. D.L. Scharfettcr, and P.K. KO, SPICE2 Implementation of BSIM Model, University of California ERL Memo No. ERL M85/42, Berkeley, May 1985.

5. M.C. Jeng, Design and Modeling of Lkep-Submicrometer MOSFETs, University of California, ERL Memo No. ERL M90/90. Berkeley, Oct. 1990.

6. D. Senderowicz, private Communication.

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