Challenges for Embedded Device Technologies for Package Level Integration

Kevin Cannon, Steve Riches – Tribus-D Ltd

Guangbin Dou, Andrew Holmes – Imperial College London

Embedded Die Technology – IMAPS-UK/NMI Conference

22 September 2016

Scope of Presentation • Overview of Tribus-D Ltd and Imperial College London

• Challenges for Embedded Die Technology • Advanced Package Types

• Technical

• Components

• Commercial

• Technology Trends

• Can Embedded Die Technology be Applied to Custom Products? • Embedded Die at Package Level

• Laser Generated Ultrasound Micro-welding Techniques

• Process Developments Required

• Concluding Remarks

Overview of Tribus-D and Imperial College London

Tribus-D Ltd Imperial College London

• Experience in wide range of packaging technologies • Interest in developing versatile packaging solutions • Support of R&D activities in Universities

• 20-year track record in MEMS and Nanotechnology, including assembly and packaging technologies

• Applications in sensing/instrumentation, energy harvesting/storage and nano-electronics

Advanced Package Types

QFN – Quad Flat No-Lead Courtesy of Digikey

WLCSP (Fan In) Wafer Scale Chip Scale Package

Courtesy of Digikey

FOWLP (Fan Out) Wafer Level Package Courtesy of Electroiq

Advanced Package Types

Flip Chip Courtesy of Dow

2.5D and 3D IC Courtesy of Indium Corp

Embedded Die Technology Courtesy of Fraunhofer IZM

Advanced Package Types Package Types Miniaturisation Increased

Performance Increased Functionality

Established Applications

Quantities

QFN X X X RF packaging Low to High

Fan-In (WLCSP) √ X X Analog/Mixed Signal Automotive Radars

High

Fan-Out (FOWLP) √ √ X Wireless Power

High

Flip-Chip √ √ X Mobile Consumer

Med to High

2.5D/3D IC √ √ √ CMOS Image Memories/GPUs

High

Embedded Die √ √ √ Power Sensors

Low to High

Ref: Beica R et al “The Growth of Advanced Packaging: An Overview of the Latest Technology Developments, Applications and Market Trends” IMAPS 2015 Orlando, October 2015, pp 1-5

Technical Challenges for Embedded Die Technology

• Miniaturisation • Bond pad bumping • Laser drilled via/Cu plating fill • Connection to bond pad • Die thinning • Thermal density • Multi-level structures (crosstalk) • Reliability/lifetime • Thermally conductive voltage isolation • Electro-magnetic effects

(radiated/susceptibility) • End of Life recycling

Image: Andreas Ostmann, Fraunhofer IZM

Component Challenges for Embedded Die Technology • Compatible metallisation systems on devices,

components and substrates • Encapsulants and substrates with dielectric and

thermal properties • Flexibility to accommodate different devices

types and ratings • Incorporation of driver and control electronics

Image: Lars Boettcher et Al, Fraunhofer IZM Ref: Embedding of Chips for System in Package Realisation –

Technology and Application

Commercial Challenges for Embedded Die Technology • Economies of scale • Low volume vs high volume • Established supply chain • In-house manufacture vs sub-contract • Standard vs customised product • Investment required • Level of integration • Low power vs high power • Availability of bare die • Minimum order quantities • Yield • Obsolescence • Cost modelling • Patent issues

Typical FOWLP Process Flow Source: Palesko A “Using Cost Modelling to Make Better Design Decisions”

Chip Scale Review, September-October 2015, pp37-40

Technology Trends - Structural In-Mould Electronics

Printed Circuit Building Block Courtesy of TactotekTM

Proximity Sensor/Lightstrip Courtesy of TactotekTM

Technology Trends - 3D Printed Electronics

Conformal Printed Antenna Courtesy of Optomec

3D Printed LED and Resistor Courtesy of Voxel 8

Can Embedded Die Technology be Applied to Custom Products?

Assumptions: • Use standard SM PCB assembly techniques • Embedding at package level • Use sinter/plated material to provide interconnection Proposed Assembly Route: • Deposition of sinter/plated material • Preparation of devices for attachment • Attachment of devices to sinter/plated material • Encapsulation of devices • Back lamination • Lift-off from carrier • Singulation into devices • Solder placement and reflow

Embedded Die and Components at Package Level

Assembly Process Steps Assembly Step Materials Processes

1. Deposition of sinter/plated material onto carrier Sinter/plated material onto carrier plate Screen printing/dispense of sinter material and sintering Plating of Cu or Ag

2. Preparation of devices for attachment Cu pillars Al metallisation bond pads

Supplied from foundry Cu stud bumping, Cu plating

3. Attachment of devices to sinter material Cu studs to sinter/plated material LGU (*) + pressure + heat Thermosonic bonding

4. Encapsulation of devices High thermal conductivity encapsulant Moulding 3D Printing

5. Back lamination Cu or Al sheet Conductive adhesive or sinter

Screen printing or film lamination and curing

6. Lift-off from carrier Mechanical removal

7. Singulation into devices Wafer sawing Laser cutting

8. Solder Placement and Reflow Sn-Ag-Cu alloy HT solder Other

Screen printing and reflow Solder jet deposition Solder ball placement

Laser-Ultrasonic Micro-Welding Process

• Use of pulsed laser to generate ultrasound close to individual bonding site

• Stress transients produced by confined laser ablation of sacrificial layer between bond head and workpiece

• Allows localised control of bonding parameters - may facilitate scaling of ultrasonic flip-chip attachment to larger chip sizes

• Demonstrated for Cu-Ag bonding on high-temp substrates

• Potentially also applicable to temperature-sensitive materials because of localised, transient heating

• Needs to be scaled to manufacturable process

See: Dou G., Gower M.C., Holmes A.S., “Micro-welding using laser-generated ultrasound”, Proc. ESTC 2016, Grenoble, France, 13-16 September 2016

Laser-Ultrasonic Micro-Welding Process

• R&D bonder with windows in sample platform and bond head to allow illumination from above and below

• Two laser sources: • upper: 20 W max average power, 1064 nm wavelength

nanosecond pulsed laser for u/s generation • lower: 30 W, 970 nm wavelength laser diode for pre-heating

workpiece

• Initial work with sacrificial layer comprising 75µm-thick W (tungsten) with overlying glass layer. W acts as IR absorber; ablation occurs mainly in glass

• Bonding demonstrated for Au-Au and Cu-Ag systems

Cu-Ag bonding by Laser-Ultrasonic Technique

• Flip-chip attachment of Cu-bumped silicon dies to high-temperature substrates with sintered Ag metallisation

• Individual bump shear tests showed average shear strengths of ~116 MPa for bumps transferred to Ag layer

• FIB-SEM analysis indicated solid-state micro-welds with clear bonding line

Images: a) bumps on chip before bonding; b) chip surface after de-bonding; c) bumps transferred to Ag layer on substrate; d) FIB-SEM image

d)

Process Developments Required Assembly Step Development Required Comments

1. Deposition of sinter material onto carrier

Optimisation of carrier and coating

2. Preparation of devices for attachment

Copper stud bumping or Cu plating

3. Attachment of devices to sinter material

Scalable manufacturable process for Cu bump to Ag or Cu sinter

Techniques for rapid alignment and assembly

4. Encapsulation of devices 3D printing of moulding compound or thermoplastic

Rapid prototyping using polymers

5. Back lamination High thermal conductivity assembly to encapsulant/thermoplastic and devices

Adhesion – encapsulant or thermoplastic to Cu or Al conductor Rapid prototyping through late customisation

6. Lift Off from carrier Mechanical removal

7. Singulation into devices Sawing/laser cutting

8. Solder Placement and Reflow

Reliability of SAC solder alloy to Ag sinter joints

Concluding Remarks

• Widespread investment is taking place to develop embedded die technologies at the package level and printed circuit board level, some of which have reached production maturity

• Other technologies such as structural in-mould and 3D printing are advancing into the electronics arena

• There is scope for applying embedded die technology for custom products at the package level, but developments are required to prepare devices for attachment and demonstrate technical and economic benefits

• Imperial College are investigating novel micro-welding techniques to provide interconnections for temperature sensitive applications