Ch3_The Metal Layers
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Transcript of Ch3_The Metal Layers
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Figure 3.1 The bonding wire connection to a pad.
Bonding wire
Pad
(the smashed wire)
(the bright square)
100 µm (final size)
100 µm (final)
FOX
InsulatorInsulator
Top of the wafer or die
Metal2
Layout or top view
Cross-sectional view
Insulator
p-substrate
Layout of metal2 used for bonding pad with associated cross-sectional view.Figure 3.2
Table 3.1 Typical parasitic capacitances in a CMOS process. Note that while thephysical distance between the layers decreases, as process technology scalesdownwards, the dielectric constant used in between the layers can be decreased tokeep the parasitic capacitances from becoming too significant. The values arerepresentative of the parasitics in both long- and short-channel CMOS processes.
Plate Cap. aF/µm2
min typ maxFringe Cap. aF/µm
min typ maxPoly1 to subs. (FOX) 53 58 63 85 88 92Metal1 to poly1 35 38 43 84 88 93Metal1 to substrate 21 23 26 75 79 82Metal1 to diffusion 35 38 43 84 88 93Metal2 to poly1 16 18 20 83 87 91Metal2 to substrate 13 14 15 78 81 85Metal2 to diffusion 16 18 20 83 87 91Metal2 to metal1 31 35 38 95 100 104
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Top of the wafer or die
InsulatorInsulator
Overglass opening
Insulator
2,000 (drawn)
Layout of a metal2 pad with pad opening for bonding connectionFigure 3.3in a 50 nm (scale factor) CMOS process.
Metal2
Overglass layerSpacing between OVGL layer and metal2exactly 6 µm or a drawn
2,000 (drawn)distance of 120
InsulatorInsulator
InsulatorFOX
p-substrate
Figure 3.4 Layout and cross-sectional views.
Metal2
Via1
Via1Metal1
Cross-sectionCross-section
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Metal1
Metal2
Cross-section
Figure 3.5 An example layout and cross-sectional view using including the n-well.
n-well
InsulatorInsulator
InsulatorFOX
p-substraten-well
Metal2Metal1
Via1
Cross-section
p-substrate
4
20,000
Metal1 layout view for Ex. 3.3. 4One square
Drawn layout
Figure 3.6 Layout and cross-sectional view with parasitics for the metal line in Ex. 3.3.
1 2 3 4,999 5,000
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
in
out
time
28 ps
Figure 3.7 Simulating the delay through a 1 mm wire made using metal1.
*** Figure 3.7 CMOS: Circuit Design,Layout, and Simulation ***.controldestroy allrunplot vin vout.endc.tran 1p 250p
O1 Vin 0 Vout 0 TRCRload Vout 0 1GVin vin 0 DC 0 pulse 0 1 50p 0.model TRC ltra R=0.1 C=32e-18 len=5k.end
Layout view of 10 square metal1 and metal2
Metal2 is the topplate of the capacitorand metal 1 is bottom.
Insulator
Insulator
Capacitance between metal1 and metal2.Figure 3.8
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
01
Equivalent circuit used to calculate the change in metal1 voltage, see Ex. 3.5.Figure 3.9
C12
C1sub
∆Vmetal1∆Vmetal2
Figure 3.10 Simulating the operation of the circuit in Fig. 3.9.
∆Vmetal2∆Vmetal1*** Figure 3.10 CMOS: Circuit Design,Layout, and Simulation ***
.controldestroy allrunplot vmetal2 vmetal1.endc
.tran 10p 5n UIC
vmetal2 vmetal2 0 DC 0 pulse 0 1 2n 1n
C12 vmetal2 vmetal1 209e-18C1sub vmetal1 0 164e-18
.end
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Metal1
Met
al2
Met
al2
Overlap of via1 withmetal1 and metal2
Minimum spacing 1.5
Min
imum
wid
th 1
.5 Via1 exact size 1.5 by 1.5
is a minimum of 0.5
Minimum width is 1.5
Min
. spa
ce 2
Figure 3.11 Design rules for the metal layers using the CMOSEDU rules.
Metal1
(a) Layout using two boxes (b) Layout using a single box
Figure 3.12 Equivalence of layouts drawn with a different numberof shapes.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Figure 3.13 Via1 cell with a rank of 1.
Three boxes: a via1 box that is1.5 by 1.5, a metal1 box 2.5 by2.5, and a metal2 box directlyplaced on the metal1 box thatis 2.5 by 2.5.
Insulator
Insulator
Cross-sectionalview of the via1cell.
M1
M2
Figure 3.14 Layouts used in Ex. 3.8.
(a) (b)
Minimum via spacing, 1.5M1
M2
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
M2
M1
10
M2
M1
10
(a) The contact resistanceof the via in Fig. 3.14a.
(b) The contact resistanceof the four vias in Fig. 3.14b.
101010
Figure 3.15 The schematics of the contact resistances forthe layouts in Fig. 3.14.
Conductors used to illustrate crosstalk.Figure 3.16
Layout view Angled view
p-subFOXInsulator
Metal1
Cm
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Circuit
10 mm of metal1 150 nm wide
VDD
Ideally
Ideally ground (= 0 V)
I
I
VDD
10 mm of metal1 150 nm wide
Circuit
6.67k
6.67k
1V
50 µA
50 µA
667 mV (not 1 V)
333 mV (not 0 V)
(a)
(b)
Figure 3.17 Illustrating problems with incorrectly sized conductors.
Pad
Pad
VDD
VDD
ground
ground
BufferIn Out
30 pF
VDD
Figure 3.18 Estimating the decoupling capacitance needed in an output buffer.
Off-chipOn-chip
Decoupling C
Table 3.2 Sizes for an example 1 mm square chip with a scale factor of 50 nm.
Final size Scaled sizePad size 100 µm by 100 µm 2,000 by 2,000
Pad spacing (center to center)
130 µm 2,600
Number of pads on aside (corners empty)
6 6
Total number of pads 24 24Overglass opening 88 µm by 88 µm 1,760 by 1,760
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Figure 3.19 Layout of a Via1 cell.
2.5
1.5
2.5
Metal2
Via
Metal1
Layout view
Figure 3.20 Layout of the bonding pad.
2,000 (100 um)
2,00
0 (1
00 u
m)
Both metal1 and metal2 Outline layer
30015 um
Overglass
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Overglass layer
120 (6 um)
120
Figure 3.21 Corner detail for the pad in Fig. 3.20.
(6um)
Zoomed in corner showing vias
Figure 3.23 The layout of a padframe.
1,040 um or 20,800
CMOS circuitry goes in this area.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
InsulatorInsulator
Overglass opening
Insulator
Metal2Metal1
Via1
Figure 3.22 Simplified cross-sectional view of the bonding pad discussed in this section.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Figure 3.24 Showing the layout of various patterns for measuring parasitics.
A
B(a) A serpentine pattern AB
(b) Rectangular patternAB
(c) Using two serpentine patterns to measure mutual capacitance
x
y
A B
(d) Measuring plate capacitance
Cm
Figure 3.25 SEM photo showing patterned metal layers.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Metal1
Overglass layer
Figure 3.26 Layout used in Problem 3.4.
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Metal2
Via1 Via2Metal1
Metal3
Figure 3.27 Layout for Problem 3.5.
Figure 3.28 Layout for Problem 3.8.
Met
al2
Metal1 Metal1
Met
al2
Metal1
N-well
A B
Figures from CMOS Circuit Design, Layout, and Simulation, Second Edition
By R. Jacob Baker, Copyright Wiley-IEEE
Figure 3.29 Circuit used to show the benefits of a decoupling capacitor.
VDD1 V
5k
5kCurrent pulse usedto model a circuitpulling current.Resistance of the wires
Decoupling capacitor
Ideally VDD
Ideally ground