Ch16 (1) electronics

8/10/2019 Ch16 (1) electronics

1/94

Chapter 16 CMOS Amplifiers

16.1 General Considerations

16.2 Operating Point Analysis and Design 16.3 CMOS Amplifier Topologies

16.4 Common-Source Topology

16.5 Summary and Additional Examples

16.6 Chapter Summary

1


2/94

Chapter Outline

2CH 16 CMOS Amplifiers


3/94

Example: Desired I/O Impedances


inR 0ampR


4/94

Method to Measure the I/O Impedances


To measure Rin(Rout), deactivate all the other independent

sources in the circuit and find the ratio of vX/iX.

X

Xini

vR

X

Xout

i

vR


5/94

Example: Input Impedance of a Simple Amplifier


inX Ri 0


6/94

The Concept of Impedance at a Node


When the other node of a port is grounded, it is more

convenient to use the concept of impedance at a node.


7/94

Example: Impedance Seen at Drain


Oout rR


8/94

Example: Impedance Seen at Source


m

outg

R 1


9/94

Impedance Summary


Looking into the gate, we see infinity. Looking into the drain, we see rOif the source is (ac) grounded.

Looking into the source, we see 1/gmif the gate is (ac)

grounded and rOis neglected.


10/94

Bias and Signal Levels for a MOS Transistor


Bias point analysis establishes the region of operation and the

small-signal parameters.

On top of the bias point, small signals are applied to the circuit.


11/94

General Steps in Circuit Analysis


First, the effects of constant voltage/current sources are

analyzed when signal sources are deactivated.

Second, small-signal analysis is done when constant sources

are set to zero.


12/94

Simplification of Supply Voltage Notation



13/94

Example: Amplifier Driven by a Microphone


20mV

0V

Microphone Output

Since the DC (average) value is at zero, and 20mV is not

sufficient to turn on M1, M1 is off and Voutis at VDD.


14/94

Example: Amplifier with Gate Tied to VDD


Since the gate voltage level is fixed at VDD, no signal current

will be produced my M1, leading to no amplification.


15/94

Example: Amplifier with Gate Bias


With proper value of VB, M1can operate in the desired

saturation region and amplify the incoming voice signal.


16/94

Simple Biasing


In (a), VGS=VDD, whereas in (b) VGSequals to a fraction of VDD.

DDGS V

RR

RV

21

2


17/94

Example: Bias Current and Maximum RD


KR

KR

LW

VAC

VV

oxn

TH

15

20

0

18.05

/100

5.0

2

1

2

KRVVVVV

AVVRR

RLWCI

DRDTHGSD

THDDoxnD

15529.1271.0

10221

maxmin

2

21

2


18/94

Capacitive Coupling


Capacitive coupling is used to block the zero DC output value

of the microphone and pass the voice signal to the amplifier.


19/94

Biasing with Source Degeneration


Soxn

THDD

THGS

RL

WC

V

VRR

VRVVVVV

1

2

1

21

21

2

11


20/94

Example: ID and Maximum RDfor Source Degeneration Biasing


0

18.0/5/

/1005.0

2

LW

VACVV

oxn

TH

KI

VVVR

VVRR

VRVVVVV

V

RL

WC

V

D

THXDDD

THDD

THGS

Soxn

25.3)(

974.02

36.01

21

21

2

11

1


21/94


22/94

Self-Biased MOS Stage


22

1THDDSDDoxnD VIRRV

L

WCI

The gate voltage is provided by the drain with no voltage drop

across RGand M1is always in saturation.


23/94

Example: Self-Biased MOS Stage


0

5.0

/100 2

VV

VAC

TH

oxn

KRAI

AI

DD

D

867.2278

556


24/94

Example: PMOS Stage with Biasing

VVKR

KR

LW

VAC

TH

oxp

5.015

20

0

18.05

/50

2

1

2

KRSaturation

AVVL

WCI

VVRR

RV

D

THGSoxpD

DDGS

3.27

562

1

771.0

max

2

21

2



25/94

Example: PMOS Stage with Self-Biasing

VV

LW

VAC

TH

oxp

5.0

0

18.05

/50 2

AI

VRIVLWCI

D

THDDDDoxpD

418

21 2



26/94

Good Example of Current Source

As long as a MOS transistor is in saturation region and =0, the

current is independent of the drain voltage and it behaves as an

ideal current source seen from the drain terminal.



27/94

Bad Example of Current Source

Since the variation of the source voltage directly affects the

current of a MOS transistor, it does not operate as a good

current source if seen from the source terminal



28/94

Possible I/O Connections to a MOS Transistor

Of all the possible I/O connections to a MOS transistor, only

(a,d), (a,e) and (b,d) are functional.



29/94

Common Source (CS) Stage

If the input is applied to the gate and the output is sensed at the

drain, the circuit is called a common-source (CS) stage.



30/94

Small-Signal Model of CS Stage


Dmv

m

D

out

RgA

vgR

v

1


31/94

Example: CS Stage

31

33.3

300

1

2

Dmv

Doxnm

RgA

IL

W

Cg

CH 16 CMOS Amplifiers

0

5.0

/100

1

2

VV

VAC

mAI

TH

oxn

D

Saturation

VIRVVVV

V

L

WC

IVV

DDDDTHGS

oxn

DTHGS

6.08.0

8.0,6.0

1.12


32/94

Example: Faulty CS Stage Design


0

18.05

/100

5.0

5

8.1

1

2

LW

VAC

VV

A

VV

mWPower

oxn

TH

v

DD

28455

56915561

Dv

mD

RA

gAImWPower

However, no solution exists since M1is out of the saturation

region (VDD-IDRD


33/94

CS Stage I/O Impedance Calculation

x

xin

i

vR


D

x

xout R

i

vR


34/94

CS Stage Including Channel-Length Modulation


ODout

ODmv

rRR

rRgA

||

||


35/94

xAv

Example: Gain

2xAv


No Channel-Length Modu lat ion With Channel-Length Modu lat ion

DD

D

D

O

RI

R

I

r

1

1


36/94

Example: RD


D

oxn

D

oxn

v

Omv

I

WLC

I

LWC

A

rgA

2

2


37/94

CS Stage with Current Source Load


21

211

||

||

OOout

OOmv

rrR

rrgA


38/94

Example: CS Stage with Current Source Load


211

||OOmv

rrgA


39/94

CS Stage with Diode-Connected Load


12

2

12

2

1

||||1

||||1

OO

m

out

OO

m

mv

rrg

R

rrg

gA


40/94

Example: CS Stage with Diode-Connected PMOS


121

2 ||||

1OO

mmv rrggA


41/94

CS Stage with Source Degeneration


S

m

Dv

Rg

RA

1


42/94

Example: CS Stage with Source Degeneration


21

11

mm

D

v

gg

R

A


43/94

Example: Degeneration Resistor

8

2001

v

m

A

g

4

2001

v

m

A

g


200141

6.18

mS

Sm

Dm

DDm

gRRg

Rg

KRRg

Withou t Degenerat ion With Degenerat ion


44/94

Effective Transconductance


Sm

m

in

outm

Rg

g

v

iG

1


45/94

Effect of Transistor Output Resistance


SmOoutSOmOout

RgrR

RrgrR

1

1


46/94

Stage with Explicit Depiction of rO


Sometimes, the transistors output resistance is explicitly

drawn to emphasize its significance.


47/94

Example: NMOS Current Source Design

VV

V

VAC

KR

mAI

DS

oxn

out

D

3.0

25.0

/100

20

1

min

1

2


578

201

150

12

3.0min

S

SOSm

THGS

D

m

THGSDS

R

KRrRg

VV

I

g

VVV


48/94

Example: Output Resistance of CS Stage with Degeneration I


121

22

11

2

111

Ooutmmm

mm

mOout

rRggg

gggrR


49/94

Example: Output Resistance of CS Stage with Degeneration II


211

12111OOmout

OOOmout

rrgRrrrgR


50/94

Example: Failing Microphone Amplifier


No Ampli f icat ion!!

Because of the microphones small low-frequency output

resistance (100), the bias voltage at the gate is not sufficient

to turn on M1.

mVVKK

KVX 5.25.2

50||100100

50||100


51/94

Capacitive Coupling


To fix the problem in the previous example, a method known as

capacit ive cou pl ingis used to block the DC content of the

microphone and pass the AC signal to the amplifier.

C C


52/94

Capacitive Coupling: Bias Analysis


Since a capacitor is an open at DC, it can be replaced by an

open during bias point analysis.

2

21

2

2

1

THDDoxnD VV

RR

R

L

WCI

C iti C li AC A l i


53/94

Capacitive Coupling: AC Analysis


Since a capacitor is a short at AC, it can be replaced by a short

during AC analysis.

ODmin

out rRgv

v||

C iti C li I/O I d


54/94

Capacitive Coupling: I/O Impedances

212

1

||RRR

R

in

in


ODout rRR ||

E l A lifi ith Di ti C ti f S k


55/94

Example: Amplifier with Direction Connection of Speaker


This amplifier design still fails because the solenoid of the

speaker shorts the drain to ground.

E l A lifi ith C iti C li t I/O


56/94

Example: Amplifier with Capacitive Coupling at I/O


This amplifier design produces very little gain because its

equivalent output resistance is too small.

08.0||8||

spDmv

spDeq

RRgA

RRR

S D ti ith B C it


57/94

Source Degeneration with Bypass Capacitor


It is possible to utilize degeneration for biasing but eliminate its

effect on the small-signal by adding a bypass capacitor.

Dm

G

v RgRRR

RRA

21

21

||

||

E l S D ti ith B C it D i


58/94

Example: Source Degeneration with Bypass Capacitor Design

mVV

VV

VV

VAC

mWPower

KR

A

SR

DD

TH

oxn

in

v

400

8.1

0

5.0

/100

5

50

5

2


KRKR

R

LW

g

R

D

m

S

225,3.64

2463

864

3.461

148

21

Concept S mmar


59/94

Concept Summary


Common Gate Stage


60/94

Common-Gate Stage


In a common-gate stage, the input is applied at the source

while the output is taken at the drain.

Small Signal Analysis of Common Gate Stage


61/94

Small Signal Analysis of Common-Gate Stage


Dmv RgA

Example: Common Gate Stage Design


62/94

Example: Common-Gate Stage Design

VV

VV

VAC

LW

mAI

DD

TH

oxn

D

8.1

5.0

/100

50

5.0

2


06.6447171.2

vm

DTHbDDDD

AgkRVVRIV

Input Impedance of Common Gate Stage


63/94

Input Impedance of Common-Gate Stage


m

ing

R 1

The Use of Low Input Impedance


64/94

The Use of Low Input Impedance


The low input impedance of a common-gate stage can be used

to impedance match a 50-transmission line.

Output Impedance of Common Gate Stage


65/94

Output Impedance of Common-Gate Stage


DOout RrR ||

Example: Alternate A Expression of CG Stage


66/94

Example: Alternate Av Expression of CG Stage


in

outvR

RA

CG Stage in the Presence of Finite Source


67/94

Resistance


S

m

D

in

out

Rg

Rvv

1

Output Impedance of a General CG Stage


68/94

Output Impedance of a General CG Stage


SOSmDout RrRgRR 1||

CG and CS Stages Output Impedance Comparison


69/94

CG and CS Stages Output Impedance Comparison


SOSmDoutCSoutCG RrRgRRR 1||

Since when calculating the output impedance, the input voltage

source of the CG stage is grounded, the result will be identical

to that of a CS stage if the same assumptions are made for both

circuits.

Example: AV and R t


70/94

Example: AVand Rout


SmmDm

in

out

Rgg

Rg

v

v

21

1

1

= 0

DOSm

Omout

RrRg

rgR ||||1

12

11

> 0

Example: CG Stage Lacking Bias Current


71/94

Example: CG Stage Lacking Bias Current


Although the capacitor C1isolates the DC content of the signal

source, it also blocks the bias current of M1,hence turning it

OFF.

Example: CG Stage with Source Shorted to Ground


72/94

Example: CG Stage with Source Shorted to Ground


Although there is now a path for bias current to flow to ground,

the signal current also goes with it, hence producing no gain.

CG Stage with Proper Bias Circuitry


73/94

CG Stage with Proper Bias Circuitry


R1 is used to provide a path for bias current to flow without

directly shorting the source to ground.

However, it also lowers the input impedance of the circuit

1||1

Rg

Rm

in DmSmv Rg

RRgA

111

1

Input Current Flowing Paths


74/94

Input Current Flowing Paths


To maximize the useful current i2, R1needs to be much larger

than 1/gm.

mg

R 1

1

Example: CG with Complete Bias Network


75/94

Example: CG with Complete Bias Network


VVmWPower

g

RR

A

VV

VAC

DD

m

S

v

TH

oxn

8.1

2

50/1

500,0

5

0

5.0

/100

1

2

kRkR

R

VVIg

LW

VV

GG

D

THGSDm

GS

135,45

682

4.136/2

244

8.0

21

1


76/94


77/94

Source Followers Response to an Input Change


78/94

Sou ce o o e s espo se to a put C a ge


As the input changes by a small amount, the output will follow

the input and changes by a smaller amount, hence the name

source follower.

Small-Signal Model and Voltage Gain for Source Follower


79/94

g g


m

S

S

in

out

gR

R

v

v

1

Example: Source Follower with Current Source


80/94

p


AV

1vA

Source Follower Acting as a Voltage Divider


81/94

g g


m

S

S

in

out

gR

R

v

v

1

Complete Small-Signal Model with rO


82/94

p g O


m

SO

SO

in

out

gRr

Rr

v

v

1||

||

Example: Source Follower with a Real Current Source


83/94


m

OO

OO

v

grr

rrA

1||

||

21

21

Example: Source Follower with a Real Current Source


84/94


VV

VV

VAC

mWPowerA

R

DD

TH

oxn

v

S

8.1

0

5.0

/100

105.0

50

2

360

50

1

5.01

LW

g

Rg

RA

m

S

m

Sv

Output Resistance of Source Follower


85/94


SOm

out RrgR ||||

1

Example: Source Follower with Biasing


86/94


kR

VV

VV

VACA

mAI

G

DD

TH

oxn

v

D

50

8.1

0

5.0

/100

8.0

1

2

107

933.0

867

2

LW

VRIVV

RR

I

VV

R

A

SDDDGS

S

S

D

THGS

S

v

Source Follower with Current Source Biasing


87/94


In IC technology, source follower is often biased by a current

source to avoid the bias currents dependence on the supply

voltage.

Summary of MOS Amplifier Topologies


88/94


Example: Common Source Stage I


89/94


321

3

321

3

1

||||||1

||||||1

OOO

m

out

OOO

m

mv

rrrg

R

rrrg

gA

Example: Common Source Stage II


90/94


3

31

2

||11 Omm

Ov

rgg

rA

Example: CS and CG Stages


91/94


S

m

OvCG

OOSOmmvCS

Rg

rA

rrRrggA

1

2

11112

1

||1

Example: Composite Stage I


92/94


21

11

mm

D

v

gg

RA

Example: Composite Stage II


93/94


221

43

32

1

2

2

2

21

||11

||||1

1||

1

||1

Omm

OO

m

in

out

m

O

m

O

m

in

out

rgg

rrg

v

v

g

r

g

rg

v

v

Chapter Summary


94/94

The impedances looking into the gate, drain, and source of a

MOS are equal to , rO and 1/gmrespectively (under proper

conditions).

The transistor has to be properly biased before small-signal

can be applied.

Resistive path between the supply rails establishes the gate

bias voltage.

Only three amplifiers topologies are possible.

CS stage provides moderate AV, high Rinand moderate Rout.

Source degeneration improves linearity but lower AV.

Source degeneration raises the Rout of CS stage considerably.

CG stage provides moderate AV, low Rin and moderate Rout.

AVfor CS and CG stages are similar but for a sign.

Source follower provides AVless than 1, high Rinand low Rout,

serving as a good voltage buffer

Ch16 (1) electronics

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