Ch. 10 Central Processing Unit Designs - CISC Two CPU designs CISC Non-pipelined datapath with a micro- programmed control unit RISC Pipelined datapath with a hardwired pipelined control unit The Complex Instruction Set Computer Instruction set architecture Memory-to-memory access for data manipulation 8 addressing modes Two instruction format lengths Instruction with many operations Datapath Non-pipelined Control unit Microprogrammed control Register Set 0 Instruction Formats # of operands determine the addr. of operands amount of shifts New addr. placed in PC Addressing Modes offset S=0: SRC uses addressing mode S=1: DST uses addressing mode Datapath Organization modification Register file R0~R7: User accessible registers R8~R15: temporary storage for use by microprogram R12~R15: registers for specifying standard locations B addr. : for source A A,D addr. : for source B or destination Modification to Shifter Modification for arithmetic shift and rotate operations Sign bit Logical shift Arithmetic shift Rotate: circular shift 0 0 s 3 s 2 s 1 s 0 PC, SP PSR Memory Through Bus D Through MUX A, Bus A Through MUX B, Bus B Datapath Microstatus register - store PSR values for microprogram level - cf) PSR register: for program level Microprogrammed Control Design Sequencing Microsequencer Next-address generator + control address register (CAR) SBR: subroutine branch register Micro-routine Subroutine for microprogram Single-level cf) multi-level call in program level SBR Store the next address for CAR at the time a micro- subroutine is entered. Microinstruction Formats Format A: data transfer, manipulation decode instruction return from microsubroutine Format B: change the flow of the microprogram (branches and microsubroutine call) To datapath Microinstruction Formats Related to carry Zero-filled constant from SB field Microinstruction Formats Opcode Instruction decoder CAR Microinstruction Formats Microsequencer Q) When is SBR loaded with CAR++? Branch (MC=11) prevent the writing of register file Microinstruction Formats MM field Define which field of instruction is involved in determining the addr. Provided MR field Provide distinct sets of addresses for the same IR fields Microinstruction Formats MR : region 1regin: 64 addresses Microinstruction Formats Microprogram Structure