CES 2013 Everspin Presentation (1)
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Transcript of CES 2013 Everspin Presentation (1)
Accelerating Data Storage
Everspin – The MRAM Company
MRAM - Magnetic Random Access Memory Ø Fastest non-volatile memory with unlimited endurance
Only company to have commercialized MRAM
Established 2008, 100%+ annual revenue growth
Fundamental & essential MRAM IP Ø 600+ Patents & Applications WW, 220+ US Patents granted
Backed by top-tier VCs
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Our Customers
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Recognized Everspin for Perfect MRAM Quality 250k+ systems with no reported failures to-date
Critical Storage for Industrial Computing Boards Robust & reliable non-volatile memory solution
MRAM products for A350 Flight Control Computer Critical program and data storage in extreme environment
Non-volatile memory for Superbike Engine Control Reliable power fail safe memory for automotive temperature
MRAM used as write journal for RAID Storage Power fail recovery increasing system reliability & uptime
MRAM is Everywhere
Data Center & Storage�
Energy & Infrastructure
Automotive & Transportation�
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48-BGA Ø x8 Asynchronous parallel I/O Ø x16 Asynchronous parallel I/O Ø x8 Asynchronous parallel 1.8V I/O
44-TSOP2, 54-TSOP2 Ø x8 Asynchronous parallel I/O Ø x16 Asynchronous parallel I/O
8-DFN Ø SPI-compatible serial I/O Ø 40 MHz; No write delay
32-SOIC Ø x8 Asynchronous parallel I/O
Current MRAM Products
16-bit I/O Part Number Density Temp
MR4A16B 16Mb 1M x 16 C,I,A
MR2A16A 4Mb 256K x 16 C,I,E,A
MR0A16A 1Mb 64K x 16 C,I,E,A
8-bit I/O Part Number Density Temp
MR4A08B 16Mb 2M x 8 C,I,A MR2A08A 4Mb 512K x 8 C,I
MR0A08B 1Mb 128K x 8 C,I
MR256A08B 256Kb 32K x 8 C,I MR0D08B 1Mb 128K x 8, 1.8v I/O C
MR256D08 256Kb 32K x 8, 1.8v I/O C
SPI I/O Part Number Density Temp
MR25H40 4Mb 512K x 8 I, A
MR25H10 1Mb 128K x 8 I, A
MR25H256 256Kb 32K x 8 I, A
Temperatures Commercial 0 to +70 ºC
Industrial -40 to +85 ºC
Extended -40 to +105 ºC
Automotive -40 to +125 ºC
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MRAM Adoption Accelerating
7.0M+
MRAM Shipments
MRAM Customers
MRAM Design Wins(1)
MRAM Applications
MRAM Products
500+ 100+ 100+ 200+
(1) New Design Wins in CY2012
7M
13M
0
2
4
6
8
10
12
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16 Everspin Toggle MRAM Cumulative Shipments (Mu)
* Projections
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2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
Spin Torque MRAM
64Mb DDR3
Serial SPI Compatible
256Kb, 1Mb
4Mb
Next Gen Hi-Speed
SRAM Compatible
SOIC
256Kb, 1Mb (x8)
SRAM Compatible
BGA
256Kb, 1Mb,4Mb (x16 x8)
1 Mb,256Kb 3.3/1.8V
(x8)
16 Mb (x16)
16 Mb (x8)
ST-MRAM
SRAM Compatible
TSSOP
4Mb (x16)
1Mb (x16)
256Kb, 1Mb, 4Mb (x16 x8)
1 Mb,256Kb 3.3/1.8V
(x8)
16 Mb (x16)
16 Mb (x8)
ST- MRAM
Product Roadmap
Production
Sampling
Design
Concept
Pre-Production
Rapidly Increasing From Mb to Gb Density
Increasing density and speed
Increasing density as defined by market requirements
Increasing density as defined by market requirements
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Spin-Torque – Next Generation MRAM
Current Toggle MRAM uses a magnetic field for switching
Next generation MRAM enables scaling to Gb densities Everspin on track to deliver industry’s first ST-MRAM
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Toggle Write Spin-Torque Write
Everspin Introduces the 64Mb DDR3 ST-MRAM
CCEESS 22001133
ST-MRAM
^ST-
What we’ve announced Everspin debuts first Spin-Torque MRAM for high performance storage systems, The EMD3D064M - 64Mb DDR3 ST-MRAM A new type of high performance and ultra-low latency memory that will transform storage architecture A performance-optimized Storage Class Memory (SCM) that bridges the role of today’s conventional memory with the demands of tomorrow’s storage systems Provides non-volatility and high endurance
Compatible with the industry standard JEDEC DDR3 specification 1600 million transfers per second per I/O, Bandwidth of 3.2 GBytes/second
Select customers are now evaluating working samples.
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ST-MRAM
^ST-
Product Overview 64Mb DDR3 ST-MRAM
Non-volatile 64Mb DDR3
DDR3-1600 ST-MRAM
16Mbx4, 8Mbx8, and 4Mbx16 configurations
Supports Standard DDR3 SDRAM Features
No refresh required
Burst length: 8 (programmable Burst Chop of 4)
DDR3 SDRAM Standard FBGA Package Pinout:
VDD = 1.5V +/-.075V
On-device termination
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ST-MRAM
^ST-
Building the ST-MRAM Eco System
FPGA Evaluation Boards Using DDR3 ST-MRAM DIMMs DDR3 ST-MRAM controller IP Enabling Memory Subsystems Enabling Storage Subsystems
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Why it’s needed
Scalability Issues: Application Performance degrading
Faster & consistent data storage access is needed to deliver acceptable performance
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MORE DATA + MORE USERS + INSTANT ACCESS
What the industry is saying
Three new low latency memories on the horizon:
Ø Phase Change Memory, Memristor and Spin-Torque MRAM
Processor architectures & filing systems need dramatic redesign to take advantage of new NVM technologies
Systems must be ready for low latency NVM in 3-5 years
Huge power savings and much faster data transfer
Changing the memory hierarchy has huge knock-on effects on how computation works!
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Justin Rattner, CTO Intel, IDF 2012 San Francisco
Bifurcation of Moore’s Law
Continuous demand for exponential cost declines in computational power and storage density
Radical advances in memory density & performance will relieve processor memory performance bottleneck
Processor chips dominated by memory, not logic
Long wait time when accessing off-chip memory
Big Data driving $28B of IT Spending in 2012
Ultra-low latency MRAM extends Moore’s Law 15
Compute needs ultra-low latency NVM
NAND improved storage I/O performance & latency
BUT still several orders of magnitude latency GAP
ST-MRAM is closest to RAM and to high volume mass production
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late
ncy
(ns)
10-1 100
CPU RAM
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TAPE DISK
106 104
NAND MRAM
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Delivering 10x better Price/Performance
Cloud Storage Needs: Ø More content & users, instant access Ø Better response times from storage Ø Predictable balanced performance
Nanosecond-class MRAM Storage
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…at only 50x Cost/GB
500x Performance…
NAND SSD MRAM SSD
Key Metrics NAND MRAM Density 64Gb 1Gb Latency 50us 45ns 4kB Write IOPS 800 400k Cost/GB 1 50
Delivering 100x Power/Performance
Data Center needs: Ø Number of servers & CPU cores exploding Ø Better bandwidth & IOPS to handle Big Data Ø More performance @ less power to scale up
High Performance, Power-Efficient MRAM Storage
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Key Metrics NAND MRAM Density 64Gb 1Gb Power 80mW 400mW 4kB Write IOPS 800 400k Cost/GB 1 50
…at only 5x Power
500x Performance…
NAND SSD MRAM SSD
Faster, more reliable Enterprise Storage
Enterprise Storage: Can’t lose data if power fails! Historically using batteries/caps to protect data in RAM
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Areas of concern DRAM with battery/caps Spin-Torque MRAM Write performance Temporary persistent cache Truly persistent write cache
Complexity Power fail circuitry Simplified system
Reliability Lifetime reliability issues Truly persistent RAM
Form factor Large battery/caps No battery/caps
Temperature Commercial Automotive
Environmental Battery/caps concerns Truly green storage
Storage Solutions craving ST-MRAM
ST-MRAM complements solid state & magnetic storage Improved response time due to low latency & high bandwidth
ST-MRAM as Buffer Memory MRAM instead of low density DRAM
Better performance & reliability
ST-MRAM as I/O & Network Cache MRAM instead of NV-DRAM
Better reliability & overall TCO
ST-MRAM as Fast Storage-Tier MRAM in addition to SSD/HDD
Better IOPS/$/W & reliability 20
Multi-billion dollar market opportunity
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Advancing Storage Architecture
Storage OEMs are tuning storage to application needs Ø Capacity, Performance, Power, Uptime/Service and Reliability Ø OEMs need to balance storage capacity and performance
Ø HDD leveraged as capacity optimized data storage q Benefits : Lowest cost per GB/TB for data storage q Challenges: Random access, active power & power fail
Ø NAND SSD leveraged as performance optimized storage q Benefits : More IOPS, reduced latency & less overall power q Challenges: Write latency & variability, endurance, power fail
Ø ST-MRAM leveraged as non-volatile buffer/cache for storage q Benefits : DRAM like access, unlimited endurance & power fail q Challenges: New storage architecture, density & cost scaling
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Positioned for Extraordinary Growth
Proven track record - manufacturing MRAM since 2006 Top tier 1 customers – Dell, LSI, Siemens, BMW, Airbus etc… Deployment in many applications with exemplary quality
Continued MRAM leadership Leadership ST-MRAM R&D with initial silicon demonstrated
Establishing 300mm ST-MRAM capacity to reduce cost Asset light approach in collaboration with partners
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CCEESS 22001133