Central Processing Unit - Neff · 2017-03-14 Module 4.1.2 –Central Processing Unit 3 Operand...
Transcript of Central Processing Unit - Neff · 2017-03-14 Module 4.1.2 –Central Processing Unit 3 Operand...
Components (1)
• Block diagram
– Execution Unit
• Control Unit
• Registers
• Arithmetic logic unit– ADD, SUB etc.
– NOT, AND etc.
– Bus Interface Unit
Module 4.1.2 – Central Processing Unit
CPUExecution Unit
ControlUnit
Registers
ALU
Bus Interface Unit
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Components (2)
• Arithmetic logic unit
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Operand Fetch
Source
R1, R2
+
R0
Execute
Operation
Write Back
Destination
Result = Operand1 Operator Operand2Destination = Source1 Operator Source2
Operator (+)
Register
Operand 1 (R1)
Register
Operand 2 (R2)
Register
Result (R0=R1+R2)
Arithmetic LogicalUnit
Components (3)
• Structure of Control Unit
Module 4.1.2 – Central Processing Unit
Storage
007h006h005h
003h004h
002h001h000h
Control Unit
Instruction Decode
Instruction Fetch
Operand Fetch
Execute
Write Back
Next instruction to be executed
Instruction Pointer
Instruction Register
Currently executed instructionRegisters
ALU
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Components (4)
• Instruction pipeline (details: module 1.3)
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Instruction Pipeline stage
1 IF ID OF EX WB
2 IF ID OF EX WB
3 IF ID OF EX WB
4 IF ID OF EX
5 IF ID OF
Clock 1 2 3 4 5 6 7
Parallel execution of five instructions
Register Machines (1)
• Theoretical model
Module 4.1.2 – Central Processing Unit
Central Processing Unit
Instructions
1…
2…
3…
0…
Data
1…
2…
3…
0…
Accumulator Instr. Pointer
Input Tape… … …
Output Tape… … …
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Register Machines (2)
• Program Execution
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Central Processing Unit
Instructions
1add 1
2store 2
3stop
0load 0
Data
12
2free
3free
01
? 0
Store data at memory location(mem[2] = acc)
Load data from memory location(acc = mem[0])
Register Machines (2)
• Program Execution (continued)
Module 4.1.2 – Central Processing Unit
Central Processing Unit
Instructions
1add 1
2store 2
3stop
0load 0
Data
12
2free
3free
01
1 1
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Register Machines (2)
• Program Execution (continued)
Module 4.1.2 – Central Processing Unit
Central Processing Unit
Instructions
1add 1
2store 2
3stop
0load 0
Data
12
2free
3free
01
3 2
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Register Machines (2)
• Program Execution (continued)
Module 4.1.2 – Central Processing Unit
Central Processing Unit
Instructions
1add 1
2store 2
3stop
0load 0
Data
12
23
3free
01
3 3
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Register Machines (2)
• Program Execution (finished)
Module 4.1.2 – Central Processing Unit
Central Processing Unit
Instructions
1add 1
2store 2
3stop
0load 0
Data
12
23
3free
01
3 4
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Instruction Set (1)
• Instructions
– Statements of a program
– Stored storage
– Specify operation, source and destination
Module 4.1.2 – Central Processing Unit
StorageControl
Unit
Instruction
Data Operation
Registers
ALU
Source
Destination
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Instruction Set (2)
• Machine Language
– Specific for every microprocessor
– Set of instructions understood by these processors
– Represented by numeric operation codes
– Example:
• Operation: ADD
• Source: R0, R1
• Destination: R0
• Opcode: 0C01hex
Module 4.1.2 – Central Processing Unit
0000 1100 0000 0001
R0ADD R1
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Instruction Set (3)
• Assembly Language
– Opcodes replaced by textual mnemonics
– Source code is readable
– Has to be compiled
– Major benefits:
• Easier to read
• Comments allowed
• Variables names
• Labels
Module 4.1.2 – Central Processing Unit
; z=x+y
LDS R0,x
LDS R1,y
ADD R0,R1
STS z,R0
EXAMPLE.ASM
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Instruction Set (4)
• Instruction Set
– Instructions for the ALU
• Arithmetic Instructions: ADD, SUB, MUL, CP, …
• Logical Instructions: AND, OR, EOR, COM, …
• Shift and Rotate Instructions: LSL, LSR, ROL, ROR, …
• Bit Manipulation Instructions: SBI, CBI, CLI, SEI, …
– Instructions for the Control Unit
• Data Movement Instructions: MOV, LD, ST, PUSH, …
• Branch Instructions: RCALL, RET, BRcc, …
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Instruction Set (5)
• Complex/Reduced Instruction Set Computing
Module 4.1.2 – Central Processing Unit
– CISC
• Complex instructions
• Many instructions
• Few registers
• Many cycles per instruction
• No pipelines
• Example– INTEL x86
– RISC
• Simple instructions
• Few instructions
• Many registers
• One cycle per instruction
• Pipelining
• Example– SUN SPARC
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Stack (1)
• Operating mode
Module 4.1.2 – Central Processing Unit
33
32
31
R0
R1
30
free
RAMEND
SP
PUSH R0PUSH R1
POP R1POP R0
RAMEND
SP 33
32
31
30
free
free
free
R1
R0
R1
R0Do something
Store Restore
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Stack (2)
• Summary
– Used to store temporary data.
– Is a last-in-first-out (LIFO) memory.
– Grows from up to down.
– Stack pointer points to the last element.
– Two special instructions
• PUSH: Decrement Stack pointer, put element on Stack.
• POP: Get element from Stack, increment Stack pointer.
• PUSH/POP: Pre-decrement / post-increment.
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Stack (3)
• Application: functions
– Are defined and called
– Alter sequential control flow
– Return to caller
• Many callers possible
• Return address has to be stored
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Call Return
Definition
Main Program
Function
Stack (4)
• Execution
CALL …
RET
…
…
…
original IP
…
free
SP
IP
IPSP …
…
…
…
free
free
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Stack (5)
• Compilation
Module 4.1.2 – Central Processing Unit
int i;
void inc(void)
{
i = i+1;
}
int main(void)
{
i = 1;
inc();
inc();
}
CPU
0load #1main
1store i
2call inc
3call inc
4stop
5load iinc
6add #1
7store i
8return
9undef.i
A
B
Instr. Pointer
Accumulator
Stack Pointer
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Stack (6)
• Execution
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
9i
A
B
B Stack Pointer
Accumulator
0 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
9i
A
B
B Stack Pointer
1 Accumulator
1 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
91i
A
B
B Stack Pointer
1 Accumulator
2 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
91i
A3
B
A Stack Pointer
1 Accumulator
5 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
91i
A3
B
A Stack Pointer
1 Accumulator
6 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
91i
A3
B
A Stack Pointer
2 Accumulator
7 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
92i
A3
B
A Stack Pointer
2 Accumulator
8 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
92i
A3
B
B Stack Pointer
2 Accumulator
3 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
92i
A4
B
A Stack Pointer
2 Accumulator
5 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
92i
A4
B
A Stack Pointer
2 Accumulator
6 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
92i
A4
B
A Stack Pointer
3 Accumulator
7 Instr. Pointer
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Stack (6)
• Execution (continued)
Module 4.1.2 – Central Processing Unit
CPU
0load #1main
1store 9
2call 5
3call 5
4stop
5load 9inc
6add #1
7store 9
8return
93i
A4
B
A Stack Pointer
3 Accumulator
8 Instr. Pointer
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