Cellot Proprietary Slide-0 Cellot Inc. The presentation was created with Microsoft PowerPoint 2003....

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>>> From Idea to Product <<<>>> From Idea to Product <<<

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From Idea to Product & ASICFrom Idea to Product & ASIC

Development DemonstrationDevelopment Demonstration


The following is a demonstration for using the FPCL Developer Environment to develop an application:

The demonstration utilizes schematic capture and CSL (Cellot Simulation Language).

The target application is a simple FIR filter: 8 Tap, 8 Bit (19 Bit out)

Introduction

>>> From Idea to Product <<<>>> From Idea to Product <<<

Please note:

Italic fonts are used for additional explanation

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Check the Idea (the theoretical solution):Define the application and check that the idea is feasible.The result can be used as a reference to the needed application.

Implement the application.The result is a downloadable code.

Development Steps

There are two steps in the “From Idea to Product” procedure:

This presentation shows how a user implements the application.

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Container is an FPCL Object tool that can hold other (subordinate) Containers and / or Functions (Shown graphically on next slide).

Functions are stored in Gates.The input of the gate is the input of the function. The output of the gate is the output of the function.

Containers and Gates

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Container

Developer Environment

Function

FPCL mappingContainer Container

Function

Container

Container Container

Function Function

Application

Container

Sub Applicatio

n

Cell

CompilerEliminates Containers

Library

Connections

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The user starts with an empty page which is the Schematic View of the Application Container.

When the user double-clicks the Container’s representation (icon) it enters into the Container's schematic diagram. This enables inserting the subordinate Containers, the Gates holding the functions and documentation.

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This is an empty page ready to insert the application

The user adds a heading …

!

8 Tap 8 Bit FIR Filter

Choose “Documentation” from the “Library” menu …

The user double-clicks the documentation icon for the documentation sheet to appear

Opens an “Explorer type” window from which the user can choose an empty documentation sheet.

and continues with documentation:

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The user inserts the documentation in this documentation sheetand returns back to the upper schematic diagram of the upper container

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8 Tap 8 Bit FIR Filter

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The schematic now includes the Container heading and an icon for the documentation.

During the idea definition and analysis process, the user:

Creates the filter function using float numbers.

Converts the float into integer resulting in a model of the application which applies the exact needed result.

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The user creates a Container to hold the reference (float type) application

adds a grid, resizes the Container icon to the appropriate dimension and adds text to define the Container. The result is shown in the next slide.


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The user adds float type input and output pins


Right click

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Similarly, the user adds a float type output pin

The Container for the float filter which has just been created is not empty: it shows the two pins the user added. These two pins are automatically inserted into the Container schematic diagram.

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The user double-clicks on the Container to edit its schematic diagram


Double-Click

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Locate the gate,

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The input and output pins are already inserted.

The filter formula is:

Y = (X0+X7)*h0 + (X1+X6)*h1 + (X2+X5)*h2 + (X3+X4)*h3

This means a function (gate) with 8 (float) inputs (X0 – X7) and one output (Y)

Please c l i c k y o u r m o u s e to see how the function (gate) reference is implemented:… and adds 8 float inputs and 1 float outputs

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The user connects the function gate output to the automatically created output pin

Right click

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The Gate is ready to host the function:

Y = (X0+X7)*h0 + (X1+X6)*h1 + (X2+X5)*h2 + (X3+X4)*h3

where:

h0, h1, h2, h3 are constants provided by the application engineer.

X0, X1, … X7 are the gate inputs.

X0 is the filter input

Any other Xn is the Xn-1, delayed by one clock.

The next slide demonstrates creation of the Delay:

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The user inserts one float input pin and eight float output pins …

… and connects the pins

The user double-clicks on the “Delay” Container to enter into its schematic diagram

Double-Click

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A delay is achieved by routing a signal via a register.

This register has float input and float output!

The overall delay is achieved by routing the input signal via 8 registers:

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Right Click

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Again, the schematic of the “Delay” Container is not empty: the pins are already there.

Clicking this button enables the user a multiple paste operation


The user exits insertion mode and connects the lines

and back to the float filter schematic diagram

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By now, you’ve seen the schematic diagrams of the following: original schematic diagram, filter, documentation and delay.

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TopContainer

DocFloatFilter

Delay FilterFormula

The top level is the top container hosting the original schematic diagram.

To help navigating in the application, the user activates the “Auto Expand” feature in the left bar:

Reg Reg Reg Reg Reg Reg Reg Reg


Clicking on this icon leads the user to the upper schematic diagram. The user can continue clicking until reaching the Top Container.

The Top Container (to be presented later) is the only Container not included on any schematic diagram.

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The last step to complete building the float reference filter is to insert the function code.

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Right Click

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float fFirFilter(float fI0, // The filter input float fI1, // The filter input delayed 1 time float fI2, // The filter input delayed 2 times float fI3, // The filter input delayed 3 times float fI4, // The filter input delayed 4 times float fI5, // The filter input delayed 5 times float fI6, // The filter input delayed 6 times float fI7) // The filter input delayed 7 times{ // Brief: Calculate a filter output sample according to the filter formula // Get: 8 float inputs, each is delayed one clock after the other // Return: float calculation of the formula

// The Band-Pass Filter coefficients (the ‘:’ note means definition) // ~~~~~~~~~~~~~~~~~~~~~~~~~ K0 : -0.09112012; // LP: -0.05418289 // BP:-0.09112012 K1 : -0.2961822; // LP: -0.09458317 // BP:-0.2961822 K2 : -0.08889319; // LP: 0.1416305 // BP:-0.08889319 K3 : 0.4576864; // LP: 0.4554365 // BP:+0.4576864

return (fI0 + fI7)*K0 + (fI1 + fI6)*K1 + (fI2 + fI5)*K2 + (fI3 + fI4)*K3;}

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The filter is now ready and needs to be tested.

In order to test the filter, the user needs a generator. The user uses an FM generator to test the application.

The user can use a ready-made FM Generator from the library, or build one.

The method of creating the generator is the same as creating the filter or any other application.

In this demonstration, a ready-made FM Generator from the library is used:

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Opens an “Explorer type” window from which you can choose the appropriate saved application

The user connects the FM generator output to the reference Filter input

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Have you noticed?

When the line is connected, the icon which indicates an error in the application disappears.

Lets see this again:

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The user connects the FM generator output to the Filter (reference) input

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This happens as there is a thread compiling the application, even during editing which saves the user compilation time.

Nevertheless, the user can compile any function or Container independently:

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Right click

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If there is an error, the user will get a detailed message similar to the following:

The user can scroll down the message box to see more details

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Now it’s time to see the results:

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Right click

FM and Filter Reference

Double-click

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In the following slide, the user can drag and drop any pin or connection point from the schematic diagram to the simulation window.

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DragDrag

Drop

Drop

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Using the same tool, the user creates the integer implementation (with the exact same formula)

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Right click

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The procedure of changing the pins and the formula from float to integer is not shown.

However, the outcome of such operation is shown (Schematic and code, side by side):

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So this is the same formula but using integers.

The integer input size used is 8 bits. This result in an output (according to the formula) of 19 bits.

You may have noticed that the color of the lines and pins have changed from purple to black. This is because purple represents float and black represents “Bits”. Blue represents a 64-bit integer.

The Container color convention is: white : there is no register in the Container (purely functional).gray: contains registers.light gray: a Cell. Contains one function and one register

The user may change both the Container color and the color convention.

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At this point, the application needs to be connected to the same FM generator. However, the FM generator provides float signal and the input to the new application is integer, therefore the user will add a float to 8-bit integer converter. The user will get this converter from the library

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Opens an “Explorer type” window from which you can choose the appropriate saved application

Right click

Right click

Right click

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and the results (after creating a new simulation window):

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Drag

Drop

Drag

Drop

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What do you think should be dropped?

The integer at the output is 19 bits.

Bits, in general, do not represent a value: the ‘Bits’ can represent collection of flags, PCM, log value, , float, char, string or anything else. Only the user knows what these bits represent. Therefore, beside the defaults provided, the user can add any formula to convert the bits into the appropriate value.

But not only this: the Bits can be presented as a collection to form an integer or in “Logic Analyzer” style, bus style, histogram or other.

While dropping a “Bits” signal, the user is forced to explicitly define the needed representation:

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The conversion to ‘Int’ is OK

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Although it seems similar, a close look (Zoom In) will show the differences:

The user may place the integer result figure over the float result figure

The user can create a function to automatically compare the two results

In this case the user chooses to compare by placing one graph over the other and zooms in the result:

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The user may try integers with different bit counts and compare each result to the float reference.

When satisfied with the “Integer” application, the user implement the application. The result is a downloadable code.

The following is a less detailed presentation starting with the Top Container.

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Remainder: The reference is:

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Only two different application Containers have to be implemented: Multiply - accumulator [1]

4 inputs - adder [2]

The 4 left Containers in the next slide are equivalent (implementing [1] )

Implementation

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In the code for one of the four multiply-accumulators: ‘d17CombineAndMultiply’ (see slide above) there is a line marked out:

// int iResult = iIntPart(fResult)

If this line is activated to replace the following line (which is doing round rather then integer) even in one Container, the 19-th bit is not accurate. This shows the accuracy the FPCL Developer Environment can achieve.

Following is the result of the second (Integer) filter implemented with that line (changed in only one multiply-accumulator) compared with the result of the filter implemented for downloading to the FPCL device. The engineer can see that the result is not accurate enough. By not changing that line, the results are absolutely identical.

Implementation

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In this presentation we have tried to show the simplicity of the implementation process. Hopefully, we did not cloud the issue with too many details as

the actual application comprises only on the following three slides:

58, the filter schematic diagram (resides in its Container)59, the multiply-accumulator and

63, the 4 inputs adder.

These three applications / sub-applications are stored in the Library for future use.

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Any Container can be independently implemented by Code or Schematic Capture or in Script or by importing from other environments (e.g. C++) or a combination of all of these. The demonstration uses both CSL (Cellot Simulation Language) code and schematic capture.

If C++ is used, the third party developer environment (such as the Microsoft Visual C++) is used and the compiled result is integrated into the FPCL Developer Environment.

If Verilog is used, the FPCL Developer Environment compiles the code.

Supported Languages

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Thank youThank you

Cellot Proprietary Slide-0 Cellot Inc. The presentation was created with Microsoft PowerPoint 2003....

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