CDFG for free HDL compiler as refenrece VCD file dumper Said Mchaalia Dortmund, September 2000
Transcript of CDFG for free HDL compiler as refenrece VCD file dumper Said Mchaalia Dortmund, September 2000
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FreeHDL Compiler Control Data Flow
Graph and its application in waveformcompression
Said Mchaalia
August 18, 2012
1 Intention of this document
In this document, we try to present an idea of using Control Data
Flow Graph (CDFG) to improve waveform compression.
A waveform file is a VCD (Value Change Dump) file, which is divided
in two parts: header that contains general information, which are
version, date,.. and kernel, which contains signal values belong to
each simulation step and simulation time.
Figure ?? describes a VCD file. Notice that each parameter is coded
with an ASCII code composed of 1 to 4 characters depending on the
number of parameters inside considered VHDL model. For eachVHDL model, the simulation time is written before the parameter val-
ues. For example: #0 and #100 represent the simulation times 10
and 100 us. The character b preceded parameter value describes
that this parameter value is a binary format. Thereby all parameter
values will be transformed to a binary format before that they will be
written in the VCD file.
To compress a VCD file, many techniques are developed. The basic
idea of these techniques is inspired from the Lempel-Ziv and the oth-
ers algorithms for data compression [4]. Mainly, five algorithms that
are Time-Value Separation, Time Compression Technique, Value
Compression Technique, Strength Reduction and Cross Signal StrengthReduction (see [1] and [2]) are developed to allow a suitable VCD file
compression.
The object of this work is to get out an idea of using CDFG for devel-
oping a new waveform compression algorithm. In following sections,
we will describe this idea and present its features.
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$date
Sep 26 2000 16:28:52
$end
$version
FREEHDL 0.1
$end
$timescale1 us
$end
$scope module struct $end
$var reg 8 ! qsig2[8:1] $end
$var reg 8 " qsig[8:1] $end
$var trireg 1 ? clk $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b110100 !b110100 "
b0 ?
#100
b110100 !
b1 ?
$end
Figure 1: VCD File
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2 An overview of waveform compression technique
The basic idea of waveform compression is finding a method that
reduces waveform file sizes in order to get more storage space for
further use.
The actual waveform compression techniques are described in [1]
and [2].
3 Control Data Flow description
The Control Data Flow Graph is a graphical representation, which
identifies each statement in a given program with a graph. A CDFG is
composed of edges, which represent data and/or control and nodes
that identify arithmetic and/or logic operations[3]. Figure ?? repre-sents a CFDG of VHDL model.
4 CDFG and its application in waveform compression
The object of using CDFG is to develop a compression algorithm
based on interpreted graphical information. In this section we detail
the different waveform compression cases in which the CDFG will be
used.
4.1 Dependency Schedules
In this section, we will deal with the dependency between signals
and/or variables and dependency between processes. This section
is divided in two main subsection: however the first section treats
the case of the dependencies between signals and/or variables, the
second one interests the dependency between processes.
4.1.1 Signal dependency schedules
We know that CDFG gives a knowledge a priori of relationships be-
tween signals and variables inside a given VHDL model. Due to this
information, we can minimize the data storage. For example let con-sider the VHDL model described in figure ??. We see, that the signal
c is depended on whether the signals a and/or b change values or
not. So, we can use such an information to reduce the stored infor-
mation belong to considered waveform. Thereby, we do not need to
store the c signal value and we should just store the a and b signal
values. In the other hand, notice that the signal d is depended on
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process(a,b)
begin
c
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Let us consider the new relation as follows:
c(n) = f(a(n1), b(n1)) (3)
where f(x, y) a logical function, which is defined as follows:
f(x, y) = x XOR y (4)
as the first relation between signals c, a and b.
d(n) = f(c(n1), a(n1)) (5)
where f(x, y) a logical function, which is defined as follows:
f(x, y) = x AND y (6)
as the second relation between signal d, a and c.
Where n is the nth clock signal (clk) cycle.
4.1.2 Process dependency schedules
In this section, we will try to give an idea how the CDFG can solve
the dependencies between processes inside the same VHDL model
and how which information will be used in the waveform compression
techniques.
Let us look at the example of figure ??, we see that the three pro-cesses P1, P2, and P3 are depended each of the other. Based onthe CDFG of each process and on the knowledge that all processes
inside the same VHDL model have the same Read Signal and
Write Signal nodes, we can involve some relationships between
signals inside different processes to make a suitable optimization of
the waveform compression.
Figure ?? describes the CDFG of the VHDL model represented in
figure ??. We see that, the CDFGs allow us to get information about
the dependencies between signals inside theses processes and so
to achieve the needed optimization, which is the storage of signal a
and all relationships between considered signals such as:
b = f(a, 1) (7)
where f(x, y) a logical function, which is defined as follows:
f(x, y) = x XOR y (8)
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P1: process(a)
begin
b
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S(n+1) = f(Si(n), Sj
(n))) (13)
Wheref(.,.,.)
represents a mathematical multi-variable func-
tion.
The more complex case is the case where each process hasits own clock signal. In this case, we must define a relation-
ship between all clock signals, and try to write the other clock
signals function of the first one for example. If we suppose
for example that the clock signal clkk is slower k times thanthe clock signal clk0, and the clock signal clkp is p times fasterthan signal clock clk0, we can write the following relationshipsbetween the distinguished clock signals:
clkk = k clk0 (14)
clkp = 1/p clk0 (15)
The relationships between signals inside theses processes will
be defined as follows:
Sl0(n) = f0(Si0
(n1), Sjk(E((n1)/k)), Shp
(p(n1))) (16)
Where E(x) is a function, which is defined as follows:
E(x) : IR > IN : x | > n such as : n 1 < x
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P1: process
begin
if clk0rising_edge then
b
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Suppose for example that:
clk1 = 3 clk0 (20)
and
clk2 = 0.5 clk0 (21)
To involve the relations between signals that are defined previously,
we can consider these equations:
b(n+1) = a(n) XOR 1 (22)
Where n is the nth clock signal clk0 cycle.
c(k+1) = b(k) N OR 1 (23)
Where k is the kth clock signal clk1 cycle.
d(m+1) = c(m) XOR 1 (24)
Where m is the mth clock signal clk2 cycle.
Indeed, we can use these equations to minimize data storage. Thereby,
we can just store the signal value a and these relations between dif-
ferent clock signals clk0, clk1 and clk2, and signals a, b, c and d.
Notice that these relations will be stored just only once a time dura-tion the VHDL model simulation.
4.2 CDFG and Waveform Decompression
In this section, we will describe how the CDFG will be used in the
complex cases to improve the waveform compression techniques.
4.2.1 Compromise between decompression and signal depen-
dencies
In the previous section, we treated the case of signal dependenciesand the involved solution based on the CDFG research. In section
4.1.1, we developed an algorithm that searches whether a signal will
be stored or not. Indeed, the storage of signal values needs a knowl-
edge a priori of the signal dependencies. Thereby, a signal value will
be stored only when this signal is independent from all other sig-
nals defined inside a given VHDL model. On the other hand, section
4.1.1 involves that only the relationship in their mathematical forms
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between signals will be stored, because this will be done just once
a time during a simulation process of waveform compression. Al-
though, it is hard to achieve this task during the decompression pro-
cess. Thereby, we do not know exactly the complexity of considered
mathematical functions, which link the signals to each other. In the
most case of complex VHDL models, we have mostly very complex
mathematical functions that belong a set of signals to a defined sig-
nal. This will make the process of decompression very complex and
it will take a great schedule time.
To solve this problem, we try to find an optimized solution for the
waveform compression techniques based on the signal dependen-
cies.
This solution is described as follows:
in the case of a signal that depends of a set of signals: find analgorithm that searches to store all needed signals based onoperation numbers that identify the signal values. Thereby, let
consider the signal Sk that depends on a set of signals. Thissignal will be written as follows:
Sk = fk(Sp0 ,...,Spi , Sj,...,Sn) (25)
where Sp0 ,...,Spi are independent or primery signals and Sj,..,Snare signals that depend of each other and the other signals.
For example, let consider the following signal dependencies:
Sj = fj(S1,..,Sl) (26)
Sm = fm(S3, S2) (27)
Sl = fl(S0) (28)
Sn = fn(S0, Sh, Sm) (29)
In section 4.1.1, we will just store the signals that do not de-
pend of any other signal. For example Sp0 ,...,Spi . There-fore, the decompression process complexity will depend on the
complexity of the functions f0(),...,fn(). Notice that these func-tions can be as complex as possible and so the decompression
task will be so complex. To solve this problem, we can precede
as follows:
first, store all independent signals.
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Figure 11: Complexity of dependency functions function of signal
numbers
secondly, in the case of dependent signals: see whetherthe dependency function fi() : i = 1...n and i kis complex or not. If it is simple then do not store the
corresponding dependent signal Si. Figure ?? representsthe graph of the complexity of dependency functions.
In figure ??, we see that the complexity Cij of dependencyfunction fi() depends on the number of signals j that are con-tained in this function. If this number is higher than the com-
plexity is lower and vice versa. This means that, in this case
of dependent signals, we must search the signal number to be
stored in order to reduce the complexity of the decompression
process. In the figure ??, we see that for a given dependencyfunctions that depend on m signal, we can find the suitablesignal number k such as k < m with which we can get anoptimized complexity of all considered dependency functions.
So, our object is to develop an algorithm that returns the signal
number k, which their values will be stored to allow a simplerestoration of the other signals and to identify the signals that
must be stored.
Thirdly, optimize the compromise between the storage space ofsignal values and the complexity of schedule time needed for
the decompression process. As, we describe above, we must
find the signal number k that allows a suitable complexity of allconsidered dependency functions inside a given VHDL model.
Although the research of this number is so complex and in the
most time we cannot find just a number but an interval. In this
case we must resolve the solution of finding this signal number
k based on other information, which is the reduction of neededstorage space of signal values. Throughout these information,
we must find a signal number k inside the considered intervaland which gives a less need of storage space of signal values.
Finally, store all needed signal and required dependency func-tions.
Problem formulation: The problem we are going to consider may
be formulated as follows:
For a given signal Sk, which is written in the form:
Sk = Fk(S0,...,Si)i = 0 n (30)
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minimize the dependency function complexity: Cki, which shouldbe written in the following form:
Ck =i Cki =
i,j iwiCij
(31)
where k, i = 0...n, n is the number maximal of signals, f(., .) afunction to define, and:
j is defined as follows:
j =
0 : Sj value not stored in DDB1 : otherwise
(32)
wi is the weight of operation i contained inside the dependencyfunction
fi(). It is defined as follows:
wi =
0 : Si independent1 : fi() = NOT2 : fi() = XOR
: so on(33)
Let consider the signal sets S = {S0, , Sn} as information model,which will be identified. It looks like that our VHDL model is a source
of signals, which will be produced each simulation time ti with distin-guished probabilities pi. These signals are dependent one of each
other and they are correlated between them. Where each signal Sirepresents an information to be stored or not. Thereby, our problem
will be considered as a Lossless Data Compression Problem that
searches to encode each signal Si with a number of bits and thenoptimizes the number of the signal values, which must be stored for
further use and that allows a suitable restoration of the all signals
during the decompression process.
On the other hand, for a given signal sets S = {S0, , Sn}, we con-sider the probability of a signal Si, i = 0 n, pi to be appear in theVCD file during a simulation process and the probability pi/j i j&i, j = 0
n as the probability of the dependency between signals
Si and Sj. The probability pi of signal Si. is defined as follows:
pi =i SSin
j=0j SSj
(34)
where i is the occurrence frequency of the signal Si and SSi isthe storage space needed for storing the signal Si. It means, when
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a signal Si appears just once a time during simulation process, iwill have the value one and so on. Although, the probability pi/jof dependency between the signals Si and Sj (or the conditionalprobability) is defined as follows:
pi/j = j SSj
i SSi =jSSj
pi nl=0
l
(35)
where j is the number of times in which the Sj belongs to signal Si.I.e. the number of times that the signal Sj is defined as a parameterof function fi().
The problem we are dealing with can be defined as an optimization
problem. So, mathematically, this problem will be written as follows:
OP :
minm ( 1mi,j
Cki)
minm
( 1mi
pi)(36)
From this optimization problem, we can say that the needed storage
space and the dependency function complexity are inversely (con-
versely) proportional. So, we can define a new space composed of
the complexity and the probability as shown in figure ??. This allows
us to consider the function to minimize as follows:
min
k
(1
k dim2) (37)
where dim is the distance between the points Xmin(pm, Ckm) andXi(pi, Cki):
dim = d(Xi, Xm) =
(pi pm
A)2 + (
Cki CkmB
)2 (38)
where A and B are constants for scaling, and the distance dm isdefined as follows:
dm = mini
(di) di =
(piA
)2 + (CkiB
)2 (39)
The Xmin(pm, Ckm) is chosen with the manner that Sm = fm(Sj)j {0 n} is composed of independent signals only. This means thatall Sj are independent.
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So, the problem we are dealing with can be written as follows:
minl
(1
l
(pi pm)2 + (Cki Ckm)2) (40)
This problem can be transformed to a quadratic optimization problemin the following form:
k {i h} Xk =
pi...
pkCik
...
Ckk
mink
(1
k(XTk MkXk + VkXk + Kk))(41)
where :
Mk =
1A2 0 00 1A2 0 0... . . . ...0 0 1A2
0 0
0 0
1B2 0 00 1B2 0 0... . . . ...0 0 1B2
the matrix of quadratic optimization. This matrix is (2k, 2k) di-mension. I.e Mk
R2k2k. We can demonstrate that the
matrix Mk is symmetric and positive definite, which meansMTk = Mk and x R2k1 : xTMkx > 0.
Vk = 2
pmA...
pmA
CmkB...
CkkB
, the vector of quadratic optimization.
The length of this vector is 2k.
Kk =
p2
iA2...p2k
A2C2km
B2...
C2kk
B2
is a constant vector. The length of this vector
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Figure 12: Considered Space
Figure 13: Variation of the chance of getting optimal solution
is 2k.
The solution of considered problem consists to find a set of signals
Xm = {Si}i{jm} where j < m < n, which satisfy the conditionbelow. Our object is to define the convenient signal sets with which
we have an optimal storage space that associates an optimal com-
plexity.
So, our new problem will be formulate as follows:
m
0
kfind Xm = Sii{jm}
j < m < n (42)
that succeeds:
m Xm = {Si}i{0m}
mink=0n
i=0n
( 1m
Cki) = (1m
Cki)opt
minm
( 1m
p(Si)) = (1m
pi)opt
(43)
To resolve this problem, we try to consider the optimal signal set
as Xopt, which has a length (number of signals inside) nopt such asnopt < n where n is the total signal number inside the consideredVCD file.
To search Xnopt, we need to consider a discrete probability problem,which is defined as follows:
for each m {0 k} we have a chance probability to geta solution of our OP problem. This solution can be writtenas follows: ( 1m
Cik,
1m
pi). Let associate to this solution a
chance probability qm that satisfies 0 < qm < 1.
we know that for our nopt we have the best chance to get theoptimal solution ( 1nopt
Cik,
1nopt
pi)of our OP solution. So,
m {0 k} we have the following condition to be verified :1 > qnopt qm > 0. The Figure ?? shows the variation of thechance to get an optimal solution function of the consideredsignal sets.
We can assume that the variation of the chance of getting an optimal
solution is a distribution. So, we can define this distribution, which
will identify the relationship between the chance probability to get an
optimal solution an the signal sets. This distribution can be written
as follows:
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q(Xi) = exp((Xi Xnopt)T(Xi Xnopt)
) + (44)
where , and are constants.We note that the peak of the chance is found at the point Xnopt .Although, we cannot demonstrate that the considered distribution or
density is not symmetric around Xnopt.
If we assume that this density is symmetric around Xnopt, we candemonstrate that it will be written as follows:
q(Xi) = fXnopt ,Mk(Xi) =1
(2)kdet(Mk)exp( (Xi Xnopt)
TM1k (Xi Xnopt)2
) (45)
Proof: to prove the equation above, just consider the case of the
p-variate normal distribution for multivariate with p = 2k [5].
So, we can use this equation as a constraint for the optimization
problem defined in equation (41). Always, we can fix the chance to
obtain an optimal solution of considered optimization problem, and
than search the corresponding signal sets which succeeds consid-
ered chance probability.
For example is we would like that the chance of getting an opti-
mal solution must be greater than 0.7, we can consider the followingquadratic optimization problem:
mink
( 1k (XTk MkXk + VkXk + Kk))
1
(2)kdet(Mk)
exp( (XkXnopt)TM1
k(XkXnopt)
2 ) 0.7(46)
where k represents the length of the vector Xk =
Si...
Sk
that must
be identified.
4.2.2 One signal restoration
In this section we try to treat the case of restoration of one signal from
a signal lists that have been compressed. We know that considered
signal is combination of a signal sets. So, to restore this signal we
need to calculate the function link this signal to all other signals. In-
deed the complexity of the restoration depends on the calculation of
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these signals. This can be so complex so possible. To reduce this
complexity, we need to reduce the complexities of the calculation of
all signal that are dependent of each other. This means that the
restoration depends on the operation number needed to calculate all
required signals.
Sn = Fn(S0, , Sn1) (47)
where
Si = Fi(S0, , Sk) i, k = 0 n 1 (48)
So, to calculate Fn() we need first to calculate Fi(). So, the com-plexity of the function Fn(), will be calculated based on the functioncomplexities Fi():
Cn =
ni=0
wiCi (49)
where wi represents the weight of the operation belong to signal Si
This problem can be transformed to an optimization problem, which
is
minn
(ni=0
wiCi) (50)
4.2.3 Data base optimization
In this section we try to give an overview about the case where the
same signal depends on itself for each clock cycle and/or on signal,
which depends on clock cycle. Although the simplicity of the sim-
ulation of the relationship between considered signal and the other
associated signal, we have to solve the problem of storage space
optimization.
Let look at the example of figure ??. We see that the signal a de-
pends on the clock signal. It changes value for each clock signal
cycle.
In the example of figure ??, we see that the signal a will change
value each cock signal cycle. So, if we like to store the signal a,
we will need more storage space. Mathematically, we can write the
following relation between the clock signal clk and the signal a
a(n) = a(n1) XOR 1 (51)
where n is the nth clock signal cycle.
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P: process
begin
if clkrising_edge then
a
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Figure 15: Software Design
needed for the restoration of signal value S(n). Arbitrary, we can
choose p as follows:
p IN : p 1 n10
p i = 1 9 (56)
Schedule time analyses: In this paragraph, we prove our choice
of the value of p. Let consider the case, when all values of the signala will be stored. So, we need (n 1) size(a) storage space tostore all values of signal a. However, if we store just the value of a
at the clock signal cycle 0, we will need (n 1) C0 schedule timeto restore the value of signal a at the clock signal cycle n. Indeed,if we apply the developed algorithm, we need just p C0 n10 C0schedule time to restore the a signal value at the clock signal cycle
n and just 9 size(a) storage space. So, we have to reduce thenumber of schedule time of 10 and the number of storage space of10 too.
4.3 Waveform Compression Software Design
In this section an overview of the developed software design is pre-
sented. Figure ?? represents the general aspect of this software.
FreeHDL Simulator: its task is to simulate a given VHDL designin order to create the VCD and DDB files for further use. CDFG Simulator: the CDFG simulator allows to create the
Control Data Flow Graph of considered VHDL model and write
it in a specific file.
Waveform Compressor: its task is the compression of the VCDfile based on the CDFG of considered model. The obtained file
will be stored for further use.
Waveform Decompressor: realizes the decompression of com-pressed VCD file to view it.
Waveform viewer: allows the viewing of the decompressedVCD file in order to get out the verification results of consid-
ered VDHL design.
Figure ?? represents the software module designs in detail.
Waveform Compressor: the waveform Compressor is com-posed of two basic modules:
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Waveform Compression module: this module interests the
compression techniques. Three compression modules
are employed:
Header file compression module: as it is describedabove, the compression of the VCD header file isdone independently of the Control Data Flow Graph.
Simulation Time Compression module: this moduleinterests the compression of the signal ids through-
out the knowledge of considered clock cycle and sig-
nal events. It returns the signal ids, which must be
compressed and stored.
Parameter value compression module: this modulerealizes the compression of considered parameter val-
ues inside the given VCD file based on the informa-
tion returned from Dependency Scheduler and VCDfile. It returns the signal values, which must be com-
pressed and stored.
Dependency Scheduler module: this module treats the
dependency of signals and processes based on the de-
veloped CDFG of the VHDL design. This module has to
control whether a given signal Id and value will be com-
pressed and stored or not. So, it controls the Parameter
Value Compression and the Simulation Time Compres-
sion modules. Thereby, it gives the needed information to
the Simulation Time module about which signal Ids that
must be compressed and these to the Parameter ValueCompression about which signal and variable values must
be compressed and stored. On the other hand, it returns
the dependency between signals and variables in math-
ematic forms to the Waveform Compression module to
be stored. Its input comes from the CDFG Scanner and
Parser.
CDFG Scanner and Parser module: this module translates theCDFG, which is written in a given file to a data base inside the
memory for further need. Its inputs are coming from the DDB
and CDFG files.
Viewer: the viewer has to get out the verification results of con-sidered VHDL model. Basically it consists of two modules :
Waveform Decompressor: it is composed of four mod-
ules, which are needed for the decompression of com-
pressed VCD file.
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Figure 16: Software Module Designs
Header File Decompression module: this module is
used to decompress the VCD header file.
Simulation Time Decompression module: this mod-ule allows the decompression of the Simulation Time
based on the information returned from the compressed
VCD file and the Dependency Simulator.
Parameter Value Decompression module: this mod-ule decompresses all parameter values based on the
information stored in the compressed VCD file and
those returned from the Dependency simulator.
Dependency Simulator module: this module allows to
simulate the stored dependencies between parame-ters and returns either the parameter value or the the
Simulation Time.
waveform viewer: simulates decompressed VCD file to
get out the Verification results of VHDL model.
5 Time Schedule
In this section we presents the needed time to achieve each module
of this software.
VCD header file compression: already done. Simulation time compression: one month. Parameter value compression: one month. Dependency scheduler: two months. CDFG scanner and parser: already done. VCD header file decompression: one month.
Simulation time decompression: two months.
Dependency simulator: three months. Parameter value decompression: two months. Waveform viewer: using Dinotrace. Already done.
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6 Conclusion
In this document, we presented an idea of using CDFG to improve
the developed waveform compression technique. Two cases for us-
ing CDFG in the waveform compression are developed: simple case,
which interests the signal and process dependencies, and complex
case that interests the other VHDL statements. We can conclude
that the CDFG advantages are to allow a rapid interpretation of the
information inside a VHDL model throughout a graphical represen-
tation.
7 Reference
[1] E. Naroska, A Novel Approach for Digital Waveform Compres-
sion.
[2] E. Naroska, Waveform Compression Technique.
[3] E. Naroska and S. Mchaalia, Control Data Flow Graph for Free-
HDL compiler.
[4] J. Ziv and A. Lempel,A Universal Algorithm for Sequential Data
Compression, IEEE Transaction on Information Theory, Vol. IT-23,
No.03, May 1997.
[5] The multivariate Normal Distribution, basic course.
List of Figures Figure ?? : VCD File. Figure ?? : VHDL Model 1. Figure ?? : CDFG of VHDL Model 1. Figure ?? : VHDL Model 2. Figure ??: VHDL Signal Assignment procedure. Figure ?? : CDFG of VHDL Model 2. Figure ?? : VHDL Model 3. Figure ?? : CDFG of VHDL Model3. Figure ?? : VHDL Model 4. Figure ?? : CDFG of VHDL Model 4. Figure ?? : Software Design. Figure ?? : Software Module Designs.
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