CD00271682_PM3533_datasheet_rev3

Preliminary Data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

December 2010 CD00271682 Rev 3 1/77

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PM3533

All-in-one energy management for smart phone RF solutions

DescriptionPM3533 is an all-in-one solution for RF energy management and RF front-end control for GSM/EDGE/WCDMA/TD-SCDMA/LTE RF solutions. It is designed specifically to support Multi-Mode and Multi-Band Power Amplifier (MMMB PA); with >90% efficiency and 2.6 V cut-off voltage support, PM3533 enable improved efficiency for PA and RF IC to maximizes the battery life time of smart phones.

The PM3533 includes DCDC converters for transceiver and PA, PA bias DAC, linear regulated low noise supply for RF FE, GPIOs for antenna control of tunable antennas and SPI RF FE control.

Applications• Multi-Mode and Multi-Band PA solutions

• Mobile phones

• Portable communication equipment

• Navigation systems and connected devices

Features• All-in-one RF PMU

• Supports 2.6 V to 5.5 V battery voltage range

• High efficiency 400 mA DCDC converter for RF transceiver– five level programmable output voltage

• High efficiency 600 mA/1.5 A Buck DCDC converter for PA with analog control voltage

• Boost DCDC converter for PA– BOOST by-pass mode– Enables support for low VBAT cut-off: 2.6 V

• Line regulated low noise 2.5 V supply for RF FE components

• PA bias DAC

• Three GPIO signals for RF FE control

• Battery voltage monitoring circuitry

• Under-voltage-lockout circuitry

• Thermal shutdown circuitry

• Green product: lead-free/RoHs compliant.

• VFBGA 3.4 mm x 3.4 mm x 1.0 mm with 0.4 mm pitch

www.stericsson.com

http://www.stericsson.com

PM3533

2/77 CD00271682 Rev 3

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Device summary

Table 1. Device summary

Features Range

Temperature rangeAll specifications fulfilled

-20°C to +85°C

Temperature rangeFunctional

-30°C to +85°C

Battery voltage range 2.6 V to 5.5 V

Package VFBGA 3.4 mm x 3.4 mm x 1.0 mm, 64 F8x8

DCDC1 - GSM PA operation

Output voltage range 50 mV to 5.5 V

Control voltage range 0 to 1.5 V

Maximum output current 1.5 A

Efficiency 90% (combined efficiency of Boost-Buck)

Efficiency 95% (Buck)

Large signal loop BW 230 kHz

DCDC1 – WCDMA PA operation

Output voltage range 50 mV to Vin-150 mV

Control voltage range 0 to 1.5 V

Maximum output current 600 mA


Large signal loop BW 230 kHz

DCDC2 for TRX

Output voltage (Vout) 1.35 V, 1.45 V or 1.65 V



PSRR ≤ 100 kHz 63 dB

Start-up time 10 μs

IDAC

Resolution 6 bits

Output current range 0 to 2.3 mA (Vout < 2.3 V)

2.5 V linear regulator

Output voltage 2.5 V


PSRR ≤ 100kHz 40 dB

PM3533

3/77 CD00271682 Rev 3

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Figure 1. DCDC1 GSM operation - Combined Boost-Buck

Figure 2. DCDC1 GSM PA operation - Buck

Figure 3. DCDC1 WCDMA PA operation - Buck

DCDC 1 GSM PA operation (Buck/Boost) - VBAT= 3.6V

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DCDC 1 GSM PA operation (Buck) - VBAT= 3.6V

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DCDC 1 GSM PA operation (Buck) - VBAT= 3.6V

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DCDC 1 WCDMA PA operation (Buck) - VBAT= 3.6V

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PM3533

4/77 CD00271682 Rev 3

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Figure 4. DCDC2 in TRX operation

DCDC 2 TRX operation - VBAT= 3.6V, Vout= 1.45V

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PM3533 Contents

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CD00271682 Rev 3 5/77

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1.1 Special power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 General specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Reference design schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 SMPS for PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 Closed-loop mode SMPS full power critical electrical parameters . . . . . . 19

5.2 Closed-loop mode SMPS section mode, critical electrical parameters . . 20

5.3 Operating parameters for SMPS converter . . . . . . . . . . . . . . . . . . . . . . . 21

5.4 Critical external components for SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4.1 SMPS performance with critical components . . . . . . . . . . . . . . . . . . . . 26

6 Boost DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 Boost full power electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.2 Operating requirements for Boost DC-DC converter . . . . . . . . . . . . . . . . 28

6.3 Critical external components for Boost DC-DC converter . . . . . . . . . . . . 31

7 BUCK DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 DC-DC closed-loop mode, critical electrical parameters . . . . . . . . . . . . . 33

7.2 Operating requirements for BUCK DC-DC converter . . . . . . . . . . . . . . . . 34

7.3 Critical external components for BUCK DC-DC converter . . . . . . . . . . . . 38

7.3.1 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.3.2 Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1 VHI regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Contents PM3533

6/77 CD00271682 Rev 3

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8.1.1 Power up for VHI regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10 RF controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12 OTP memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13 Battery monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

14 Under-voltage-lockout block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

15 Mux structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

15.1 MUX 1 controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

15.1.1 PM3533 self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

16.1 Power UP/DOWN sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

17 Control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

17.1 Data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

18 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

18.1 PM3533 ball-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

18.2 PM3533 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

19 PM3533 register description for closed-loop mode . . . . . . . . . . . . . . . 61

20 Example of WCDMA output power distribution curve . . . . . . . . . . . . . 72

21 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

21.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

21.2 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

22 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PM3533 Contents

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CD00271682 Rev 3 7/77

23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

List of tables PM3533

8/77 CD00271682 Rev 3

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 3. Operation conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 4. Electrical characteristics of SMPS full power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 5. Electrical characteristics of SMPS section mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 6. SMPS operation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 7. SMPS inductor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 8. SMPS capacitor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 9. SMPS performance with critical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 10. Boost full power mode general electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 11. Boost converter operation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 12. Inductor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Table 13. Capacitor specification for Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Table 14. DC-DC closed-loop mode electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Table 15. Buck DC-DC converter operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Table 16. Inductor specification for closed-loop mode DC-DC converter usage . . . . . . . . . . . . . . . . 38Table 17. Capacitor specification for closed-loop mode DC-DC converter usage . . . . . . . . . . . . . . . 38Table 18. Current output capability / nominal voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 19. Regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 20. Power-up timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Table 21. D/A-converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values . . . . . . . . . . . . . . . . . . . . . . . 43Table 23. I/O pad accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 24. RF control voltage output parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 25. Thermal shutdown parameter table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 26. Battery monitoring characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 27. Under Voltage Lockout characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 28. MUX1 register writings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 29. PM3533 Kelvin nodes for self test purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Table 30. Power up timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 31. Power down timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 32. Data interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Table 33. SPI control signal timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 34. PM3533 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 35. Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 36. Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 37. Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 38. Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 39. Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 40. Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 41. Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 42. Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 43. Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Table 44. Register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table 45. Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table 46. Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 47. Register 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 48. Register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

PM3533 List of tables

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CD00271682 Rev 3 9/77

Table 49. VFBGA 3.4 mm x 3.4 mm x 1.0 mm with 0.4 mm pitch and 0.25 mm ball . . . . . . . . . . . . . 73Table 50. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Table 51. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Table 52. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

List of figures PM3533

10/77 CD00271682 Rev 3

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List of figures

Figure 1. DCDC1 GSM operation - Combined Boost-Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 2. DCDC1 GSM PA operation - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 3. DCDC1 WCDMA PA operation - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 4. DCDC2 in TRX operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 5. PM3533 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 6. PM3533 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 7. Reference design schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 8. USB application reference design schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 9. Step-down switching regulator based on Buck converter with voltage-mode control . . . . . 19Figure 10. Transient response requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 11. Boost converter simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 12. Transient response requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 13. Buck DC-DC-converter simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 14. Transient response requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 15. Power up sequence timing diagram for VHI regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 16. DA-converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 17. Output current accuracy of PADAC coded characteristic equation . . . . . . . . . . . . . . . . . . 44Figure 18. RF control connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 19. Thermal shutdown functional of modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 20. Simplified OTP bits connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Figure 21. Under-voltage-lockout block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Figure 22. PM3533 multiplexer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 23. Power up sequence timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 24. Power down sequence timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 25. Timing waveform of writes cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 26. Timing waveform of read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 27. Serial data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 28. PM3533 ball-out diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 29. DG09 WCDMA output power distribution curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Figure 30. VFBGA 3.4 mm x 3.4 mm x 1.0 mm, 0.4 mm pitch, 0.25 mm ball . . . . . . . . . . . . . . . . . . . 74Figure 31. Marking composition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

PM3533 Overview

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CD00271682 Rev 3 11/77

1 Overview

PM3533 is RF energy management and RF FE control device that contains following functionalities: SMPS (Switched Mode Power Supply), Boost DC-DC converter, Buck DC-DC converter, several regulators for internal use and one regulator for external use. PM3533 also contains two antenna control IOs and two PA bias DAC outputs with the possibility to use the second DAC output also as third GPIO.

Figure 5. PM3533 functional block diagram

1.1 Main features• Antenna controls and PA control signals

– Two antenna-tuning controls. Controls are programmable via the Serial Peripheral Interface (SPI).

– One adjustable current reference for PA, with two multiplexed outputs.

– One of the outputs can also be used a static control output

• SMPS converter

– SMPS converter optimized for both GSM and WCDMA power amplifiers

– GSM mode bursts ramp-up/ramp-down capability

– Two different operating modes, which are controlled via Serial Peripheral Interface (SPI). The operating modes are used to optimize SMPS efficiency at lower power levels. Operation modes are explained in Section 1.1.1.

– Internal adjustable switching clock

– Dithering. Dithering adds deviation to switching frequency, which lowers switching harmonic at output of SMPS. The deviation of the dithering is adjustable between two different frequencies.

– Adjustable delay control for SMPS power switch drivers.

– Adjustable integrated loop-filter.

• Boost DC-DC converter

– Boost DC-DC converter regulates the battery voltage up to 4.0 V, 4.3 V, 5.3 V or 6 V.

Overview PM3533

12/77 CD00271682 Rev 3

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– Three different operating modes are controlled by the Serial Peripheral Interface (SPI). The operating modes are used to optimize the power converter efficiency at lower power levels. The operation modes are explained in Section 1.1.1.

– Sampled soft-start, to enable smooth transient behavior on Boost DC-DC converter output when starting the device or to continue from earlier idle (with its output already at the correct level)

– Internal adjustable switching clock.

– Dithering. Dithering adds deviation to switching frequency, which lowers switching harmonic at the output of the boost DC-DC converter. The deviation of the dithering is adjustable between two different frequencies

• Buck DC-DC converter

– The buck DC-DC converter down-regulates the battery voltage to 1.45 V.The output voltage is adjustable also to 1.65 V or 1.35 V, another normal usage set is 1.85 V or 1.55 V.

– Sampled soft-start, to enable smooth transient behavior on Buck DC-DC converter output when starting the device or to continue from earlier idle (with its output already at the correct level).

– Internal adjustable switching clock.

– Dithering. Dithering adds deviation to switching frequency, which lowers switching harmonic at the output of the buck DC-DC converter. The deviation of the dithering is adjustable between two different frequencies.

• External regulators

– PM3533 has one regulator for external use. VHI regulates the battery voltage to 2.6 V or 2.5 V. VHI is enabled automatically after power-up with default output voltage of 2.5V.

• Multiplexer

– PM3533 has one programmable multiplexer used to switch several analog node voltages to PM3533 MUX1 I/O. The battery-monitoring block is also connected to the multiplexer. Additionally MUX1 I/O can be used for self-testing purposes.Multiplexer structure is shown in Figure 22.

• Serial Peripheral Interface (SPI) for PM3533 control.

• Battery monitoring block. This block enables battery voltage monitoring during the operation and can also be used for self-testing purposes in production line.

• Under Voltage Lockout block. This block adds special protection by automatically powering-down the boost power converter if abnormal power-downs occur at full power mode.

• 40-bit OTP memory. One time programmable memory is needed to switch the frequency tuning for all three converters. Also TSD (Thermal shutdown cell) can be tuned with OTP memory.

• Thermal shutdown

– Thermal shutdown circuitry monitors the die temperature and fulfills a shutdown when a specified temperature is reached. Thermal protection is enabled automatically after power-up.

PM3533 Overview

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CD00271682 Rev 3 13/77

1.1.1 Special power saving modes

DCDC converters have “low power” operation modes, which reduce the current consumption in low power mode. The modes are controlled through the serial control interface.

SMPS converter

1. “Low power” mode means that the size of power switches including the drivers are reduced at lower power levels.

2. Power switches are divided into two parts. In high power levels both parts are used while in low power levels only 1/3 part of the switches and their drivers are used. The decision on which mode is used comes from the base-band.

Boost DC_DC converter

Boost DC_DC converter includes two different power saving modes.

1. “Full power” mode means that the boost DCDC converter at normal operational mode with the full output power capability. Enabling of this is coming from the base-band.

2. The boost converter has also a “By-Pass” mode, which corresponds to 100% duty cycle operation. In that mode the converter upper switch is turned on while the converter lower switch is turned off. The boost by-pass function can be used in low power levels by shutting down the boost-converter.

General specifications PM3533

14/77 CD00271682 Rev 3

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2 General specifications

2.1 Absolute maximum ratingsNote: Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Always use the operating conditions mentioned below when using the PM3533 in the application usage or similar kind of, to achieve the correct functionality and performance (look at Section 2.2: Operating conditions for further details).

2.2 Operating conditions

Table 2. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

IND_BOOST, INPUT_SMPS,

VBATT, VBB_VRX

Supply voltage level -0.3 9 V

SMPS_CTRL, DATA, ENABLE, SCLK, XRESET,

VREF, VXO

Supply voltage level / control voltage level -0.3 2.7 V

Tj Junction temperature 150 °C

TS Storage temperature -50 125 °C

ESDHBMElectrostatic discharge integrity for pins connected to battery, HBM(1) -1000 +1000 V

ESDCDM Electrostatic discharge protection, Charge device Model(2) -500 +500 V

1. Test conditions according to JESD22-A114.

2. Test conditions according to JESD22-C101.

Table 3. Operation conditions


General electrical characteristics

TOP Operating ambient temperature, all specifications fulfilled -20 +85 °C

TOPF Operating ambient temperature, functional -30 +85 °C

TJA Thermal resistance 50 °C/W

VBAT Battery voltage in normal operation mode 2.6(1) 5.5 V

VBATMAX Maximum battery voltage (due to charging) 4.8 5.5 V

VBAT1 Battery voltage in normal operation mode with Vbuck_boost 2.3 5.5 V

VBOOSTMAX Maximum up-converted voltage 6.5 V

PM3533 General specifications

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CD00271682 Rev 3 15/77

VUSB USB supply voltage

4.75(2) (3)

5 5.25 V

IAD Admissible current per ball 800 mA

PMAX Power dissipation(4) 800 mW

VBAT_Iload Battery current for PM3533 3 A

VXO Digital power supply 2.1 2.5 V

VXO_Iload Digital power supply current load (UVL enabled) 120 µA

VIO Driver stage supply voltage 1.7 1.8 1.9 V

VIO_Iload Driver stage supply current Iload 3.5 18 mA

Vbuck_boost Analog power supply DC

TRAN 3.339-0.1

3.4 3.461+0.1

V

Vbuck_boost_Iload Analog power supply current load 25 mA

VREF Reference voltage 1.176 1.2 1.224 V

VLOW Digital input/output low 0 0.67 V

VINPUT,HIGH Digital input high 1.1 1.88 V

VOUTPUT,HIGH Digital output high 1.5 1.88 V

Ileak_vbat Leakage current from Vbat supply 120 µA

1. Analog power supply can be supplied from the Baseband Vbuck_boost or directly from the battery. When the Analog supply is fed from battery, PM3533 cut-off voltage is 2.6 V (typical) otherwise cut-off is 2.3 V

2. Analog power supply range in the USB mode is according to the USB standard specification.

3. USB supply voltage as low as 4.0 V is allowed and even under transient conditions minimum of 3.67 V is possible for a short period of time in the USB 3.0 specification.

4. Maximum that is allowed while taking into account internal losses at applicable load condition

Table 3. Operation conditions (continued)


Block diagram PM3533

16/77 CD00271682 Rev 3

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3 Block diagram

PM3533 block diagram in the closed-loop mode environment is shown below.

Figure 6. PM3533 block diagram

PM3533 Reference design schematic

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CD00271682 Rev 3 17/77

4 Reference design schematic

Figure 7. Reference design schematic

Reference design schematic PM3533

18/77 CD00271682 Rev 3

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Figure 8. USB application reference design schematic

PM3533 SMPS for PA

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CD00271682 Rev 3 19/77

5 SMPS for PA

Figure 9 shows the simplified schematic of PM3533 step-down switching regulator with basic functionality. The converter itself is a Buck converter with synchronous rectification. The control is realized using the so-called voltage-mode control.

Figure 9. Step-down switching regulator based on Buck converter with voltage-mode control

5.1 Closed-loop mode SMPS full power critical electrical parametersThe most critical parameters are collected in Table 4.

Table 4. Electrical characteristics of SMPS full power mode


Vin Input voltage range 2.3 6 V

Iout Max.output current range, bursted 2.5 A

IqActive current consumption with no load current, 9.5 MHz clock, Vctrl 0V

2.8 mA

Efficiency with Iload1.2 AVinput=3.6V , Vout=3.2V Freq 9.5MHz (coil loss included)

92 94 %

Max continuous load current in +85 °C ambient temperature

2 A

SMPS for PA PM3533

20/77 CD00271682 Rev 3

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5.2 Closed-loop mode SMPS section mode, critical electrical parameters

Programmable switching frequency (5-bit)

2.1 12 MHz

Power-up time 10 µs

Table 4. Electrical characteristics of SMPS full power mode (continued)


Table 5. Electrical characteristics of SMPS section mode


IoutOutput current range. Continuous current over temp range and over life-time

600 mA

IqActive current consumption with no load current, switching freq 9.5 MHz. SMPS_cntrl at 0 V

2.8 mA

Efficiency with VBAT=3.6 V, Iout = 80 mA, Vout = 0.95 V, f = 2.2 MHz

82 %

Efficiency with VBAT=3.6V, Iout = 285 mA,Vout=3.4 V, f = 2.2 MHz

95 %

Max load current, continuous at application level

500 (TBD) mA

PM3533 SMPS for PA

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CD00271682 Rev 3 21/77

5.3 Operating parameters for SMPS converterCharacteristics to be met over the operating temperature range specified in Table 3: Operation conditions unless otherwise stated.

Table 6. SMPS operation parameters

Symbol Parameter Min Typ Max Unit Notes

Voltage levels and regulation

Vi_oper1Operating input voltage (full power mode)

5.82 6 6.18 VAccuracy: +/- 3% BOOST OUTPUT

Vi_oper2Operating input voltage (full power mode)

5.15 5.3 5.45 VAccuracy: +/- 3%BOOST OUTPUT

Vi_oper3Operating input voltage(full power mode)

3.88 4 4.12 VAccuracy: +/- 3%BOOST OUTPUT

Vi_oper4Operating input voltage(full power mode)

4.18 4.3 4.42 VAccuracy: +/- 3%BOOST OUTPUT

Vi_oper_lowOperating input voltage(low power mode)

Vbat min - 350 mV

Vbat min V

Lowest power levels Boost-converter is in by-pass mode when SMPS input voltage is VBAT. NOTE: Depends on the application usage

Vout

-[-30;+85]°C

smps_ctrl at0.0230.03

0.10.4

0.751.001.251.55

1.591.62

0.0660.088

0.3261.269

0.0730.095

0.3181.2722.3853.1953.9824.964

5.0975.198

0.0800.103

0.3111.277

3.2434.0015.097

5.4465.461

V

(default gain setting)Accuracy: +10.0/- 9.5%Accuracy: +8.0/- 7.9%

Accuracy: +2.6/- 2.3%Accuracy: +0.4/-0.2%(used as a ratio reference)

Accuracy: +0.2/+0.05%Accuracy: +0.65/+0.2%Accuracy: +3.4/+0.7%

Accuracy: +7.7/+0.8%Accuracy: +6.0/+0.9%

Gain, Voutg1 3.18

Look at smps_ctrl = 0.75V / Vout = 2.385V above

g2 3.38 Optional (via bit control)

Dropout voltage at room temp

Switching freq 9.5 MHz. Note: Minimum delay setting used @ Vi_oper2.

370 420 mV

Iload=1.25A @Vi_oper2Included LC DCR/ACR values (see Section 5.4 values)

Dropout voltage-[-30;+85]°C

Switching frequency typ of 5.0 MHz @ Vi_oper2. (1) 270 350 mV

Iload=1.25A @Vi_oper2Included LC DCR/ACR values (see Section 5.4 values)

SMPS for PA PM3533

22/77 CD00271682 Rev 3

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Iload Load current 1.2 1.7 A

@Vout max= 4.7 VNote: Max currents are defined during the GSM burst. MAX value includes PA current consumption in worst case VSWR case.

Iload_mode

Load current in GSM mode when Boost-converter is by-passed or PA max power is achieved lower than nominal SMPS Vout value.

2.5 A

@Vout max= 3.6 VNote: Max currents are defined during the GSM burst.

Inol

-[-30;+85]°C

No load current consumption

Switching freq 9.5MHz3 3.5 mA

Note: PA is in power-down mode.Includes internal clock and drivers and internal regulator quiescent currents.Converter in full power mode

Iidle

-[-30;+85]°CIdle current 0.6 0.8 mA

Note: PA is in power-down mode and PM3533 is in idle mode.Regulators are on.Clock and drivers are off.

f_oscAdjustable Internal clock (typical values)

6.5(4.7/7.9)[2.1/5.3]

13.5(11.7 /14.9)[8.2/10.5]

MHz

Clock range can be tuned with 5+ 1-bit (with the 1stset of reduction / increment bits) [with the 2nd set of reduction / increment bits]

f_osc_tuning_range-[-30;+85]°C

OTP tuning range

7.1[5.7,4.2,3.3]

10.0[9.3,5.8,5.45]

MHz

Tuning range over temp, vbat and corners.[extended range available dedicated control bits:set 1, set2, set3]

f_osc_tuning_acc-[-30;+85]°C

160 230 350 kHz

Can be tuned with OTP memory and with 4+1-bit current bias. Absolute accuracy.

Delta f_osc_shift-[-30;+85]°C

450 ΔkHzTuned OTP freq shift over vbat and temp.

f_osc_d1-[-30;+85]°C

Dither deviation 1 1.9 2 MHzSelectable 2MHz dither deviation

f_osc_d2-[-30;+85]°C

Dither deviation 2 3.7 4 MHzSelectable 4MHz dither deviation

Line_tr (2) Line transient response mVppVin 300mVpp perturbation. Trise/tfall=10 µs. Iload = 1.25 A DC

Table 6. SMPS operation parameters (continued)


PM3533 SMPS for PA

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CD00271682 Rev 3 23/77

Load_tr (2) Load transient response (3) mVpp

Vin=Vbat rangeTransients from 10 mA to 1250 mA.Trise = Tfall = 13 µs.

PSRR[-30;+85]°C

Mode1 Iout = 1200 mA 35 dBsine wave perturbation <10 kHz

Efficiency in GSM-mode

[-30;+85]°CVin = 5 V. Iload 1.25 A @ Vout, typ = 4.6 V Switching freq 9.5 MHz

93 95 %Iload = 1.25A (GSM burst rms current value). Full power mode

[-30;+85]°CVin = 3.6 V. Iload 0.52A @ Vout = 2 V,

Switching freq 9.5 MHz89 92 %

SMPS full power mode,. Boost converter by-passed (active mode)

[-30;+85]°CVin = 3.6 V. Iload 0.17 A @ Vout = 1.1 V, Switching freq 9.5 MHz

79 83 %SMPS Section mode,. Boost converter by-passed (active mode)

[-30;+85]°CVin = 5.0 V. Iload 0.52 A @ Vout = 2 V, Switching freq 9.5 MHz

87.5 90.5 %SMPS full power mode in VUSB case

[-30;+85]°CVin = 5.0 V. Iload 0.17 A @ Vout = 1.1 V,

Switching freq 9.5 MHz74 77 %

SMPS section mode in VUSB case

Efficiency in WCDMA-mode

[-30;+85]°CVin = 3.6 V. Iload 0.5 A @ Vout, typ = 3.37 V

Switching freq 2.1 MHZ93 94.5 %

SMPS Section power mode, Boost by-passed (active mode)

[-30;+85]°CVin = 3.6 V. Iload 0.15 @ Vout = 1.6V,Switching freq 2.1 MHZ

85 88 %SMPS section mode,

Boost by-passed (passive mode)

[-30;+85]°CVin = 3. 6V. Iload 0.045 @ Vout = 0.77 V,Switching freq 2.1 MHZ

62 68 %SMPS section mode,Boost by-passed (passive mode) (4)

[-30;+85]°CVin = 5.0 V. Iload 0.5 A @ Vout, typ = 3.37 V

Switching freq 2.1 MHZ92 93.5 %

SMPS section power mode in VUSB case

[-30;+85]°CVin = 5.0 V. Iload 0.15 @ Vout = 1.6V,Switching freq 2.1 MHZ

81 84 %SMPS section mode in VUSB case

[-30;+85]°CVin = 5.0 V. Iload 0.045 @ Vout = 0.77 V,Switching freq 2.1 MHZ

56 62 %SMPS section mode in VUSB case



SMPS for PA PM3533

24/77 CD00271682 Rev 3

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t_idleIdle start-up From idle to operation

5 μsInitially: regulators on and SMPS is off.

t_onDevice start-upFrom shutdown to operation.

15 μsInitially: PM3533 is shutdown.

1. Minimum delay setting used

2. Transient response requirement clarification is illustrated in Figure 10.

3. These parameters are verified in system measurements in closed-loop mode RF engine platform. It should not inhibit GSMK modulation for burst power-up/down sequences

4. BOOST by-passed active mode means that BOOST serial switch is open by having charge pump activated. BOOST by-passed passive mode means that also charge pump is disabled.



PM3533 SMPS for PA

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CD00271682 Rev 3 25/77

Figure 10. Transient response requirement

5.4 Critical external components for SMPS

Inductor

Vout

T_rec

Load transient

Line transient

Vout +/-tolerance

Vin = Vout = constant. Load step = Iload min to Iloadmax

Line step: 300mV. xV < Vin < xV

Iload = constant = Mode1/Mode2

Tr (mV)

overshoot

Load rise time = fall = Xus

Line fall time = rise = Xus

overshoot

Note: During rise or fall recovery times, there must be no unstable behaviour. The fall recovery time is dependant on Cout and load current

tr<(mV)

Table 7. SMPS inductor specification

Symbol Parameter Min Typ Max Notes

L Inductance (µH) 1

Ira Rated current 1 (A) 1.5Peak current value when inductance is within ± 20 % tolerance, compared to measured typical value at 50% Irated.

Rdc DC resistance (mohm) 60 Rdc is measured with Ira bias current

LtempInductance tolerance over temperature range (%)

-5 +5

Coil inductance compared to nominal value in nominal temperature should not change more than specified over the operating temp. range. Measured with Ira bias current

PL Power Loss (mW) 160Measured with Ira bias current and Sf switching freq.

Magnetic shielding TBD

SMPS for PA PM3533

26/77 CD00271682 Rev 3

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Capacitors

Table 8 lists the specification for SMPS capacitor.

5.4.1 SMPS performance with critical components

Table 8. SMPS capacitor specification

Parameter Specifications

Size (target) 0603

Dielectric X5R/X7R

Temperature range –30°C to +85°C

Rated voltage 10 V DC

Capacitance (typical) 0V Bias 470 nF +/-10 %

Max. Capacitance change 0-5V DC Bias, over temperature range, after aging

From initial value +/-10%

ESR @ 9 MHz (max) 20 mohm

Maximum operating voltage 5.5 V DC

Serial Inductance max. 1.8 nH

Table 9. SMPS performance with critical components

Symbol Parameter Typ Unit Notes

Vo_ripple Ripple voltage 3.1 mVppCout ESR < 20 mohm, L=1 µH, Iload 10 mA to 1200 mA, Switching frequency 9 MHz

PM3533 Boost DC-DC converter

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CD00271682 Rev 3 27/77

6 Boost DC-DC converter

Boost DC-DC-converter’s design topology is the same as SMPS. DC-DC-converter’s output voltage control is done with reference voltage and dedicated control bits.

Figure 11. Boost converter simplified block diagram

6.1 Boost full power electrical parametersNote: The most critical parameters are collected in Table 10 and Table 13. These tables are

shown separately to ease the reading and best define the converter most critical parameters.

Table 10. Boost full power mode general electrical characteristics


Vin Input voltage range 2.3 4.4 V

Vout1 Output voltage range, no load 5.3 V


Vout3 Output voltage range, no load(1) 6.0 V


Iout Boost input current range, bursted 3 A

IqActive current consumption with no load current, full power mode, 7 MHz clock, over temperature and Vbat range (smps_ctrl=0V)

14 26 mA

Boost DC-DC converter PM3533

28/77 CD00271682 Rev 3

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6.2 Operating requirements for Boost DC-DC converterCharacteristics are to be met over the operating temp range specified in Table 3: Operation conditions unless otherwise stated.

Efficiency with Iload=1.2 AVBAT=2.7 V, Vout=5.3 V, Switching frequency 7 MHz, over temperature

80 83 %

Efficiency with Iload=1.2 AVBAT=3.6 V, Vout=5.3 V, Switching frequency 7 MHz, over temperature

89 92 %

Efficiency with Iload=700 mA

VBAT=3.6 V, Vout=5.3 VSwitching freq 7 MHz, over temperature

92 94 %

Max continuous input current in +85°C ambient temperature 2 A

Programmable switching frequency (4-bit) 4.5 11.4 MHz

Output settling time (function of load LC circuitry) 10(2) µs

1. Restricted usage only during production calibration

2. For example L=1 µH C=10 µF

Table 10. Boost full power mode general electrical characteristics (continued)


Table 11. Boost converter operation parameters

Symbol Parameter Min Typ Max Unit Remarks


Vi_operOperating input voltage

2.3 4.4 V

Vout_b1 Output voltage 5.15 5.3 5.45 VAccuracy +/- 3%. Including ripple voltage and line/load regulation

Vout_b2 Output voltage 4 VAccuracy +/- 3%. Including ripple voltage and line/load regulation

Vout_b3 Output voltage 6 VAccuracy +/- 3%. Including ripple voltage and line/load regulation

Vout_b4 Output voltage 4.3 VAccuracy +/- 3%. Including ripple voltage and line/load regulation

IloadLoad current in normal mode

1 1250 1700 mA

Normal mode means that PA is active. Max value includes also PA VSWR current.Note: Max current is defined during the GSM burst.

Ibatt Vbatt Input current 3450 mAIncludes power coil ripple current

Note: Max current is defined during the GSM burst.


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CD00271682 Rev 3 29/77

Iq1Quiescent current (no load) Full power modeSwitching freq 7 MHz

14 26 mA

Note: PA is in power-down mode and PM3533 is thus in idle mode (i.e.SMPS_ctrl=0V).

Includes internal clock & control blocks and boost trap capacitor circuitry & power stages, and also internal regulator quiescent currents


4.5 11.4 MHz Clock range can be tuned with 5-bit

f_osc_tuning_range

[30; +85°C]OTP tuning range 6.8 8.0 MHz

Tuning range over temp, vbat and corners.

f_osc_tuning_acc

[30; +85°C]160 220 330 kHz

Can be tuned with OTP memory and with 4-bit current bias. Absolute accuracy.

Delta f_osc_shift

[-30; +85°C]450 ΔkHz Tuned OTP freq shift over vbat and temp.

f_osc_d1[-30; +85°C]

Dither deviation1 1.9 2 MHz Selectable 2 MHz dither deviation

f_osc_d2[-30; +85°C]

Dither deviation2 3.7 4 MHz Selectable 4 MHz dither deviation

Line_tr(1) [-30; +85°C]

Line transient response(1).

(2) mVpp

Vin 300 mVpk perturbation. Trise/tfall=10 µs. Iload = 1200 mA.In the application SMPS and BOOST blocks are in series.

Load_tr [-30; +85°C]

Load transient response(1) 250 mVpp

Vin= 3.6 V

Transients from 10 mA to 1250 mATrise = Tfall = 13.3 µs.

Line_tr [-30; +85°C]

Line regulation(1). 0.1 0.2 mV Vin 2.7 – 5.3V, Iload 1200 mA

Load_tr[-30; +85°C]

Load regulation(1) 20 mVIload 10 mA – 1200 mA, Vin 5 V, Vin 2.7 V

PSRR[-30; +85°C]

Mode Boost+ SMPS Iout = 1250 mA

35 dB sine wave perturbation <10 kHz

Efficiency - condition Vbat = 3.6 V

η

Vbatt = 3.6 V Iload 1.2 A @ Vout = 5.3 V, switching freq 7 MHz over full Temp. range

89 92 % Boost in full power mode

Table 11. Boost converter operation parameters (continued)



30/77 CD00271682 Rev 3

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η

Vbatt = 3.6 V Iload 0.7 A @ Vout = 5.3 V, switching freq 7 MHz over full Temp range


η

Vin = 2.7V Iload 1.2A @ Vout = 5.3V switching freq 7 MHz over full Temp range


η

Vin = 2.7 V Iload 0.35 A @ Vout = 5.3 V, Switching freq 7 MHz Over full temp range


Timing (refer to start-up and mode change section)

Idle to operationSampled soft-start

10 15 µsInitial condition: Regulators on Boost-converter idle mode. Output capacitor charged but not loaded.

Power-off to operationSampled soft-start

25 45 µsBoost converter initial power-up. Output starts from Vbat - 350mV (typical).

1. Transient response requirement is illustrated in Figure 12.

2. These parameters are verified in system measurements on the close-loop mode RF engine platform. It should not inhibit GSMK modulation for burst power-up/down sequences

Table 11. Boost converter operation parameters (continued)



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CD00271682 Rev 3 31/77


6.3 Critical external components for Boost DC-DC converter

Inductor

Vout

T_rec

Load transient

Line transient

Vout +/-tolerance

Vin = Vout = constant.

Load step = Iload max.

Line step: 300mV. Iload = constant =Ilaod max

tr<XXmV

overshoot

Load rise time = fall = 10us

Line fall time = rise = 10us

overshoot


tr<XXmV

Table 12. Inductor specification


L Inductance 1 µH

Ira Rated current 1 3 A

Peak current value when inductance is within ± 20 % tolerance, compared to measured typical value at 50% Irated.

Rdc DC resistance 50 mΩ Rdc is measured with Ira bias current

LtempInductance tolerance over temperature range

-5 +5 %


PL Power loss TBD WMeasured with Ira bias current and Sf switching freq.


32/77 CD00271682 Rev 3

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Capacitor

Table 13. Capacitor specification for Boost converter

Parameter Specification

Size (target) 0805

Dielectric X5R / X7R

Temperature range –30°C to +85°C

Rated voltage 10 V DC

Capacitance (typical) 0V Bias 11 µF +/-10% or +/-20%,

Min capacitance @ 6 V DC Bias 4 µF

ESR @ 7.5 MHz (max) 20 mΩ

Maximum operating voltage 6 V DC

PM3533 BUCK DC-DC converter

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CD00271682 Rev 3 33/77

7 BUCK DC-DC converter

The BUCK DC-DC-converter design topology used is similar to the SMPS one. DC-DC-converter control is performed via the reference voltage.

Figure 13. Buck DC-DC-converter simplified block diagram

7.1 DC-DC closed-loop mode, critical electrical parametersThe most critical parameters are collected in Table 14.

Table 14. DC-DC closed-loop mode electrical characteristics


VBAT Input voltage range 2.3 4.4 V

Vout1 Output voltage, programmable 1.35 V





Iout Output current range 400 mA

IqActive current consumption (no load current (1);

3.5 4.5 mA

[-30;+85]°C

Efficiency with 100mA loadVBAT 3.6V, switching freq 2.1 MHz, Vout 1.45 V (coil 3u3, case 2520)

87 88 %

BUCK DC-DC converter PM3533

34/77 CD00271682 Rev 3

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7.2 Operating requirements for BUCK DC-DC converterThe following characteristics are to be met over the operating temperature range specified in Table 3: Operation conditions, unless otherwise stated.

[-30;+85]°C


89 90 %

[-30;+85]°C


89 90 %

[-30;+85]°C

Efficiency with 300mA load

VBAT 3.6V, switching freq 2.1 MHz, Vout 1.45 V (coil 3u3, case 2520)

88 89.5 %

Max continuous load current 400 mA

Programmable switching frequency (5-bit)

1.8 4.5 MHz

Startup time (function of load LC circuitry)

10(2) µs

1. In the continuous conduction mode of coil current

2. For example, C=10 µF, L=2.2 µH

Table 14. DC-DC closed-loop mode electrical characteristics (continued)


Table 15. Buck DC-DC converter operating parameters



Vi_operOperating input voltage

2.3 4.4 V

Vout1,2,3,4,5

Output voltage 1)

Output voltage 2)Output voltage 3)Output voltage 4)

Output voltage 5)

1.309

1.4061.6001.504

1.795

1.350

1.4501.6501.550

1.850

1.390

1.4931.6991.596

1.905

V

VVV

V

Accuracy +/- 3%. Including ripple voltage and line/load regulation.Output voltage can be programmed based on battery voltage information from base band.

VrefReference voltage accuracy

1.182 1.200 1.218 VExternal band-gap reference voltage

Iload Load current 10 400 mARF IC is also included in maximum Iload

Ibatt VBAT input current 250 mA

Max. Iload and VBAT at 2.7 V

Note: 1.45 V output voltage used.


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CD00271682 Rev 3 35/77

Iq

Quiescent current (no load)Switching frequency 2 MHz

3.5 4.5 mA

Note: the RF IC is in power-down mode and PM3533 is in idle mode.

Includes internal clock & control blocks and boost trap capacitor circuitry/power stages.Also internal regulator quiescent currents.


1.8 4.5 MHzClock range can be tuned with 5-bit

f_osc_ tuning_range[-30;+85]°C

OTP tuning range 2.5 2.8 MHzTuning range over temp, vbat and corners.

f_osc_tuning_acc-[-30;+85]°C

60 120 kHz

Can be tuned with OTP memory and with 4-bit current bias. Absolute accuracy.

Delta f_osc_shift-[-30;+85]°C

250 kHzTuned OTP freq shift over vbat and temp.

f_osc_d1-[-30;+85]°C

Dither deviation1 0.8 1 MHzSelectable 1 MHz dither deviation

f_osc_d2-[-30;+85]°C

Dither deviation2 1.8 2 MHzSelectable 2 MHz dither deviation

Line_tr

Figure 14Line transient response.

2 4 mVpp

Vin 300 mVpk perturbation. Trise/tfall=10 µs Iload = 400 mA.

Load_tr[-30;+85]°CFigure 14

Load transient response

10 20 mVpp

Vin=2.3/3.6/ 4.4 VTransients from 10 mA to 400 mATrise = Tfall = 10 µs.

Line_tr [-30;+85]°CFigure 14

Line regulation. 0.1 0.2 mVVin 2.3 V – 4.4 V, Iload 400 mA

Load_tr[-30;+85]°C

Figure 14Load regulation 1 2 mV

Iload 10 mA – 400 mA, Vin 4.4 V, Vin 2.3 V

PSRR

[-30;+85]°CMode1 Iout = 400mA

58 dBsine wave perturbation <10 kHz

Table 15. Buck DC-DC converter operating parameters (continued)



36/77 CD00271682 Rev 3

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Efficiency measured with coil 3u3 case2520, condition: Vbat 3.6 V closed-loop mode

[-30;+85]°C

Vin = 3.6 V. Iload 300 mA @ Vout = 1.45 VSwitching freq. 2.1MHz

88 89.5 %DC-DC in normal power mode

[-30;+85]°C

Vin = 3.6 V. Iload 200 mA @ Vout = 1.45VSwitching freq 2.1MHz

89 90 %DC-DC in normal power mode

[-30;+85]°C

Vin = 3.6 V. Iload 150 mA @ Vout = 1.45 VSwitching freq 2.1MHz


[-30;+85]°C

Vin = 3.6 V. Iload 100 mA @ Vout = 1.45 VSwitching freq 2.1 MHz


[-30;+85]°C

Vin = 3.6 V. Iload 60 mA@ Vout = 1.45 VSwitching freq 2.1 MHz


Efficiency measured with coil 3u3 case2520, condition: VUSB 5.0 V closed-loop mode

[-30;+85]°C

Vbatt =5.0 V. Iload 300 mA @ Vout = 1.45 VSwitching freq. 2.1MHz

86.5 88 %Buck DC-DC in VUSB case

[-30;+85]°C

Vin = 5.0 V. Iload 200 mA @ Vout = 1.45VSwitching freq 2.1MHz

87 89 %Buck DC-DC in VUSB case

[-30;+85]°C

Vin = 5.0 V. Iload 150 mA @ Vout = 1.45 VSwitching freq 2.1MHz


[-30;+85]°C

Vin = 5.0 V. Iload 100 mA @ Vout = 1.45 VSwitching freq 2.1 MHz





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CD00271682 Rev 3 37/77


[-30;+85]°C

Vin = 5.0 V. Iload 60 mA@ Vout = 1.45 VSwitching freq 2.1 MHz


Timing (refer to start-up and mode change section)

t_idle_dcdc

[-30;+85]°CIdle to operation Sampled soft-start

6 12 μs

Initial condition: Regulators on DC-DC-converter off, output capacitor charged but not loaded.

T_on_dcdc[-30;+85]°C

Power-off to operation Sampled soft-start

35 55 μsDC-DC-converter power-up, output at 0V.



Vout

T_rec

Load transient

Line transient

Vout +/-tolerance

Vin = Vout = constant.

Load step = Iload max.

Line step: 300mV. Iload = constant = Ilaod max

tr<XXmV

overshoot

Load rise time = fall = 10us

Line fall time = rise = 10us

overshoot


tr<XXmV


38/77 CD00271682 Rev 3

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7.3 Critical external components for BUCK DC-DC converter

7.3.1 Inductor

7.3.2 Capacitor

Table 16. Inductor specification for closed-loop mode DC-DC converter usage


L Inductance 3.3 µH

Ira Rated current 1 0.6A APeak current value when inductance is within ± 20 % tolerance, compared to measured typical value at 50% Irated.

Rdc DC resistance 140 mΩ Rdc is measured with Ira bias current

LtempInductance tolerance over temperature range

-5 +5 %


PL Power loss 1) TBD WMeasured with Ira bias current and Sf switching freq.

Table 17. Capacitor specification for closed-loop mode DC-DC converter usage

Parameter Value

Size (target) 0603

Dielectric X5R / X7R

Temperature Range –30°C to +85°C

Rated voltage 6.3 V DC

Capacitance (typical) 0V Bias 10 µF +/-10% or +/-20%,

Min Capacitance @ 2.8V DC Bias 6 µF

Max capacitance @ 0V DC Bias 12 µF

ESR @ 100 kHz (max) 20 mΩ

Maximum operating voltage 5.5 V DC

PM3533 Regulators

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CD00271682 Rev 3 39/77

8 Regulators

PM3533 includes one linear regulator that can be used to supply low-power functions inside PM3533, RFIC and RF FE components.

8.1 VHI regulator The VHI regulator provides 2.6 V / 2.5 V output voltage. 2.6 V is a default value and 2.5 V can be selected via SPI interface.

Note: 1 For 2.5 V mode: Full_perf (full performance) Vin>2.7 V, Reduced_perf (reduced performance) Vin between 2.6 V and 2.7 V;

For 2.6V mode: Full_perf Vin>2.8V, Reduced_perf Vin between 2.7 V and 2.8 V

Table 18. Current output capability / nominal voltage

Parameter Min Typ Max Unit Notes

VHI output current 30 60 mA

Table 19. Regulator specifications(1)


External compensation capacitance 0.47 1 µF 0.02< ESR < 0.1 ΩIout=<60 mA

Output voltage device to device variation

2.510

2.425

2.605

2.500

2.69

2.575

V

V

Device to device output voltage variation.

Over full temperature range, input voltage range, load range and Vref range (see Note 1)

Output voltage: one sample variation2.5302.445

2.6702.555

V

One sample. Over full temperature range, input voltage range and load range (see Note 1)

Line regulation (1) /(PSRR)30/

(50)dB F < 10 kHz, Vin>Full_perf

Line regulation(2)/(PSRR)30/

(40)dB F < 100 kHz, Vin>Full_perf

Line regulation 0 10 dBF < 100 kHz, Vin=Reduced_perf range

Load regulation 2 6 mVOver full temperature and load range,

Input voltage >Full_perf

Load regulation 35 mV

Over full temperature and load range Input voltage =Reduced_perf range

Regulators PM3533

40/77 CD00271682 Rev 3

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8.1.1 Power up for VHI regulator

VHI regulator’s power-up-timing-sequence is presented in Figure 15. The VXO supply voltage is used as enable signal for the VHI regulator. VHI regulator uses VREF as reference voltage and hence VREF must be activated for VHI to settle to the right output voltage level. The timing diagram below is representative only and therefore real power-up timings are linked to different application use cases and external filtering components (for instance on the external Vref line).

Figure 15. Power up sequence timing diagram for VHI regulator

Rise time (1% to 99%)Voltage reference already On(3) 6 10 µs C = 1uF

Overshoot 3 % C = 1uF, turn on/off

Settling time (0.1% of nominal), 90 mA, depends on load, voltage reference/bias already ON

20 30 µsC = 1uF, turn on from register write latch enable

Total noise density with specified bandwidth, including VREF noise, temp, VBAT/Vbuck-boost

1555060

nVrms/ √ Hz

C = 1 µFIload = 10 mA – 60 mA

@ 1kHz @ 100kHz@ 1MHz

Short-circuit current. Note: the device does not tolerate continuous short-circuit current

300 mA Output shorted to ground

Quiescent current 230 330 µA ON mode

1. Characteristics above are NOT valid if Vin < Full_perf range (see Note 1).

2. Line regulation is 20 dB for f < 100 kHz when battery voltage is lower than Full_perf range.

3. For 90 % rise time max is 10 µs. Rise time is defined in case when VREF and VXO are already settled.

Table 19. Regulator specifications(1) (continued)


PM3533 Regulators

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CD00271682 Rev 3 41/77

Table 20. Power-up timing values

Name Time Unit

t0 0 µs

t1 20 µs

t2 30 µs

t3 70 µs

t4 270 µs

t5 300 µs

t6 350 µs

Digital to analog converter PM3533

42/77 CD00271682 Rev 3

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9 Digital to analog converter

There is one 6–bit D/A converter inside PM3533 designed for PA bias control. The converter is supplied from VHI –supply and it provides a maximum output current up to a 2.2 V output voltage level. The DAC output is multiplexed between two different outputs PADAC1 and PADAC2. The DAC value and multiplexing are controlled via SPI.

Figure 16. DA-converter block diagram

Note: Unused PADAC output should be left floating (it is internally pulled-down while at an off state).

Operation characteristics are presented in Table 21.

Table 21. D/A-converter characteristics

Symbol Characteristics Condition Min Typ Max Unit Note

N Resolution 6 bits

Iout, maxMax output source current DAC1

I_CTRL=x, Vout<2.3V

2.2 2.5 mA

Iout, min Min output source currentI_CTRL=0, Vout=0V

0 mA

LSB step sizeI_CTRL=x, Vo<2.6V

Iout, max/63

mA

PM3533 Digital to analog converter

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CD00271682 Rev 3 43/77

In addition to normal usage of the current mode PADAC it is possible to use extra added feature in order to use a coded output current to have a better accuracy of PADAC output current. During a mass-production phase and its OTP fusing phase PADAC output current by a certain code of 48 [in dec] is read/saved to certain register bits so this information can be taken into use by combining dedicated bits. Look at the register table in the end part of this datasheet for further details of registers available.

The application sw is able to read these dedicated bits in the following way:

After a normal power-up, read reg15.bit_numbers of [10,5,0] + reg2.bit[7] = MSB…LSB order of bits for saved value and by looking at the accurate measured output current value like it is coded in the table below.

INL1 Integral non-linearity 1.5 LSB

Monotonic behavior required @ VHI = 2.5 V

INL2 Integral non-linearity 0.9 LSB

Monotonic behavior required @ VHI = 2.6 V

DNL Differential non-linearity 0.5 LSB

Maximum output voltage 2.2 V

DAC output voltage in PD 100 mV

Mux_res

Internal mux switch

(use external resistor of 47ohm to get max of 100ohm as worst case)

35 55 mΩ

Table 21. D/A-converter characteristics (continued)

Symbol Characteristics Condition Min Typ Max Unit Note

Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values

Coded value [in decimal] Corresponding value [mA]

0 1.600

1 1.645

2 1.690

3 1.735

4 1.780

5 1.825

6 1.870

7 1.915

8 1.960

9 2.005

10 2.050

11 2.095

Digital to analog converter PM3533

44/77 CD00271682 Rev 3

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The following kind of an accuracy can be achieved through setting of reg9.bits[15...9] i.e. ‘1100001’ which equals to 48 [in dec] + enable_bit_of_padac. This setting is used while the coded value is saved like informed for corresponding output current values in the table above, thus being saved during the fusing phase of the mass-production testing

Then it is straightforward to use this information like matching a linear equation with the following characteristic equation:

PADAC_output_current(Padac_output_code_wanted)

= (y_offset / (48 - 1)) * (Padac_output_code_wanted - 1) + min_LSB_size

In which

min_LSB_size = 33uA

y_offset = Coded_value - min_LSB_size

* Coded_value (in μA) is read from the table PADAC coding table

With this added feature the following kind of an accuracy of

PADAC_output_current (Padac_output_code_wanted)

can be achieved as a function of different PADAC control bits in Reg9[15...10]:

Figure 17. Output current accuracy of PADAC coded characteristic equation

12 2.140

13 2.185

14 2.230

15 2.275

Table 23. I/O pad accuracy

I/O PAD Parameter Min Typ Max Unit

PADAC1 or PADAC2

Accuracy by ‘1100001’- value -50 +50 μΑ

Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values

Coded value [in decimal] Corresponding value [mA]

PM3533 RF controls

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CD00271682 Rev 3 45/77

10 RF controls

Two state IOs re designed to control the antenna switches.

Figure 18. RF control connection

Table 24. RF control voltage output parameters

Signal name


RFC1

Voltage HI LO

2.430

2.512.6

0.05V @ 0mAV @ -1mA

ANT1Resistance sinkResistance source

9550

ohm

Dynamic load 10 20 pF

Switching time 1 us

RFC2

Voltage HI LO

2.430

2.512.6

0.04V @ 0mAV @ -1mA

ANT2Resistance sinkResistance source

9550

ohm


Switching time 1 us

RFC3

Voltage HI

LO

2.43

02.51

2.6

0.04

V @ 0mA

V @ -1mA

RFCTRL3 (other mode of muxed I/O)

Resistance sink

Resistance source

95

50ohm


Switching time 1 us

Thermal shutdown PM3533

46/77 CD00271682 Rev 3

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11 Thermal shutdown

The thermal shutdown block protects the PM3533 from over-heating. The TSD block is used to shutdown functions when the temperature threshold limit is reached. When the temperature level is reached TSD shuts down the power stages of all converters, however all other PM3533 blocks are still active.

The TSD function is enabled automatically whenever a power-up sequence is controlled. See the power-up diagrams for futher details in Figure 23.

Figure 19. Thermal shutdown functional of modes

Table 25. Thermal shutdown parameter table

Parameter Name Control bit Min Typ Max Unit

Temperature threshold

Tt170Fuse <1:0> =11

147 170 183 °C

Tt160Fuse <1:0> =10

137 160 173 °C

Tt150Fuse <1:0> =00

127 150 163 °C

Tt140Fuse <1:0> =01

117 140 153 °C

Hysteresis ΔT 13 17 °C

Current consumption

IddTemp = 130

Temp = 170

14

21

17

35µA

AccuracyWith mismatching

<10 °C

PM3533 OTP memory

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CD00271682 Rev 3 47/77

12 OTP memory

One time programmable memory cell (OTP) is used for tuning purposes during PM3533 mass-production testing phase.

Basic functionality of OTP macro cell: data is programmed serially through SCANIN pin on each CLOCK rising edge. OTP is programmed using an external high voltage HV solder bump at a wafer level. To sense the data stored in cell, a RESET pulse is required after power on. Fuse_ok signal indicates that data is available on D0 to D39 pins. PROG pin is needed to select the 20-bit block for the programming.

PM3533 digital cell includes a multiplexer, which needs enabling and Fuse_ok controlling bits. Fuse_ok is generated during the OTP programming procedure, it indicates if the data_set is corrupted. If Fuse_ok is “1” and enable Reg14(15) bit is “0” the data set from antifuse can be used. If Reg14(15) is high and Fuse_ok is low, the multiplexer outputs the data which is programmed in register REG14(15:0). Reg15(15:0), Reg13(3:0) and Reg12(15:0) can be used to read the whole OTP(39:0) memory content of two 20-bit memory blocks, these are available through the SPI (Serial Peripheral Interface) access to read all the OTP memory bits.

Figure 20. Simplified OTP bits connection diagram

Battery monitoring PM3533

48/77 CD00271682 Rev 3

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13 Battery monitoring

PM3533 includes a battery monitoring block. This block provides a scaled-down battery voltage information for a transceiver IC ADC through the MUX1 output ball.

Table 26. Battery monitoring characteristics


VBAT_inf VBAT/4 VPM3533 battery information output voltage.

Initial accuracy 0.1% %Battery monitoring accuracy device to device over temperature range

Load accuracy0.2% @ 100Meg

2% @ 10Meg%

Battery monitoring accuracy vs. load resistance

PM3533 Under-voltage-lockout block

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CD00271682 Rev 3 49/77

14 Under-voltage-lockout block

PM3533 includes an Under Voltage Lockout block. This block provides special protection mode to PM3533 and especially to its boost power converter while it is working at full-power mode and the modes of operation include sudden or abnormal power-downs (i.e. uncontrolled states of critical supply voltages like those are disappearing suddenly especially VBAT and/or VXO before XRESET signal is set low by an external control see Figure 24.)

When UVL triggers it disables the internal control signals of the boost converter block which further disables the power stages of this converter making it disabled. This way boost converter is inhibited to have unwanted overshoots at its output voltage during like out-of-spec (VBAT/VXO uncontrolled power-downs) situations.

This function is automatically enabled when normal power-up is controlled, as shown in Figure 23. The function is kept enabled by hard-wired internal control signals. Only the Xreset signal asserting to '0' disables this function (at the reset state of PM3533).

Figure 21. Under-voltage-lockout block overview

Table 27. Under Voltage Lockout characteristics


VBAT_trig 2.35 2.37 2.39 VUVL_Ena at low state & XRESET at high state

VBAT_trig_hyst 170 mVBoost_off to Boost_on, that is VBAT level of 2.54 V before boost_turned_on again

VXO_trig 1.89 1.90 1.92 VUVL_Enal at low state & VXO_Mon_Ena at low state & XRESET at high state

VXO_trig_hyst 60 mVBoost_off to Boost_on i.e. VXO level of 1.96 V before boost_turned_on again

Mux structure PM3533

50/77 CD00271682 Rev 3

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15 Mux structure

PM3533 includes several nodes which can be multiplexed to MUX1 output pin or MUX2 output pin.

Figure 22. PM3533 multiplexer structure

s_drw_out

Empty

THPROTOUT

2

4

5

6

7

Empty

B_drw_in

9

10

11

12

13

8

MUX MAP for KAURA20

1

2

3

4

INPUT_SMPS

IND_SMPS

OUT_BOOST

IND_BOOST

MUX2

14

d_drw_out

b_drw_out

1_1

1_2

1_3

3

6mA_smps

6mA_dcdc

6mA_boost

4_5

4_6

4_7

VHI

4_4

VREG50S

4_3

VREG50BD

4_2

6mA_Vdig

4_1

D_drw_in

5

IND_DCDC

5

IND_DCDC

MUX1

Ritsa_drw_out

1_4

Vbb_VRX

6GND_DCDC

7GND_BOOST

8GND_SMPS

9

Mux dcdc

empty

Batman

Mux_boost

Temp

15

Mux_smps

Ol

VIO

VIO

PM3533 Mux structure

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CD00271682 Rev 3 51/77

15.1 MUX 1 controls

Table 28. MUX1 register writings

Switch Reg Bit value Explanation

1 reg6 bits 5,4,3 001

2 Reserved 011

3 Reserved 010

4 Reserved 100

5 Reserved 101

6 Reserved 110

7 Reserved 111

8 Reg6 bits 2,1,0 001 BOOST_MUX

9 Reserved 010 TEMP

10 Reserved 011 SMPS_MUX

11 Reserved 100 DCDC-MUX

12 Reserved 101 (empty)

13 Reserved 110 BATMAN

14 Reg6 bit 15 0/1 1 = Enables sw 1-7 output to sw 14

15 Reg1 bit 0 0/1 1 = Enables sw 1,2 output to sw 15

1_1 Reg06 bit9,10 1/0 01 = CLK DCDC 10 = CLK SMPS 11 = CLK Boost

1_2 Reg06 bit9,10 1/0

1_3 Reg06 bit9,10 1/0

1_4 Reg06 bit7, Reg06bit9,10 Reg06 bit7 =1, Reg06bit9,10 =00

4_1 Reg01 bit 11,10,9 001

4_2 Reserved 010

4_3 Reserved 011

4_4 Reserved 100

4_5 Reserved 101

4_6 Reserved 110

4_7 Reserved 111

Mux structure PM3533

52/77 CD00271682 Rev 3

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15.1.1 PM3533 self test

PM3533 has several Kelvin nodes which can be multiplexed to output pin MUX1 (see Figure 22). In closed-loop mode environment PM3533 MUX1 output pin is connected to the RF IC ADC which enables PM3533 self testing measurements.

Table 29. PM3533 Kelvin nodes for self test purpose

Kelvin nodeOutput ball what will be self tested

Expected voltage

value at pin MUX1

Register setupReg01

Register setupReg06

Reg06Note

Bit 11 Bit 10 Bit 9 Bit 2 Bit 1 Bit 0 Bit 15

Batman VBATT

Battery voltage

divided by four

0 0 0 1 0 0 0Battery monitoring

VIO

VBB_VRX, VREF, VIO, GND_VIO, VXO

0.9 0 1 1 0 0 0 1

Driver stage supply voltage

VIO

VBB_VRX, VREF, VIO, GND_VIO, VXO

0.9 0 1 0 0 0 0 1

Driver stage supply voltage

VHI 1.3 1 0 0 0 0 0 1Regulator output

PM3533 Modes of operation

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CD00271682 Rev 3 53/77

16 Modes of operation

The device has several operating modes. There are a few active modes, power–down mode and several test modes. Most of the blocks can be turned on and off individually through the serial interface. The operating modes are described in the following sections.

16.1 Power UP/DOWN sequencePower UP/DOWN sequence described here must always be followed when powering the IC UP or DOWN (an order of external supply voltages and control signals). Mis-use of the IC can lead to shorter lifetime. The timing diagram below is representative only and therefore real power-up timings are linked to different application use cases and external filtering components (for instance on the external Vref line).

Note: Internal VDIG_int which gives a supply voltage to the digital interface of PM3533 follows approximately a rise time of the Vref line after high state of which (five worst case time constants of RextCext) PM3533 is ready to receive more accesses for controls i.e. external component filtering on the vref line dominates the wake-up time of PM3533 added with max current capability of an external buffer driving this external Vref line during its rising period. After all this Xreset is released and control accesses are allowed.

Figure 23. Power up sequence timing diagram

Table 30. Power up timing values

Name Time Unit

t0 0 μs

t1 30 μs

t2 270 μs

t3 300 μs

t4

Modes of operation PM3533

54/77 CD00271682 Rev 3

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Figure 24. Power down sequence timing diagram

Table 31. Power down timing values

Name Time Unit

t5 μs

t6 -40 μs

t7 -30 μs

t8 Reference μs

PM3533 Control interface

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CD00271682 Rev 3 55/77

17 Control interface

17.1 Data interfacePM3533 is programmed via the serial bus (SLE,SDATA,SCLK and RESET). SDATA data is clocked by SCLK rising edge. The data is fed with MSB first and address bits before data bits. PM3533 is in RESET state, when RESET signal is logical low.

Figure 25. Timing waveform of writes cycle

Note: On SCLK rising edge, one bit of data is shifted in the shift register. SLE should be kept high when the interface is not used

Figure 26. Timing waveform of read cycle

Note: Data should read at the falling edge of SCLK.

Table 32. Data interface timings

Levels Min Max Unit

High 1.5 V

Low 0.5 V

Address Data

A2 A1 A0 MSB LSB

SCLK

SDAT

SLE

A3A4A5 R/WA6A7

Control interface PM3533

56/77 CD00271682 Rev 3

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Figure 27. Serial data input timing

Note: Clocking frequency should be approximately 19.2 MHz.

SCLK

SDAT

SLE

tslctsdc

tcl

tch thcd

tlh

tclk

tsll

Table 33. SPI control signal timing table

Symbol Parameter Min Max Unit

tclk Clock cycle 52 ns

tch SCLK high period 0.4*tclk 0.6*tclk ns

tcl SLK low period 0.4*tclk 0.6*tclk ns

tslc SLE to SCLK setup time 0.8*tcl 1.2*tcl ns

tsdc SDAT to SCLK setup time 0.8*tcl 1.2*tcl ns

tsll SLE to last clk setup time 0.8*tcl tcl ns

thcd SCLK to SDAT hold time 0.8*tch 1.2*tch ns

tlh SLE high period tclk ns

PM3533 Pin description

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CD00271682 Rev 3 57/77

18 Pin description

18.1 PM3533 ball-out

Figure 28. PM3533 ball-out diagram

Pin description PM3533

58/77 CD00271682 Rev 3

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18.2 PM3533 pin description

Table 34. PM3533 pin description

Pin nameBGA ball

Type GroundESD

Supply Voltage

Function

FB_DCDC A1 I GND_DIG DC-DC-converter feedback

MUX1 C4 O GND_DIG VXO Multiplexer output

FB_BOOST B1 I GND_DIG Boost-converter feedback

ANT_T2 B2 O GND_DIG Buffered digital output

ANT_T1 C2 O GND_DIG Buffered digital output

PA_DAC1 C1 O GND_DIG 1st Current DAC output

GND_DIG E1 G GND_DIG Ground

GND_DIG A2 G GND_DIG Ground

GND_DIG B3 G GND_DIG Ground

GND_DIG C3 G GND_DIG Ground

GND_DIG D3 G GND_DIG Ground

GND_DIG D4 G GND_DIG Ground



GND_DIG F3 G GND_DIG Ground

GND_DIG G3 G GND_DIG Ground

VXO D2 S GND_DIG 2.5V / 2.15V supply voltage

VREF D1 S GND_DIG 1.2V reference voltage

SCLK G1 I GND_DIG VXO SPI clock input

DATA F1 I GND_DIG VXO SPI data input

ENABLE F2 I GND_DIG VXO SPI enable input

XRESET E4 I GND_DIG VXO SPI XRESET input

SMPS_CTRL G2 I GND_DIG VXO SMPS-converter control voltage

FB_SMPS H1 I GND_DIG SMPS-converter feedback

VHI H2 O GND_DIG VHI 2.6V / 2.5V regulated output

Vbb_VRX H3 S GND_VIO Vbb_VRXBattery input supply voltage for converter regulators and VHI-regulator

VIO H4 O GND_VIO VIO 1.8V driver stage supply voltage

GND_VIO G4 G GND_VIO Ground for VIO

PADAC2 / RFCTRL3 F4 S GND_DIG2nd Current DAC output / Additional buffered digital output

GND_VIO F5 G GND_VIO Ground

PM3533 Pin description

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CD00271682 Rev 3 59/77

CB_SMPS H5 I GND_VIO CB_SMPS SMPS-converter boost-trap input

MUX2 G5 O GND_VIO MUX2 High voltage multiplexer output

GND_SMPS H6 G SMPS-converter ground



IND_SMPS G6 O SMPS-converter output



INPUT_SMPS F6 I SMPS-converter input



OUT_BOOST E5 O Boost-converter output




IND_BOOST D5 I Boost-converter input




GND_BOOST C5 G Boost-converter ground




VBATT B8 S GND_VIO VBATT DC-DC-converter input

VBATT A8 S GND_VIO VBATT DC-DC-converter input

IND_DCDC A7 O DC-DC-converter output

IND_DCDC B7 O DC-DC-converter output

GND_DCDC B5 G DC-DC-converter ground

GND_DCDC B6 G DC-DC-converter ground

CB_BOOST A6 I GND_VIO CB_BOOST Boost-converter boost-trap input

GND_VIO A5 G GND_VIO

CB_DC-DC B4 I GND_VIO CB_DC-DC DC-DC-converter boost-trap input

Table 34. PM3533 pin description (continued)

Pin nameBGA ball

Type GroundESD

Supply Voltage

Function

Pin description PM3533

60/77 CD00271682 Rev 3

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VIO A4 I GND_VIO VIO 1.8V driver stage supply voltage

Vbb_VRX1 A3 S GND_VIO VBB_VRX No connection

Table 34. PM3533 pin description (continued)

Pin nameBGA ball

Type GroundESD

Supply Voltage

Function

PM3533 PM3533 register description for closed-loop mode

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CD00271682 Rev 3 61/77

19 PM3533 register description for closed-loop mode

PM3533 closed-loop mode control registers are listed in this chapter.

SPI device address ID is ‘110’ (in binary format) for address decoding of A7...A5 like in Figure 25.

Table 35. Register 0

Register 0 Valid state Name Bit functional description

bit 0 Reserved

bit 1 Reserved

bit 2 Reserved

bit 3 Reserved

bit 4 1 Common BIAS enable Enables common bias OpA

bit 5 Reserved

bit 6 Reserved

bit 7 Reserved

bit 8 1 REGU6ma_B_ctrl Enable for boost_ctrl_int.regu6ma

bit 9 1 REGU6ma_DC-DC_ctrl Enable for DC-DC_ctrl_int.regu6ma

bit 10 1 REGU6ma_s_ctrl Enable for smps_ctrl_int.regu6ma

bit 11 1 PADAC_mux_sel 0' for PADAC1; '1' for PADAC2

bit 12 0/1closed-loop mode_Mode_Sel

closed-loop mode1='0' VHI=2.6 V, closed-loop mode2='1' VHI=2.5V

bit 13 0 REGU_VHIEnable for REGU_VHI. (This is also an internal supply voltage for the PA_DAC).

bit 14 0 REGU_VHI_Vext Enable for REGU_VHI

bit 15 Reserved



bit 0 1 Input_ENEnable control for the output on MUX1 by '001','010' or '011' selections

bit 1 Mux_HV_ctrl C3 (used only in test phase)

bit 2 1 TSD TESTENABLEThermal shutdown test-enable (‘1’=test mode)

bit 3 0 TSD THSDENAThermal protection enable (‘0’ for application mode enable)

bit 4 1 Mux_HV_ctrl C3 (used only in test phase)

bit 5 1 DIG_load (used only in test phase)

PM3533 register description for closed-loop mode PM3533

62/77 CD00271682 Rev 3

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bit 6 1 ENa_TEMPEnables functional measurement in test mode

bit 7 1 TSD_fuse1TSD_temp_ctrl => 00 150C;10 140C; 01 160C; 11 170C (used in test mode)

bit 8 1 TSD_fuse0TSD_temp_ctrl => 00 150C;10 140C; 01 160C; 11 170C (used in test mode)

bit 9 1 Mux_VREG_ctrl_C2 (used only in test phase)





bit 14 1 Mux_HV ctrl_C0 (used only in test phase)

bit 15 1 OTP_prog_ena Enables OTP signal paths in test phase

Table 36. Register 1 (continued)



Register2 Valid state Name Bit functional description

bit 0 1 AFForce_bit[15]; RETKUInternal AFForce_bit[15].Frequency reduction enable; 1.79MHz minus offset to the SMPS value in register 14.

bit 1 1 AFForce_bit[16]; ITKUInternal AFForce_bit[16].Frequency increasing enable; 1.35MHz plus offset to the SMPS value in register 14.

bit 2 1 AFForce_bit[17] Internal AFForce_bit[17]



bit 5 read only FuseData[15]FuseData[15]; Programmed OTP RETKU bit. To read it keep reg15.bit='0'.

bit 6 read only FuseData[16]FuseData[16]; Programmed OTP ITKU bit. To read it keep reg15.bit='0'.

bit 7 read onlyFuseData[39]/AFForce_bit[17]

FuseData[39]. This is used for in serial read-out of OTP memory. Keep reg14.bit15='0' to see this serial clocked data stream output i.e. D39.PADAC coded bit number 0 (LSB), others look at register 15.

bit 8 read only FuseData[18]FuseData[18]. Programmed THSD Fuse0 bit. To read it keep reg15.bit='0'.

bit 9 read only FuseData[19]FuseData[19]. Lower OTP mem MSB bit. Programmed THSD Fuse1 bit. To read it keep reg15.bit='0'.


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CD00271682 Rev 3 63/77

bit 10 0/1 tsd_mux1_ena‘0' for enable sr_latch to output tsd_out state in pwmreg1.bit15; '1' reset sr_latch output node to low state in pwmreg1.bit15.

bit 11 0/1 rds_smps_low_high_enaIn test mode smps rds_on low/high side sw can be set; '0' for low side; '1' for high side

bit 12 0/1 rds_boost_low_high_enaIn test mode boost rds_on low/high side sw can be set; '0' for low side; '1' for high side

bit 13 0/1 rds_dcdc_low_high_enaIn test mode dcdc rds_on low/high side sw can be set; '0' for low side; '1' for high side

bit 14 0/1 test_otp_resetIn test_mode: '1'->'0' sequence to manually set otp_reset_pulse for OTP_cell

bit 15 1 long_delaySMPS: the 5th delay tune for very high load impedances; when used set reg3.bit[3...0]='1000'





bit 0 1 SMPS_ast_lDelay tune for low side of driver chain; beneficial for having minimum dropout voltage (used ext coil res affects)

bit 1 1 SMPS_ast_lDelay tune for low side of driver chain;

beneficial at larger range of power levels (GSM)

bit 2 1 SMPS_ast_l

Delay tune for low side of driver chain;beneficial at larger range of power level (GSM) but with larger dropout voltage (used ext coil res affects)

bit 3 1 SMPS_ast_lDelay tune for low side of driver chain; beneficial mid-to-low-power range loads (WCDMA)

bit 4 1 Dither bandwidth 0 for 2.8MHz; 1 for 5.6MHz

bit 5 1 SMPS_Dither_ena SMPS dither enable

bit 6 1 SMPS_drw_inout SMPS drw in/out enable

bit 7 1SMPS_CTRL_bias/comp/sawt

Enable for smps_ctrl bias. Enable for smps_ctrl comparator/sawtooth

bit 8 1 SMPS mode selection

SMPS mode selection 00=PD, 01=bypass, 10=section, 11 normal (bits as bit '9', bit '8' order) Cdoup_SMPS is enabled also with 01=bypass

bit 9 1 SMPS mode selection (used with bit 8)


64/77 CD00271682 Rev 3

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bit 10 1 SMPS_CTRL_opamp

I/O mux control and SMPS opamp enable control (0 = I/O MUX to TSD_testforce, 1 = enables SMPS opamp and disables routing to TSD_testforce)

bit 11 Reserved

bit 12 Reserved

bit 13 Reserved

bit 14 Reserved

bit 15 Reserved





bit 0 Reserved

bit 1 Reserved

bit 2 Reserved

bit 3 Reserved

bit 4 1 Dither bandwidth 0 for 2.8MHz; 1 for 5.4MHz

bit 5 1 BOOST_XCLR BOOST dither enable

bit 6 1 BOOST_drw_inout BOOST drw in/out enable

bit 7 1BOOST_CTRL_bias/comp/sawt

Enable for boost_ctrl bias. Enable for boost_ctrl comparator/sawtooth

bit 8 1 Boost mode selection

Boost mode selection 00=PD, 01=bypass, 10=section, 11 normal (bits as bit '9',bit '8' order). Cdoup_boost is enabled also with 01=bypass

bit 9 1 Boost mode selection (used with bit 8)

bit 10 1BOOST_sampled_start_control

Enable for BOOST soft start; starts at sampled output voltage

bit 11 1 BOOST_CTRL_opamp Boost gain opamp enable control

bit 12 1BOOST_sampled_start_control

Enable for BOOST soft start; starts at sampled output voltage; this bit is left for software compatibility (as it was like fast_start before)

bit 13 Reserved

bit 14 Reserved

bit 15 Reserved


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CD00271682 Rev 3 65/77



bit 0 Reserved

bit 1 Reserved

bit 2 1 BOOST_loopfb1dBOOST feedback setting control: enables added parallel resistor to resistor divider

bit 3 Reserved

bit 4 Reserved

bit 5 1 Mux B C0Mux Boost control bits(used only in test phase)

bit 6 1 Mux B C1Mux Boost control bits(used only in test phase)

bit 7 1 Mux B C2Mux Boost control bits (used only in test phase)

bit 8 1 BOOST_loop_fb1aBOOST feedback setting control: enables also lim_opamp when _fb1x (x=a or b or c) bits are set

bit 9 1 BOOST_loop_fb1bBOOST feedback setting control: _fb1a & _fb1b set output-to-ref gain value to internal decoder

bit 10 1 BOOST_loop_fb1cBOOST feedback setting control: _fb1c enables dc path to error opamp. This bit is internally controlled by boost soft_start bit.

bit 11 1 BOOST_loop_fb2 BOOST feedback setting control

bit 12 1 BOOST_loop_fb2 BOOST feedback setting control

bit 13 1 BOOST_1,5megAdds 1.5meg resistor into feedback loop(used only in test phase)

bit 14 1 BOOST_C_shunt Adds shunt capacitor into feedback loop

bit 15 1 BOOST_paraRAdds parallel resistor into feedback loop(used only in test phase)



bit 0 1 Mux 1 C0Set ‘1’ for Battery Monitor mux output enable for decoder



bit 3 1 Mux 2 C0 (used only in test phase)




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bit 6 1 Batman_ENA Enable control for Batman_out

bit 7 1 Batman_KelvinH('0' for res_div (set bit8 to '0'); '1' for res_meas (set bit8 to '0'); test structures)

bit 8 1 Batman_KelvinL('0' for res_div (set bit7 to '0'); '1' for hi-Z state (set bit7 to '1'); test structures)

bit 9 1 Clock divider enable(‘00’ = PD, '10'=DC-DC_clock '01' = SMPS_CLOCK, 11 = Boost_clock (bits 9,10 order); used only in test phase)

bit 10 1 Clock divider enable (used only in test phase)

bit 11 1ANT_T1_T2_RFCTRL3_ctrl

Enabling digital buffers for ANT_T1, ANT_T2, RFCTRL3 I/Os, 1= Digital buffers enabled in application mode, 0= OTP_clock @ANT_T1 and TSD_testsense @ANT_T2 enabled in test mode.

bit 12 1 RFCTRL3_setEnable switch for RFCTRL3, 1=digital high state, 0=digital low_state

bit 13 1 ANT_T1_antsw_setANTENNA tuning switch control, 1=digital high state, 0=digital low_state

bit 14 1 ANT_T2_antsw_setANTENNA tuning switch control, 1=digital high state, 0=digital low_state

bit 15 1 MUX switch(0 = mux outputs 8- 13,1 = mux outputs 1-7; used in test phase)





bit 0 1 SMPS_loop_fb3

SMPS feedback setting control: linked to 0x5C01 setting (and alternatively 0x5C0D with reg2.bit0=’1’ and reg14.bit15=’1’ for lowest switching freq), additionally 0x5C05 or 0x5C09 (=recommended) with reg2.bit0='1' and reg14.bit15='1' for the semi-lowest switching frequency

bit 1 1 Open_gain_incEnables open loop gain increment option (especially in EER/ET architecture)

bit 2 1 Freq_red1

Additional smps freq reduction (bits of [3...2] combines 4 selections); can be used in GSM/WCDMA (in OTP or in free-running OSC modes)

bit 3 1 Freq_red2

Additional smps freq reduction (bits of [3...2] combines 4 selections); can be used in GSM/WCDMA (in OTP or in free-running OSC modes)


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CD00271682 Rev 3 67/77

bit 4 1 dcg_bitDC gain increment: '0'=3.18; '1'=3.40; dgc equals to smps_out / smps_ctrl

bit 5 1 Mux S C0 (Mux SMPS control bits; in test phase)



bit 8 1 SMPS_loop_fb1SMPS feedback setting control (external L-C effects on usage)





bit 13 1 SMPS_1uFSMPS 1uF cap enable bit. Note: enable also bit numbers 10,11 and 14 for response tuning

bit 14 1 SMPS_C_shunt Adds shunt capacitor into feedback loop

bit 15 1 SMPS_paraR(Adds parallel resistor into feedback loop; used in test phase)





bit 0 Reserved

bit 1 Reserved

bit 2 Reserved

bit 3 Reserved

bit 4 1 DC-DC_Dither bandwidth 0' for 1.19MHz; '1' for 2.3MHz

bit 5 1 DC-DC_XCLR DC-DC_dither enable

bit 6 1 DC-DC_drw_inout DC-DC drw in/out enable

bit 7 1 DC-DC_CTRL_biasEnable for DC-DC_ctrl bias. Enable for boost_ctrl comparator/sawtooth.

bit 8 1 DRV XPD Driver stage enable

bit 9 1DC-DC- sampled_start_control

Enable for DC-DC soft start; starts at sampled output voltage

bit 10 Reserved

bit 11 1 DC-DC_CTRL_opamp DC-DC control opamp enable


68/77 CD00271682 Rev 3

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bit 12 1DCDC_

sampled_start_control

Enable for DC-DC soft start; starts at sampled output voltage; this bit is left for sw compatibility (because it was like fast_start before)

bit 13 1 DC-DCmux (DC-DC mux C0; used in test phase)







bit 0 1 DC-DC_loop_fb1 DC-DC feedback setting control





bit 5 Reserved

bit 6 1 DC-DC_C_shunt Adds shunt capacitor into feedback loop

bit 7 1 DC-DC_paraR(Adds parallel resistor into feedback loop; used only in test phase)

bit 8 1 OVER2VENA(Enables 2.5V @Vref=1.2V; normally not used in the closed-loop configuration of SMPS usage in the rf subsystem)

bit 9 1 PA_DAC_XPD Enable for PA_DAC

bit 10 1 PA_DAC bit0 PA DAC control








bit 0 read only FuseDR[0] FuseDR[0] (Upper OTP mem LSB bit)

bit 1 read only FuseDR[1] FuseDR[1]






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CD00271682 Rev 3 69/77


















bit 3 read only FuseDR[19] FuseDR[19] (Upper OTP mem MSB bit)

bit 4 read only Version_bit0 Coding of versions as follows (bit3...bit0)

bit 5 read only Version_bit1PM3533: ‘001’ for v1.0PM3533: ‘010’ for v1.0B

bit 6 read only Version_bit2

bit 7 read only Version_bit3

bit 8 read only Family_bit0 Coding of RF PM IC family

bit 9 read only Family_bit1 PM3533: ‘010’

bit 10 read only Family_bit2

bit 11 read only Man_bit0 Coding of RF PM IC manufacturer

bit 12 read only Man_bit1 PM3533: ‘111’

bit 13 read only Man_bit2

bit 14 Reserved

bit 15 Reserved



bit 0 1 SMPS_clock_freqThese bits adjust switching frequency so that bits 00000 gives minimum freq

bit 1 1 SMPS_clock_freq and 11111 gives max freq.


70/77 CD00271682 Rev 3

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bit 2 1 SMPS_clock_freqFor SMPS: '00000': 6.48 MHz; '01101': 9.54 MHz; '01110': 9.77 MHz;

bit 3 1 SMPS_clock_freq '11111': 13.59 MHz (typical values)

bit 4 1 SMPS_clock_freq(SMPS: Calibration range in the OTP used mode is 7.1 - 10.1 MHz when reg7.bit[3...2]=’00’)

bit 5 1 BOOST_clock_freqThese bits adjust switching frequency so that bits 00000 gives minimum freq

bit 6 1 BOOST_clock_freq and 11111 gives max freq.

bit 7 1 BOOST_clock_freqFor Boost: '00000': 4.51 MHz; '01101': 7.52 MHz; '01110': 7.74 MHz;

bit 8 1 BOOST_clock_freq '11111':11.42 MHz (typical values)

bit 9 1 BOOST_clock_freq(Boost: Calibration range in the OTP used mode is 6.8 - 8.0 MHz)

bit 10 1 DC-DC_clock_freqThese bits adjust switching frequency so that bits 0000 gives minimum freq

bit 11 1 DC-DC_clock_freq and 1111 gives max freq.

bit 12 1 DC-DC_clock_freqFor RF-IC DCDC: '00000': 1.62 MHz; '01110'': 2.75 MHz;

bit 13 1 DC-DC_clock_freq'01111':2.83 MHz; '11111': 4.09 MHz (typical values)

bit 14 1 DC-DC_clock_freq(DCDC: Calibration range in the OTP used mode is 2.45 - 2.84 MHz)

bit 15 1 DATA_ENA0' sets OTP mode which uses trimmed values; '1' is for user set values.




Reg 15 Valid state Name Bit functional description

bit 0 read only FuseData[0]FuseData[0] (Lower OTP mem LSB bit) / PADAC coded bit number 1

1 read only FuseData[1] FuseData[1]




5 read only FuseData[5] FuseData[5] / PADAC coded bit number 2






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CD00271682 Rev 3 71/77

10 read only FuseData[10]FuseData[10] / PADAC coded bit number 3




14 read only FuseData[14] FuseData[14] (bits[19...15] in Reg2)

15 read only FUSE_OK Internal Fuse_ok


Reg 15 Valid state Name Bit functional description

Example of WCDMA output power distribution curve PM3533

72/77 CD00271682 Rev 3

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20 Example of WCDMA output power distribution curve

The most important driver for PM3533 is to increase efficiencies in WCDMA low power levels. Figure 29 presents the DG09 WCDMA output power distribution curve. The power distribution curve shows that in WCDMA system the mobile transmitter is almost all of the time in power level area comprised between 6 dB and -12 dB.

Figure 29. DG09 WCDMA output power distribution curve

PM3533 Package information

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CD00271682 Rev 3 73/77

21 Package information

21.1 Package mechanical data

Table 49. VFBGA 3.4 mm x 3.4 mm x 1.0 mm with 0.4 mm pitch and 0.25 mm ball

Ref. Min. Typ. Max. Unit

A(1)

1. VFBGA stands for Very thin profile Fine pitch Ball Grid Array.- Very thin profile:.

- The total profile height (Dim A) is measured from the seating plane to the top of the component.- The maximum total package height is calculated by the following methodology:

1.00 mm

A1 0.125 mm

A2 0.19 mm

A4 0.585 mm

b(2)

2. The typical ball diameter before mounting is 0.25 mm.

0.22 0.26 0.30 mm

D 3.30 3.40 3.50 mm

D1 2.80 mm

E 3.30 3.40 3.50 mm

E1 2.80 mm

e 0.40 F mm

Z 0.30 mm

ddd 0.08 mm

eee(3)

3. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

0.15 mm

fff(4)

4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.

0.05 mm

0.80 A 1.00 mm/Fine pitch:e< 1.00 mm≤<

A Max A1Typ= A2 Typ A12

A22

A42

tolerance values+ +( )+ +

Package information PM3533

74/77 CD00271682 Rev 3

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Figure 30. VFBGA 3.4 mm x 3.4 mm x 1.0 mm, 0.4 mm pitch, 0.25 mm ball

1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug.- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner.The exact shape of each corner is optional.

See Note 1

PM3533 Package information

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CD00271682 Rev 3 75/77

21.2 Package markingThe package marking consists of one line.

Figure 31. Marking composition

Table 50. Package marking

Item Description Format Value

A Marking area - Product code 1st line P3533

PACKAGE FACE : TOP LEGEND

Unmarkable Surface

Marking Composition FieldA

B C D

E

A-66669 - MARKING AREAB-66668 - Assy Plant

(P)

C-66670 - Assy Year (Y)

D-66667 - Assy Week (WW)

E-66671 - DOT

Ordering information PM3533

76/77 CD00271682 Rev 3

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22 Ordering information

23 Revision history

Table 51. Ordering information

Order code Package Packing

PM3533BDKT VFBGA 3.4 mm x 3.4 mm x 1.0 mm, 0.4 mm pitch, 0.25 mm ball

Tape on reel

Table 52. Document revision history

Date Revision Changes

07-May-2010 1 Initial release.

26-Oct-2010 2

Updated

– Table 6: SMPS operation parameters– Table 8: SMPS capacitor specification– Table 11: Boost converter operation parameters– Table 14: DC-DC closed-loop mode electrical characteristics– Table 15: Buck DC-DC converter operating parameters– Section 8.1: VHI regulator (first sentence)

– Chapter 11: Thermal shutdown (second paragraph)– Chapter 14: Under-voltage-lockout block (third paragraph)– Table 34: PM3533 pin description (update for VHI)

– Table 35: Register 0 (bit 5, bit 6, bit 12)– Table 46: Register 13 (bit 5)– Table 51: Ordering information– The Note 1 in Chapter 21: Package informationAdded– Section 21.2: Package marking

16-Dec-2010 3

Updated– The cover page: document title, description, applications and

feature list– Chapter 1: Overview

– Chapter 2: General specifications – Table 6: SMPS operation parameters– Section 8.1: VHI regulator – Table 10: Boost full power mode general electrical characteristics– Table 11: Boost converter operation parameters– Table 25: Thermal shutdown parameter table– Table 34: PM3533 pin description– Table 40: Register 5, Table 42: Register 7

PM3533

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CD00271682 Rev 3 77/77

CONFIDENTIALITY OBLIGATIONS:

This document contains sensitive information.Its distribution is subject to the signature of an Non-Disclosure Agreement (NDA).It is classified “COMPANY RESTRICTED.

At all times you should comply with the following security rules(Refer to NDA for detailed obligations):

Do not copy or reproduce all or part of this documentKeep this document locked away

Further copies can be provided on a “need to know basis”, please contact your local ST-ERICSSON sales office.

Please Read Carefully:

The contents of this document are subject to change without prior notice. ST-Ericsson makes no representation or warranty of any naturewhatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to warranties ofmerchantability or fitness for a particular purpose, interpretability or interoperability or, against infringement of third party intellectual propertyrights, and in no event shall ST-Ericsson be liable to any party for any direct, indirect, incidental and or consequential damages and or losswhatsoever (including but not limited to monetary losses or loss of data), that might arise from the use of this document or the information in it.

ST-Ericsson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of companies or used under a license from STMicroelectronics NV or Telefonaktiebolaget LM Ericsson.

All other names are the property of their respective owners.

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CD00271682_PM3533_datasheet_rev3

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