CBP 2002ITY 270 Computer Architecture1 Digital Logic This Time … Control Path, Arithmetic Ops 12 a...
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CBP 2002 ITY 270 Computer Architecture 1
Digital Logic
This Time … Control Path,
Arithmetic Ops
12
aU1
3 4
bU1
Last Time …
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CBP 2002 ITY 270 Computer Architecture 2
Data Memory
Code Memory
ALU
X
Y
W
X Y
W
0
1
7
Digital Logic Where?
Control Circuits – CPU control path - system board
(later)ALU Structure – add, sub, and, or, not
MUXES
Address Decoder
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CBP 2002 ITY 270 Computer Architecture 3
Boolean Notation, Truth Tables
A and B
AB
A or B
A + B
NOT A
A_
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Easy Way to write truth tables - count in binary !
AB
O
AB
O
A O
A B O
0 0 0
0 1 0
1 0 0
1 1 1
A B O
0 0 0
0 1 1
1 0 1
1 1 1
A O
0 1
1 0
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CBP 2002 ITY 270 Computer Architecture 4
Digi Logic Design 1 - use Gates
ABC
O
A B C O
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
O
0
0
0
1
0
1
1
1 ABC
ABC_
ABC_
ABC_
ABC
ABC
ABC
_
_
ABC + ABC + ABC + ABC__ _
Majority Function
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CBP 2002 ITY 270 Computer Architecture 5
12
1312
aU1
345
6
bU1
91011
8
cU1
1
23
aU3
4
56
bU3
56
cU
2
34
bU
2
12
aU
2
12
1312
aU4
9
108
cU3
A B C
ABC + ABC + ABC + ABC
ABC_
ABC
ABC_
ABC_
___
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CBP 2002 ITY 270 Computer Architecture 6
Address Decoder Exercise
A BO1
O2
O3
O4
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
AB
O1O2O3O4
O1 = AB__
1 2
aU1
1
23
aU2
3 4
bU1
A
B
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CBP 2002 ITY 270 Computer Architecture 7
r0
Decoder Application
r1
r2
r0X
Y
W
X Y
W
Selecting Registers, e.g, add r2,r1,r0
MIPS has 5-bit fields for registers, so are 32
add rd rs rt unused
0
csr0r0
Registers
decoder
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CBP 2002 ITY 270 Computer Architecture 8
MUX Exercise
C A B O
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
A
BOp
C
A
B O
C = 0
A
B O
C = 1
What is MUX doing here ?
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CBP 2002 ITY 270 Computer Architecture 9
MUX is a Selector
1
23
aU1
4
56
bU1
1
23
aU2
12
aU
3
A
BOp
C
A
B
C
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CBP 2002 ITY 270 Computer Architecture 10
Multibit MUX
A
BO
C
A
B
C
1
23
aU1
4
56
bU1
1
23
aU2
12
aU
3
9
108
cU1
12
1311
dU1
4
56
bU2
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CBP 2002 ITY 270 Computer Architecture 11
MUX Application
ALU
Y’
Y
Selection of Datapath into one ALU input.
Datapath Y from instruction add r2,r0,r1
Datapth Y’ from instruction addi r2,r0,4
Sam has been designed so all immediate constants come in via Y’
add rd rs rt unused
Immediate bit of op-code
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CBP 2002 ITY 270 Computer Architecture 12
Address/Data Bus MUXing
CPU MEM
addr
data
CPU MEM
add/dat
address
data
address data
Multiplexed Address/Data Bus, e.g. PCI Bus
Pentium System Bus
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CBP 2002 ITY 270 Computer Architecture 13
Digi design 2 - use MUXes
A B O
0 0 I1
0 1 I2
1 0 I3
1 1 I4
A B
Op
In 1
In 2
In 3
In 4
A B O
0 0 0
0 1 1
1 0 1
1 1 0
A B
Op
0 0
0 1
1 0
1 1
0
1
1
0
“ Muxes can be used to implement arbitrary combinatorial circuits “
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CBP 2002 ITY 270 Computer Architecture 14
MUX Design Exercise
3 input parity detector
A B C O
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
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CBP 2002 ITY 270 Computer Architecture 15
Designing Using ROM/RAM
A B
O
0 0
0 1
1 0
1 1
0
1
1
1
A B
O
0 0
0 1
1 0
1 1
0
1
1
01 1 1 00 1 1 0
decoder
A B
O
O
Several MUX’es fed with the same AB produce a multibit output. So does a ROM or RAM.
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CBP 2002 ITY 270 Computer Architecture 16
Programmable Logic Arrays
FuseABC_
majority
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CBP 2002 ITY 270 Computer Architecture 17
Addition of Binary Numbers
1 0
0 1
Sum = 1Carry = 0
A
B
1 1
1 0
Sum = 0Carry = 1
A
B
1 1 0 1
1 0 0Multibit add - cascade sum and carry ops.
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CBP 2002 ITY 270 Computer Architecture 18
Full Adder
A B Ci S Co
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
S Co
0 0
1 0
1 0
0 1
1 0
0 1
0 1
1 1
Full Adder
BA
Carry In
Carry Out Sum
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CBP 2002 ITY 270 Computer Architecture 19
Full Adder
A B Ci O Co
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
O Co
0 0
1 0
1 0
0 1
1 0
0 1
0 1
1 1
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
1
0
1
0
0
1
SUM
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
0
0
1
0
1
1
1
CARRY
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CBP 2002 ITY 270 Computer Architecture 20
4-bit Adder
Full AdderFull AdderFull AdderFull Adder
a3 a2 a1 a0
b3 b2 b1 b0
s3 s3 s3 s3
0
Carry Out
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CBP 2002 ITY 270 Computer Architecture 21
Let’s Build an ALU
+
B
A
Carry In
Carry Out S1 S0
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CBP 2002 ITY 270 Computer Architecture 22
Issues Concerning Numbers
Multiplication and Division
Subtraction
Negative Numbers
Fractional and Real Numbers
Characters and Strings
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CBP 2002 ITY 270 Computer Architecture 23
Sequential Circuits
Traffic Lights
Washing Machines
Fetch-Execute Cycle
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CBP 2002 ITY 270 Computer Architecture 24
Counters
T0 T1 T2 T3 T4
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Clock
4-bit
Counter
0 1 0 0 (4)
Reset
How to get this to sequence 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 ?
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CBP 2002 ITY 270 Computer Architecture 25
Traffic Light Sequencing
Clock
4-bit
Counter
0 1 0 0 (4)
Reset
T0 T1 T2 T3
Combinatorial
Logic
T2
T3T0
T1
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CBP 2002 ITY 270 Computer Architecture 26
Fetch Execute SequencingT1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU OpMem Access
Reg Write
ALU31
+
--
+
--ALU
Counter
Decoder
Clock
Data Memory
Code Memory AL
U
X
Y
W
X Y
W
0
1
7
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CBP 2002 ITY 270 Computer Architecture 27
Representing Numbers
000
110
001
100
010
011101
111
5
17
26
4
0
3
000
110
001
100
010
011101
111
-3
1-1
2-2
-4
0
3
Let’s take some 3-bit numbers.
“2’s Complement” – complement it (0->1 and 1->0) then add 1
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CBP 2002 ITY 270 Computer Architecture 28
2’s Complement Properties
000
110
001
100
010
011101
111
-3
1-1
2-2
- 4
0
3
Most Significant Bit (MSB) gives sign.Addition ?
0 0 1 1 1 1 0 0 0
0 1 1 1 1 0 0 0 1
1 -1 0
3 -2 1
3 - 2 = 3 + (-2) = 1
Subtraction by Addition
0 0 1 0 1 0 0 1 1
1 2 3
1 1 1 1 1 0 1 0 1
-1 -2 -3
MSB is Sign Bit !
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CBP 2002 ITY 270 Computer Architecture 29
Full AdderFull AdderFull AdderFull Adder
a3 a2 a1 a0
b3 b2 b1 b0
s3 s3 s3 s3
1
Subtraction by Addition
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CBP 2002 ITY 270 Computer Architecture 30
HEX and Chars
Hexadecimal Shorthand each nibble rep’d as a character …1 0 1 1 0 1 1 1
B 7
Binary Hex
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 A
1 0 1 1 B
1 1 0 0 C
1 1 0 1 D
1 1 1 0 E
1 1 1 1 F
Useful in Machine Level Programming and HTML scripting
HEXAscii
30 0
41 A
61 a
6D m
0D CR
ASCII
UNICODE
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CBP 2002 ITY 270 Computer Architecture 31
Multiplication
1 3 1 2 2 61 3 01 5 6
1 1 2 1 1 12 2 02 3 1
1 1 0 1
1 0 1 1
1 1 0 1
1 1 0 1
0 0 0 0
1 1 0 1
1 0 0 0 1 1 1 1
xx x
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CBP 2002 ITY 270 Computer Architecture 32
Multiplication
B
1 1 0 1
C - - - - - - - -
0 0 0 0 0 1 0 1 1 Initial values
0 1 1 0 1 1 0 1 1 Add A to B
0 0 1 1 0 1 1 0 1 SHR
1 0 0 1 1 1 1 0 1 Add A to B
0 1 0 0 1 1 1 1 0 SHR
No Add
0 0 1
0 0 1 1 1 1 SHR
1 0 0 0 1 1 1 1 1 Add A to B
0 1
0 0 0 1 1 1 1
A
1 1 0 1
0 0 0 0 1 0 1 1C
Add/no-add
A
adder
B
Add A to B. Then Shift Right (SHR). Look at LSB bit. If this is 1 then Add A to B.
A = B = AxB =