CBC2: CMS microstrip readout for HL-LHC

CBC2: CMS microstrip readout for HL-LHC

[D. Braga], G. Hall , M. Pesaresi, M. Raymond (Imperial College) D. Braga, L. Jones, P. Murray, M. Prydderch (RAL)

D. Abbaneo, G. Blanchot, A. Honma, M. Kovacs, F. Vasey (CERN)

HSDT9 Sep 2013 2

Background

• CMS upgrade under consideration for many years– objective to reach 3000 fb-1 in next decade or so– High Luminosity LHC (Phase II) requires new Tracker around 2023– Requirements:

• lower material budget• increased granularity• enhanced radiation tolerance• tolerable power consumption• affordable cost• all compatible with physics objectives –some of which remain

uncertain– e.g. will new physics be discovered in next running period?– but solid long term programme of Higgs & top studies, searches, etc…

Geoff Hall

HSDT9 Sep 2013 3

Evolution of objectives

• Original goal– new – improved - tracker with similar angular coverage, constrained by

re-using existing services– provide some part of tracker data to L1 trigger to contain rate to 100 kHz

• More recent developments– Baseline Tracker design now adopted

• “conventional” barrel-endcap layout looks optimal– but CMS exploring enhancing forward region physics as well as standard

physics programme– uncertainty if L1-track triggering will reduce rate to 100 kHz in 6.4µs

• ideas (and detector requirements) not yet validated by simulations• possible objective of L1 readout up to 1 MHz/10-20µs• both approaches require on-detector data reduction

Geoff Hall

HSDT9 Sep 2013 4

Baseline tracker layout (pixels not shown)

• Double layer readout compatible with trigger• Geometry compatible with forward extension

Geoff Hall

2S short strip double-layers(~7500 modules)

PS strip-strixel double-layers (~10,000 modules)

HSDT9 Sep 2013 5

ASIC development

• Earliest developments foresaw conventional outer tracker, plus some dedicated trigger (and pixel) layers– 128 channel CMS Binary Chip (CBC) produced and proven 2011– Readout architecture followed original tracker, using APV25– Analogue data abandoned for practical reasons

• digital optical link components now standard, ADC power, 130 nm CMS harder to implement analogue cells

• Subsequently, outer modules with trigger capability– 254 CBC2 successfully developed – delivered 2012 – optimised for new assembly method with mass production in mind

Geoff Hall

HSDT9 Sep 2013 6

Present CMS Tracker architecture

• Analogue unsparsified readout– APV25 in 0.25µm commercial CMOS– synchronous – occupancy independent data volume– 2.7mW/chan for 10-20cm µstrips

– analogue data transmission to external ADC & zero-suppression, clusters

• semi-custom optical links @ 40Msps• 1310 nm single-mode Fabry-Perot lasers• very successful• reflected state of technology at the time

– benefits• simple and easy to debug/evaluate• robust against noise

Geoff Hall

pipeline

128x192

128

x pr

eam

p/sh

aper

APSP

+ 1

28:1

MU

X

pipe logicbias gen. controllogic

7.1

mm

8.1 mm

Analogue Optical Hybrid

HSDT9 Sep 2013 7

Basic trigger module concept

• Compare binary pattern of hit pixels on upper and lower sensors

Geoff Hall

High pT tracks can be identified if hits lie within a search window in R-f (rows) in second layer

~200μm

Upper Sensor

Lower Sensor

Pass Fail

~100μm

1-2 mm

R

f~mm-cm

f (rows)

z (columns)

Sensor separation and search window determines pT cutz-segmentation determines vertex capability

HSDT9 Sep 2013 8

2S PT-module with CBC2

• Track & trigger µstrip module for outer tracker region– CBC2 logic correlates hits on two sensors to reject those from low pT tracks

Geoff Hall 8

8 x 254 channel chipsbump-bonded to hybrid

8 x 254 channel chipsbump-bonded to hybrid

chips on top surface onlysignals from lower sensor

via’d through substrate

~5 cm

90 µm pitch strips

sensors wire-bondedabove and below

~5 cm

concentrator&

controller

two layers of sensorslow mass, high density interconnect layer

HSDT9 Sep 2013 9

CBC main features

– IBM 130nm CMOS process

– binary, unsparsified architecture• retains chip and system simplicity• but no pulse height data

– designed for ~2.5 - 5cm µstrips < ~ 10 pF

– 128 channels, 50 mm pitch wire-bond• either polarity input signal

– not contributing to L1 trigger

– powering test features: • 2.5 -> 1.2 DC-DC converter• LDO regulator (1.2 -> 1.1) feeds analogue FE

– fast (SLVS) and slow (I2C) control interfaces

Geoff Hallam

plifi

ers &

com

para

tors

256 deep pipeline +32 buffers

128

chan

nel i

nput

2.5->1.25DC-DC converter

bias generator linear

drop out regulator

7 m

m

4 mm

HSDT9 Sep 2013 10

CBC measured performance

Geoff Hall

115k

80f1p

VPLUS

Vdda

16k

200k

100f

60k 92k

VCTH 2k

4k

8k

16k

500k

preamp

postamp

comparator

– analogue• 130 + (21 x C [pF]) µW/chan

– digital• < 50 µW/chan

– total• 180 + (21 x C[pF]) µW/chan e.g. < 300 µW /channel for C = 5 pF

1200

1000

800

600

400

200

0

nois

e [rm

s el

ectro

ns]

121086420

external capacitance [pF]

400

350

300

250

200

150

100

power per channel [uW

]

holes mode

noisepower

simulation: open circles

1200

1000

800

600

400

200

0

nois

e [rm

s el

ectro

ns]

121086420

external capacitance [pF]

400

350

300

250

200

150

100

power per channel [uW

]

electrons mode

noisepower

simulation: open circles

HSDT9 Sep 2013 11

CBC comparator

Geoff Hall

• thresholds adjusted satisfactorily

• timewalk within spec

720700680660640

720700680660640

even

ts a

bove

thre

shol

dcomparator global threshold [mV]

128 channelsbefore tuning

after

threshold uniformity

VCTH

timew

alk

[ 1ns

ec /

divi

sion

]

109876543210

charge injected [fC]

added capacitance 1.8 pF 3.8 pF 5.8 pF 8.1 pF 10.7 pF

timewalk: threshold at 1 fC

VDDA

postamp O/PO/S adjust8-bit value

(per channel)

16k VCTH

hysteresis

2k

4k

8k

16k

16k

500k

postampO/P

comparator

HSDT9 Sep 2013 12

Beam telescope• Based on CMS Tracker DAQ readout hardware, software (used for UA9 studies)

• FED, APV25s, 100m fibres, custom control system, multi-core PCs• 50 kHz data taking during 10s spill, 10 kHz to disk,

Geoff Hall

Goniom

eter

p+ beam

upstream downstream

XY

Plane 1

XY

Plane 2

XY

Plane 3

UV

Plane 4

XY

Plane 5

Crystal

Granite Table

10,289mm

295mm

416mm

214mm

9,960mm

Trigger Scintillators

spatial resolution: 6.8-7.0 µm

angular resolution: 5.2 µrad

HSDT9 Sep 2013 13

APV plane

CBC sensor

5 mV / division

beam profileCBC beam tests 2011

• CERN H8 beam line– 400 GeV/c protons

Geoff Hall

5 cm

p-on-n150 mm pitch320 µm thick

64 strips bonded to 5 cm p-on-n sensorno pitch adaptor150 µm pitch 320 µm thickness fan shaped

160x103

140

120

100

80

60

40

20

0nu

mbe

r of r

aw d

ata

even

ts

900850800750700650600

comparator threshold [mV]

raw data landau dist. (arb. scale) fit to raw data using landau

HSDT9 Sep 2013 14

CBC performance in beam

• Successful operation• Digital logic works well

– no pipeline errors– no CBC errors in > 30M events

Geoff Hall

use telescope to select events at CBC module- single track events only (pileup eliminated)- incident on CBC sensor (transverse to strips)- incident in 3mm along strips (const p=134um)- events within 7ns of sampling clock

measure resolution of CBC module from residual- using telescope for track extrapolation- factoring out telescope spatial resolution

resolution: 29.4 um

better than pitch/√12 due to contribution from 2 strip clusters

close to binary resolution from 1 strip clusters

HSDT9 Sep 2013 15

CBC -> CBC2: New features

• 250µm pitch C4 layout• aim for commercially assembled module• some gains in bond inductance• back edge wire-bond pads for wafer probe

• 254 channels for 127 + 127 strips• correlation logic for stub formation

• between top & bottom strips• vetoes wide clusters

• Test pulse• no time to implement on CBC• & other minor circuit improvements

• Improved DC-DC (CERN)• received Jan 2013 – fully functional

DC-D

C

LDO

pipeline+

buffering

254

ampl

ifier

/com

para

tor c

hann

els

CWD,

offs

et co

rrec

tion

and

colle

ralti

on lo

gic

band

gap

bias

gen

.

254inputs

5 mm

11mm

inter-chip

signals

inter-chip

signalsGeoff Hall

16

notch

wafer name:A4PNFAH

CBC2

reticle

CBC2 C4 wafers (shared with RAL XFEL ASIC)

Geoff Hall HSDT9 Sep 2013

Offset+

correlation

DFront End Ch. Mask CWDB

Front End Ch. Mask CWDA C

254

253

127

Front End Ch. Mask CWDB

Front End Ch. Mask CWD

252

251


Front End Ch. Mask CWDB’

250

249

2

A

B

A


Front End Ch. Mask CWDB’

2

1

B

A

22

22

22

22

22

2

2

22

2

Offset+

correlation

D

C

126

Offset+

correlation

D

C

125

Offset+

correlation

D

C

1

11

11

11

11

11

11

11

11

127

254

To pipeline RAM

4 4

fast

OR

11 11

4 4 11 11

EN

MUX toSR

Stub finding Logic

Stub

s shi

ft re

gist

er

latch

@40MHz

Individual mask for noisy channels→254b from I2C reg.(can be also used to inhibit coincidence logic)

Need to be able to inhibit stub shift register operation→1b EN from I2C reg.

254-OR of channel outputs to signal any activity on chip

127-OR of stubs to control the stubs SR readout

HSDT9 Sep 2013 18

Stub logic features

• Cluster width– exclude clusters wider than 3 strips

• Offset correction and correlation– programmable window, selects pT

• up to +/-8 channels– programmable offset, adjust lateral displacement

• up to +/-3 channels

Geoff Hall

n

n+1

n-1

1/2/3 stripcluster onchannel n

channelcomparator

outputs

p = ∞

IP

R-f view

offset

19

first wafer probed manually

selection of chips for module assembly


20

CBC2

bad chip112 reticles108 good chips4 bad chips

reticle

final yield for 1st wafer

bad chips duesolely to physicaldamage fromprobecard

supply current - all chips

no defective channel found on any of112 chips tested on this first wafer

=> 100% yield

perhaps not too surprising if overall wafer yield highCBC2 is relatively small area of reticle& significant fraction of CBC2 area notoccupied by active circuitry


HSDT9 Sep 2013 21

2S module

• Development with CMS team• Substrate development mainly by CERN

– Hybrid procured and assembled commercially• First version: 2 chip hybrid

– electrical validation

Geoff Hall

mount capacitors here to simulate interstrip capacitance

small pitch adapter board(wire-bond pitch to 1.27mm connector)

calibratedcharge injection(both sensor layers)

HSDT9 Sep 2013 22

Result with test pulse

– Proves basic functionality but need real data for better test

Geoff Hall

1234567891011121314151617181920212223

11

22

33

44

55

66

77

88

99

1010

1111

12

channelon chip

channelon layer 1

channelon layer 2

8 testgroups

HSDT9 Sep 2013 23

2S mini-module

• Prototype assembled with two sensors– Now under test in lab

Geoff Hall

beta source

data frame width

scope in persistence modeSr-90 sourcescintillator signal

CBC2 trigger output

hits in thedata stream

24Geoff Hall HSDT9 Sep 2013

CBC2 triggered data output

CBC2 trigger output

scintillator/PM signal

hits in the data stream


CBC2 triggered data output

2 consecutive hits=> track passed throughstrips directly aboveeach other

50 ns


single strip clustersoffset by 1 strip

75 nsec


single strip clustersoffset by 3 strips

175 nsec


single strip clustersoffset by 4 strips

225 nsec


2 strip cluster in one planecorrelates with 1 strip clusterin the other


2 strip cluster in lower sensorcorrelates with 1 strip clusterin the other, offset by 7 strip

375 nsec


127

33

CBC3 - the “final prototype”

bottom

top

8 bits to describe clusteraddress in bottom layer

5 bits to describe correlating clusteraddress in top layer window

1 or 3 stripcluster centredon channel n

2 strip clustercentred onn and n+1

n

n+1

n-1

next version of chip should incorporate all features required for HL-LHC

• final choices for front end½ strip cluster resolution

2 strip cluster position assigned to mid-point

• stub data definition8 bits address (for ½ strip resolution) of cluster in bottom layer5 bit bend information

address of correlating cluster in top layer

• stub data formatting & transmission to concentrator13 bit / stub, up to 3 stubs/BX => 39 bits+1 bit unsparsified L1 triggered readout data=> 40 bits / 25 nsec

e.g. 10 lines at 160 Mbps (per chip)

• other useful featurese.g. slow ADC to monitor bias levels…

concentrator

CBCCBC

CBCCBC

CBCCBC

CBCCBC

10 lines / CBC25 ns

S1 S1 S1 S1 S1 S1 S1 S1 B1 B1B1 B1 B1S2 S2 S2 S2 S2 S2 S2S2 B2 B2 B2 B2 B2S3 S3 S3 S3S3 S3 S3 S3 B3 B3 B3 B3 B3 R

25 ns

CBC data to concentrator


HSDT9 Sep 2013 34

Rough road map

Geoff Hall

CBC1

- analogue front end in 130nm- wirebonded- binary logic- L1 triggered readout only, non-sparsified

CBC2

- C4 bump-bonded- full hit correlation logic- L1 triggered non-sparsified

readout, fast trigger OR

CBC3

- full readout architecture defined

- additional correlation logic

CBC4

- optimisation- final version

2011

2012

2014

2016

2S-Pt prototype module studies

2S-Pt final module studies

start production2017

2015

2013

HSDT9 Sep 2013 35

Summary & conclusions

• Two successful iterations of new outer Tracker ASIC

• First prototype version of 2S module in hand– functions well in lab environment– first beam tests foreseen late 2013

• Road map for future developments– detailed schedule depends on complete upgrade plan and HL-LHC

approval process

Geoff Hall

Backup slides

37

CBC power featuresDC-DC switched capacitor converter(CERN)

converts 2.5 -> ~ 1.2works well: ~ 90% efficiency

but switch noise produces differencebetween internal and external grounds

=> interference depending on CEXT

improved circuit on CBC2, and bump-bondingshould help

1.111.101.091.081.071.061.051.04

LDO

out

put [

V]

1.201.151.101.05

LDO input voltage [V]

30mA load 60mA load

LDO dropout 40 mVGNDEXT

GNDINT

CEXT

Cf

vnoise

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Vol

ts

353025201510502.52 Volt supply current [mA]

DC-DC Vout vs. load

LDO linear regulator

provides clean, regulated rail to analog FE(uses CERN 130 nm bandgap)

~ 1.2 Vin, 1.1 Vout

dropout ~ 40 mV for 60 mA load

provides > 30dB supply rejection up to 10 MHzGeoff Hall HSDT9 Sep 2013

WIT 2012Mark Pesaresi (IC-CMS) CBC Readout Chip for LHC Phase II

digital logic

38

no correlation/trigger logic in this iteration- triggered readout only (~270kHz max sustained)

hit detect logic in two modes – single/variable

output from each channel stored in a 256 sample deep pipeline RAM (6.4us latency max)

32 trigger FIFO buffer

unsparsified readout (140-to-1 shift register)

40MHz clock

hit detect -variable mode

hit detect -single mode

comparator output

WIT 2012Mark Pesaresi (IC-CMS) CBC Readout Chip for LHC Phase II

CBC performance in beam

39

cluster width, resolution and efficiency will be affected by threshold setting

- expecting to operate at 1fC level (~640mV)- important to get rough estimations for tuning

stub/tracklet simulations- study of noise occupancy with threshold required

efficiency drop due to charge sharing

2 strip clusters originate from interstrip region

CBC2 architecture

pipe. control

FE amp comp. pipeline shift reg.

vth

vth

vth

vth

256 deeppipeline

+32 deepbuffer

testpulse

biasgen.

fastcontrol

slow control

stub

shi

ft re

gist

er

offs

et c

orre

ctio

n &

cor

rela

tion

clus

ter w

idth

di

scrim

inat

ion

1

254 40 MHz diff.clock

all signals in blue are single-ended -only travel shortdistance on hybrid

trig’d data outstub shift reg. O/Ptrigger O/PI2C

front end, pipeline, L1 triggered readout, biasing~ same as prototype (some bug fixes) twice as many channelsnew blocks associated with Pt stub generationchannel mask: block problem channels (not from L1 pipeline)cluster width discrimination: exclude wide clusters > 3offset correction and correlation: correct for phi offset across module and correlate between layersstub shift register: test feature - shift out result of correlation operation at 40 MHztrigger O/P: in normal operation 1 bit per BX indicates presence of high Pt stubtest pulsecharge injection to all channels (8 groups of ~32), programmable timing and amplitude

nearest neighbour signals

T1 triggerfast resettest pulseI2C refresh

4 4 11 11

chan

. m

ask

4 4 11 11

nearest neighbour signals

reset

OR_254

OR_stubs

Ck

From F.Vasey: Electronic System for 2S-Pt modules System Architecture and Data Formats, CMS Tk Week

@160MHz

(@160MHz)

HSDT9 Sep 2013 43

Comparison logic

Geoff Hall

• Modules are flat, not arcs• Compensate for Lorentz drift• Orientation of module => position dependent logicd

Luminous region (large!)

R-z view

• z offset h dependent• search window to allow for luminous region and quantization => 3 pixels (if not tiny)

p = ∞

IP

R-f view

~200µm ~12mmh = 2.5

• Family of modules with offsets in z

CBC2: CMS microstrip readout for HL-LHC

Documents

Transcript of CBC2: CMS microstrip readout for HL-LHC