Case Studies Using SST- MacSim
description
Transcript of Case Studies Using SST- MacSim
Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for
the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.
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Case Studies Using SST-MacSimGenie Hsieh
Sandia National Labs
SST + MacSim
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SST-MacSim DEMO
MacSim and DRAMSim2 integration
Parallel execution of multiple MacSim
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SST-MacSim: Two Modes Standalone
./configure <options>
make; make install
With DRAMSim2 Build DRAMSim2 library: make libdramsim.so ./configure <options> --with-dramsim=DIR
make; make install
./configure --prefix=/home/myhsieh/local/sst --with-McPAT=/home/myhsieh/local --with-hotspot=/home/myhsieh/local --with-m5=/home/myhsieh/m5-x86/
./configure --prefix=/home/myhsieh/local/sst --with-McPAT=/home/myhsieh/local --with-hotspot=/home/myhsieh/local --with-m5=/home/myhsieh/m5-x86/--with-dramsim=/home/mhsieh/DRAMSim2
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MacSim + DRAMSim2 Example<component name=gpu0 type=macsimComponent>
<params><paramPath>params_hetero_1_6</paramPath><tracePath>trace_file_list</tracePath><outputPath>results</outputPath><clock>1.4Ghz</clock>
</params><link name=membus port=bus latency=1ns />
</component>
<component name=mem0 type=DRAMSimC> <params>
<clock> 1.5 Ghz </clock> <megsOfMemory> 1024 </megsOfMemory> <systemini> system_GDDR5.ini </systemini> <deviceini> ini/GDDR5_hynix_1Gb_16B.ini </deviceini></params> <link name=membus port=bus latency=1ns /> </component>
SST-MacSim
DRAMSim2DDR2, DDR3
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DEMO
MacSim DRAMSim2SST Link
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DRAMSim2 Simulation Output[myhsieh@s910654 bin]$ ./sst.x --sdl-file=test_dram.xml
SST: construct macsimComponent and setSSTComponent with ID 0SST: construct DRAMSimC with ID 1…src/macsim.cc:588: (I=0 C=439930): elapsed time:7.4 secondsDoneDRAM: Background Energy 17202960DRAM: Burst Energy 9973920DRAM: ACT/PRE Energy 21178560DRAM: Refresh Energy 1472320
Bus packetTransactionTransaction queue 1]T [Read] [0x45bbfa4] 2]T [Write] [0x55fbfa0] [5439E]Memory statisticsPower
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MacSim Memory Experiments
<component name=mem0 type=DRAMSimC> <params>
<systemini> system_DDR3.ini </systemini> <deviceini> ini/GDDR3.ini </deviceini> </params></component>
<component name=mem0 type=DRAMSimC> <params>
<systemini> system_GDDR5.ini </systemini> <deviceini> ini/GDDR5.ini </deviceini> </params></component>
MacSim + DDR3
MacSim + GDDR5**Core 1 Core_Total Finished: insts:205888 cycles:428507 seconds:8 -- 0.48 IPC (0.48 IPC) (I=0 C=428508): finalize simulation
DRAM: Background Energy 1431920DRAM: Burst Energy 40460DRAM: ACT/PRE Energy 113280
**Core 1 Core_Total Finished: insts:205888 cycles:439929 seconds:7 -- 0.47 IPC (0.47 IPC) (I=0 C=439930): finalize simulation
DRAM: Background Energy 17202960DRAM: Burst Energy 9973920DRAM: ACT/PRE Energy 21178560
Output
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Parallel Execution of MacSim in SST
MacSim SST-MacSim
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Parallel execution of MacSim through SST Bus
MacSim
Bus
SST Link
DRAMSim2SST Link
MacSim SST Link
MacSim SST Link
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Parallel Execution of Multiple MacSim<component name=cpu0
type=macsimComponent> <params> <paramPath>params_x86</paramPath>
<tracePath>trace_file_list_cpu</tracePath>
<clock>4Ghz</clock> </params> <link name=cpu port=bus latency=1ns /> </component>
<component name=gpu0 type=macsimComponent>
<params><paramPath>params_gtx8800_v2</
paramPath> <tracePath>trace_file_list_gpu</tracePath> <clock>1.4Ghz</clock>
</params> <link name=gpu port=bus latency=1ns /></component>
<component name=mem0 type=DRAMSimC> <params> <systemini> system_GDDR5.ini </systemini> <deviceini> ini/GDDR5_.ini </deviceini> </params> <link name=mem port=bus latency=1ns /> </component>
<component name=bus0 type=bus><params> <clock>1GHz</clock>
<deviceList> cpu gpu mem</deviceList></params> <link name=cpu port=cpu latency=1ns /><link name=gpu port=gpu latency=1ns /><link name=mem port=mem latency=1ns />
</component>
SST-MacSim CPU
SST-MacSim GPU
SST-Bus
SST-DRAMSim2
CPU GPU
Memory
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DEMO
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Parallel Execution of Multiple MacSim
<comonent name=cpu0type=macsimComponentrank =0></component>
<comonent name=cpu1type=macsimComponentrank =1></component>
<comonent name=gpu0type=macsimComponentrank =2></component>
<comonent name=gpu1type=macsimComponentrank =3></component>
<com
pone
nt n
ame=
bus
type
=bus
rank
=4>
</co
mpo
nent
>
<com
pone
nt n
ame=
dram
type
=DR
AM
Sim
Cra
nk=5
></
com
pone
nt>
mpirun –np6 ./sst.x –sdl-file=macsim.xml
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Memory Experiments
DRAM: Background Energy 338800DRAM: Burst Energy 2380DRAM: ACT/PRE Energy 7080
## Simulation times# Build time: 0.00 s# Simulation time: 124.04 s# Total time: 124.04 s
DRAM: Background Energy 2569720DRAM: Burst Energy 26180DRAM: ACT/PRE Energy 77880
## Simulation times# Build time: 0.00 s# Simulation time: 174.06 s# Total time: 174.06 s
1CPU 1GPU DDR3 2CPUs 2GPUs DDR3
Parallel execution of MacSim through SST Iris Network
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Standalone MacSim
Core
Cache
Iris NIC
Iris Router
DRAM
SST/MacSim TerminalDecoupled MacSim
Core
Cache
Iris NIC Iris Router
DRAM
SST/Iris NIC SST/Iris Router
SST/MacSim DRAM
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MacSim NIC
DRAMMacSim
SST Link
MacSim
NIC
NIC
NIC
R R
R R
2X2 Mesh
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Configure SST/MacSim
<component name=cpu type=macsimComponent>
<params> <paramPath>x86</paramPath><terminalType>0</terminalType>
<id>0</id> <mc_id>1</mc_id> <term_mclass>0</term_mclass> </params> <link name=cpu2nic port=nic /> </component>
<component name=mc type=macsimComponent> <params>
<paramPath>x86</paramPath>
<terminalType>2</terminalType> <id>3</id> <mc_id>3</mc_id> <term_mclass>1</term_mclass> </params> <link name=mc2nic port=nic /></component>
SST/MacSim Terminal SST/MacSim DRAM
terminalType: 0(core), 1(cache), 2(MC/DRAM) term_mclass: 0 (request from core), 1(response from DRAM)
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Parallel Execution of Multiple MacSim<component name=cpu0 type=macsimComponent> <params> <paramPath>params_x86</paramPath>
<terminalType>0</terminalType> <id>0</id> <mc_id>1</mc_id> </params> <link name=cpu2nic port=nic latency=1ns /> </component>
<component name=mc type=macsimComponent> <params>
<paramPath>params_gtx8800_v2</paramPath> <terminalType>2</terminalType>
<id>1</id> <mc_id>1</mc_id> </params> <link name=mc2nic port=nic latency=1ns /></component>
<component name=0.rtr type=iris.router> <params> <id>0</id> </params> <link name=0.nic2rtr port=bus latency=1ns /> <link name=xr2r.0.0.1 port=xPos /> <link name=xr2r.0.0.0 port=xNeg/> </component>
<component name=0.nic type=iris.ninterface><params> <id>0</id></params> <link name=cpu2nic port=cpu
latency=1ns /><link name=0.nic2rtr port=router
latency=1ns /></component>
SST-MacSim Terminal
SST-MacSim DRAM
SST-Iris NIC
SST-Iris Router
cpu2nic MC2nic<component name=1.nic type=iris.ninterface>
<params> <id>1</id></params> <link name=mc2nic port=cpu latency=1ns
/><link name=1.nic2rtr port=router
latency=1ns /></component>
<component name=1.rtr type=iris.router> <params> <id>1</id> </params> <link name=1.nic2rtr port=bus latency=1ns /> <link name=xr2r.0.0.0 port=xPos /> <link name=xr2r.0.0.1 port=xNeg/> </component>
SST-Iris Router
SST-Iris NIC
nic2rtrnic2rtr
rtr2rtr
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DEMO