IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 2, FEBRUARY 2012 367

Carrier Lifetime Engineering for Floating-BodyCell Memory

Sungho Kim, Sung-Jin Choi, Dong-Il Moon, and Yang-Kyu Choi

Abstract—A novel bias scheme is demonstrated for performanceimprovement of floating-body cell memory, particularly retentiontime. Its basic mechanism is based on carrier lifetime engineering,which takes advantage of generation lifetime that is longer thanrecombination lifetime. In addition, the proposed scheme is suit-able for low-power operation; a high drain bias is unnecessary togenerate excess carriers, which allows reliable endurance of up to1012 switching instances at 85 ◦C.

Index Terms—Carrier lifetime, double gate, finFET, floating-body cell (FBC), silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET), 1T-DRAM.

I. INTRODUCTION

R ECENTLY, embedded memory has gained additional at-tention in efforts for the realization of the system-on-

chip (SoC) system. The need for high-speed and high-densitymemory has become essential, but conventional DRAM islikely unsuitable for embedded memory due to the difficultyrelated to capacitor miniaturization. Alternative memory cellshave been proposed to solve this problem. The floating-bodycell (FBC, which is also known as 1T-DRAM or capacitor-lessDRAM) is considered as a promising candidate.

The memory operation of previous FBCs is based on thethreshold voltage shift caused by excess majority carriers thataccumulate in the floating-body. Fig. 1 shows a summary ofthe operation principles of previous FBCs. First-generationFBCs (Gen 1) utilize impact ionization [1] or gate-induceddrain leakage [2] to generate excess majority carriers in thefloating-body. However, one limitation associated with thesedevices is their insufficient retention time, which is roughlyon the order of 100 ms, even in state-of-the art devices [3].The second generation of FBCs (Gen 2) employed a positive

Manuscript received August 24, 2011; revised October 6, 2011 andNovember 11, 2011; accepted November 14, 2011. Date of publicationDecember 19, 2011; date of current version January 25, 2012. This work wassupported in part by the Center for Nanoscale Mechatronics and Manufacturing,one of the 21st Century Frontier Research Programs supported by the KoreanMinistry of Education, Science and Technology, under Grant 08K1401-00210;by the Ministry of Knowledge Economy/Korea Evaluation Institute of Indus-trial Technology under Grant 10035320: “The Development of Novel 3-DStacked Devices and Core Materials for Next-Generation Flash Memory;”and by Samsung Electronics Co., Ltd. The review of this paper was arrangedby Editor Y.-H. Shih.

The authors are with the Department of Electrical Engineering, KoreaAdvanced Institute of Science and Technology, Daejeon 305-701, Korea(e-mail: ykchoi@ee.kaist.ac.kr).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2011.2176944

Fig. 1. Comparison of FBC memory operations. As compared with theexisting Gen 1 and Gen 2 schemes, the proposed scheme has the benefit oflonger retention time than Gen 1 and lower operation bias than Gen 2.

feedback effect stemming from a parasitic bipolar transistor(known as a single transistor latch) to create excess carriers andimprove their longevity. Hence, it could prolong the retentiontime, which was approximately on the order of 1 s [4]. However,a high drain bias is indispensible to sustain a positive feedbackeffect, which adversely leads to severe device degradation andbrings about reliability concerns [5].

In this paper, a novel bias scheme is proposed to achievelonger retention time in FBCs without the use for high drainbias. The key idea of the proposed scheme is based on carrierlifetime engineering. In the previous Gen 1 and Gen 2 schemes,excess majority carriers are generated. Hence, retention timeis determined by how fast these carriers are recombined. Inthe proposed scheme, on the other hand, majority carriers areintentionally depleted, thus creating temporary charge imbal-ance, i.e., a nonsteady state. A steady state then arises with therecovery of the charge imbalance through the carrier generationprocess at the bulk region of the floating-body. Thus, the reten-tion time is governed by the generation rate of majority carriersduring the recovery process. Because the generation rate ismuch slower than the recombination rate, the retention timecan be improved without a high drain bias to generate excesscarriers. In Section II, the basic principles of the proposed

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368 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 2, FEBRUARY 2012

Fig. 2. Principles of the proposed carrier lifetime engineering scheme and its schematics. In the proposed scheme, holes are depleted intentionally, and theretention time is governed by the generation rate of holes. Generally, the hole generation rate is slower than the recombination rate, which allows for theimprovement of the retention characteristics without high operation bias needed to generate excess holes.

scheme are discussed in detail with the aid of numerical devicesimulation data. Next, in Section III, the measurement resultsare discussed and compared with those of Gen 1 and Gen 2regarding the retention time, sensing margin, and endurance.

II. BASIC PRINCIPLES OF CARRIER LIFETIME

ENGINEERING

A. Bias Scheme

For convenience, all explanations in this paper refer to ann-channel transistor. In the case of a p-channel transistor, thepolarity of the bias and the carriers are reversed. In the previousGen 1 and Gen 2 schemes, excess holes are generated, andthe retention time is then determined by how fast the holes arerecombined in the floating-body. In other words, the retentiontime of FBCs is determined by the recombination rate of theholes (which is inversely proportional to the recombinationlifetime (τr)). However, it is known that the generation rate(∼1/τg : τg is the generation lifetime) is slower than therecombination rate (∼1/τr), at typically τg ≈ (50 ∼ 100)τr

in Si devices [6]. Therefore, if the retention time of FBCs isgoverned not by the recombination rate but by the generationrate, the retention time can be improved by 50 ∼ 100 timeseasily, which is the key idea of the proposed concept of carrierlifetime engineering.

To realize carrier lifetime engineering, an individually op-erated double-gate structure is necessary. Fig. 2 shows theschematics of the proposed bias scheme. The proposed schemecan be adapted into a nominal floating-body FET composed offour terminals, i.e., a front gate (G1), a back gate (G2), a source(S), and a drain (D). The data writing and holding operationare carried out as described here.

1) Initial (Hold “1”): The back gate (VG2) is sustained witha constant positive voltage to induce an inversion layer at

the back interface. A small drain bias (VD) monitors theresulting drain current (ID) during a reading operation,and the front gate (VG1) is biased with negative voltageto accumulate holes at the front interface. Here, theinverted electron density (Nelec) at the back interface isdynamically coupled with the accumulated hole density(Nhole) at the front interface.

2) Write “0”: When a positive voltage larger than the thresh-old voltage is applied to the front gate, the holes aredepleted suddenly as a result of the momentary inver-sion channel that forms at the front interface. Thereafter,additional holes are necessary to maintain the chargebalance inside the floating-body. However, such holescannot be supplied promptly from the bulk region ofthe floating-body due to the absence of a body contact;thus, the system enters a nonsteady state. For this reason,immediately after the positive voltage is applied to thefront gate, the demand for holes is temporarily counter-vailed by the removal of electrons from the back inver-sion channel, resulting in a decrease in the drain current[7]–[10]. This drain current reduction is regarded as aWrite ‘0’ operation in this scheme.

3) Hold “0”: The sudden reduction of holes at the frontinterface changes the electrostatic potential inside thefloating-body. This triggers bulk hole generation (Gbulk),which can be understood in terms of Shockley-Read-Hall theory [11]. As electron–hole pairs are generatedgradually from the floating-body to restore the steadystate, the holes drift toward the front interface whilethe electrons make up for carriers in the back inversionchannel. Subsequently, the temporal drain current reduc-tion recovers to its steady state. Therefore, the retentiontime of data “0” is determined by Gbulk; in other words,the generation rate of holes is a dominant factor of theretention time.

KIM et al.: CARRIER LIFETIME ENGINEERING FOR FBC MEMORY 369

4) Write “1”: The Write “1” operation induces excess holegeneration in the floating-body. When the front gate isswitched to a more negative voltage, the body-drain junc-tion becomes strongly reversely biased. Then, holes aresupplied by band-to-band tunneling. It should be notedthat these excess holes are not intended to be storedinside the floating-body in this proposed scheme; hence,the system remains in a steady state immediately after aWrite “1” operation. Therefore, the retention time of theholding data “1” is infinite.

Here, it should be noted that the coexistence of a front accu-mulation charge and a back inversion charge cannot be accom-modated in an extremely thin FB film (e.g., < 10 nm), whichhas been known as the supercoupling effect [12]. Accordingly,the application of the proposed scheme can be restricted by afloating-body thickness.

B. Simulation

To confirm the validity of the proposed bias scheme,numerical device simulations were carried out (SilvacoAtlas 3-D [13]). Fig. 3(a) shows the dimension of the simulateddevice structure, the bias condition, and the timing condition ofthe applied pulse. When a pulse is applied to the front gate forthe Write “0” operation, as shown in Fig. 3(b), accumulatedholes at the front interface are depleted. Consequently, theelectron density at the back interface (Nelec) is reduced inconjunction with the decrease in the hole density at the frontinterface (Nhole). Due to this coupling effect, the drain currentis decreased suddenly, and the system goes into a nonsteadystate, as shown in Fig. 3(c). This reduction in the drain current(ΔID) serves as a sensing margin to distinguish the data “0”and “1” in a memory operation.

Once the holes are depleted, the bulk hole generation (Gbulk)is enabled near the center of the body to recover the initialsteady state, as shown in Fig. 3(d). Therefore, the retention timeis governed by the value of Gbulk, which is mainly determinedby τg and its relation to the body doping concentration. Fromthese simulation results, it is confirmed that the expected reten-tion time is about 1 s in a scaled device (LG = 100 nm) withouta high drain bias.

III. EXPERIMENTAL RESULTS

A. Device Fabrication

An independent double-gate FinFET was used to demon-strate the proposed bias scheme for FBC memory [Fig. 4(a)].The process flow and the structure are equal to those of apreviously reported design [14]. In brief, as a starting material,a SOI wafer whose channel doping was adjusted by boronwith a concentration of 1018 cm−3 was used. The nominal finheight (Hfin) was 100 nm, and the fin width (Wfin) rangedfrom 30 to 70 nm. A chemical-mechanical polishing processwas utilized to form independently controllable front and backgates. Tetraethyl orthosilicate (TEOS) oxide with a thicknessof 20 nm (toxf and toxb) and n+ in situ doped polycrystalline

Fig. 3. (a) Three-dimensional TCAD simulations of the proof of concept. Thebias condition and the device dimensions in these simulations are equivalentto those of fabricated devices. (b) When the holes that accumulate at thefront interface are suddenly depleted, the inversion electron density at theback interface is consequently reduced according to the dynamic couplingcharacteristics. (c) This leads to a reduction in the drain current, and (d) thistemporal current reduction is recovered via the hole generation process thatoccurs at the center of the body. Two distinctive current states are utilized formemory applications.

silicon (poly-Si) were used as a gate dielectric and a gateelectrode, respectively.

Fig. 4(b) shows the ID–VG1 characteristics of a typicaldevice with variable back-gate voltages (VG2). Independently

370 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 2, FEBRUARY 2012

Fig. 4. (a) Listed device dimensions, process flow, and scanning electronmicrscope and transmission electron microscope images of the independentdouble-gate FinFET used to demonstrate the proposed scheme. (b) Draincurrent versus the G1 bias while the G2 bias is varied from −3 to −2 V at 1-Vincrements. This shows the controllability of each independent gate electrode.

controllable double-gate operation is clearly guaranteed in thisindependent double-gate FinFET; however, it should be notedthat the bias scheme proposed here is also feasible for use witha planar SOI MOSFET structure comprised of a front gate anda controllable back gate underneath the buried oxide.

B. Memory Operations

Fig. 5(a) shows the measured results of an FBC memoryoperation in which the proposed bias scheme is applied. Theback gate is biased at a constant voltage to induce an inversionchannel at the back interface. In the Write “0” operation, todeplete the holes, VG1 and VD are set to 2 and 0.5 V, respec-tively. This bias creates a momentary inversion channel at thefront interface, which depletes the accumulated holes. Duringthe read operation, this hole depletion is monitored through thedrain current, which flows in the back inversion channel. Themeasured sensing margin between State “0” and State “1” is3.2 μA/μm, which is sustainable for more than 500 ms duringthe read operation (implying that the read retention time is500 ms). In addition, when the data are kept under hold bias

Fig. 5. (a) Bias condition and corresponding read current characteristics forthe proposed memory operation. Hole depletion induces the state of “0,”and band-to-band tunneling near the junction supplies holes for the state of“1.” Both the Write “1” and the Write “0” operations can be carried outby a pulsewidth of 10 ns. (b) Bias condition and consequent hold retentioncharacteristics. The sensing margin is sustained for more than 2 s. Here, itshould be noted that a pulsewidth of 100 ms was utilized to measure the holdretention time due to the limit of the measurement system. The hold retentiontime is on the order of a few seconds, so a low data sampling rate of anoscilloscope should be used because the total amount of storable data is fixed.Consequently, if a short pulse (10 ns) is used for the Write “1” or the Write“0” operations, the oscilloscope (Tektronix TDS 540) cannot detect the currentchange due to the low data sampling rate. (Due to the limit of the total amountof storable data, the data sampling rate and the maximum scan range have atradeoff relationship.) Accordingly, although the Write “1” or the Write “0”operations can be carried out within 10 ns in the proposed scheme, there wasno choice but to use a longer pulsewidth (100 ms) for the measurement of thehold retention time. (c) Nondestructive multiple read operations under the holdstate confirm that a binary state can be read repeatedly.

condition (VG1 = −3 V, VD = 0 V), the hold retention timeis more than 2 s without a degradation of the sensing margin,as shown in Fig. 5(b). This is approximately ten times longer

KIM et al.: CARRIER LIFETIME ENGINEERING FOR FBC MEMORY 371

Fig. 6. Bias condition between the proposed dynamic coupling scheme andGen 1 and a comparison of the memory performance in the same device. Theproposed scheme is superior to Gen 1 in terms of the retention time and thesensing margin.

than that of Gen 1 and comparable to that of Gen 2 withoutthe use for a high drain bias. Moreover, the read operation isnondestructive, as shown in Fig. 5(c), which means that multi-ple reads are possible without an additional refresh step. Thisis a distinctive advantage compared to the destructive readingoperation of Gen 1, which requires a refresh step after everyread operation [2], [15].

A direct performance comparison between the proposedscheme and Gen 1 was carried out in the same device, as shownin Fig. 6. Impact ionization was introduced to generate excesscarriers in the Gen 1 scheme, and the equivalent amount ofbias was used for a fair comparison. Despite the fact that ahigher drain bias was used to enable impact ionization in theGen 1 scheme, it is clear in Fig. 6 that the proposed scheme issuperior to the Gen 1 scheme in terms of the retention timeand sensing margin. Therefore, it can be concluded that theproposed bias scheme based on carrier lifetime engineeringconfirms an improved retention time without a high drain biasor a complex device optimization process.

C. Retention Time and Sensing Margin

Fig. 7(a) shows the measured retention times at differenttemperatures. Because the generation rate is governed by theShockley–Read–Hall mechanism, faster carrier generation oc-curs as the temperature increases. The measured results showthat the retention time of 100 ms is guaranteed, even at 85 ◦C.This retention time can be improved further by adapting adifferent channel material or by adjusting the body dopingconcentration. The reported generation lifetimes of other ma-terials are summarized in Fig. 7(b). Because the independentdouble-gate FinFET used in this work is fabricated on an SOI

wafer with a body doping concentration of 1018 cm−3, itsexpected generation lifetime is 10−7 s [16]. From the datashown in Fig. 7(b), it can be concluded that a lower bodydoping concentration or channel material optimization (e.g., thegeneration lifetime of strained Si is 10−4 s [19]) would improvethe retention time by at least 100 times, which is an attractiveadvantage of the proposed carrier lifetime engineering scheme.

In terms of the sensing margin, the Gen 2 scheme is superiorto the proposed scheme. Owing to the current gain from theparasitic bipolar transistor, the sensing margin of the Gen 2scheme is more than 50 μA/μm in general [20]–[22]. However,a high drain bias of more than 3 V is necessary to achievethis high sensing margin, which causes several reliability issues[5]. Unfortunately, the reliability and the endurance issues inthe Gen 2 scheme have not been studied comprehensivelythus far. In the case of the proposed scheme, the use of ahigh drain bias is unnecessary to attain a sufficient sensingmargin. Nevertheless, the sensing margin increases slightly asdrain bias increases because excess carriers are generated aswell by the impact ionization process during the Write “1”operation [Fig. 8(a)]. These excess carriers lead to a widersensing window between State “0” and State “1.” Moreover,this increase in the sensing margin is also observed for the samereason when the gate length of the device is scaled. Fig. 8(b)shows the measured data of the sensing margin increment as thegate length is scaled, which is consistent with the simulationdata. However, the use of a high drain bias in the proposedscheme also causes device degradation, as in the Gen 2 scheme.The endurance characteristic was investigated using differentdrain biases, as shown in Fig. 9, where the currents of bothState “0” and State “1” are plotted as a function of the numberof write cycles. The figure shows that the sensing marginbetween State “0” and State “1” is stable under VD = 2 Vwith up to 1012 of switching at 85 ◦C, whereas the sensingmargin is degraded seriously when VD = 3.5 V. The moreserious device degradation that arises from the hot carriersleads to poor device endurance. Accordingly, although the Gen2 scheme shows a higher sensing margin than the proposedscheme, it is expected that more reliable operation with asufficient sensing margin will result from the use of the schemeproposed here.

IV. CONCLUSION

In summary, a novel FBC biasing scheme based on carrierlifetime engineering has been demonstrated. The actively con-trolled carrier lifetime in the proposed scheme has allowedreliable FBC operation without the need for a high drain biasor a complex device optimization process. The retention timeincreased up to 1 s, whereas the sensing margin and goodendurance have been maintained. The potential of the proposedscheme is immense when other materials are used as thechannel material. Such a strategy may improve the retentiontime 100-fold compared to present results.

Here, it should be noted that the proposed scheme in thiswork looks similar to previous one called as the Meta stableDip (MSD) scheme [23]–[25]. However, memory performancesand operation mechanisms between them are quite different.

372 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 2, FEBRUARY 2012

Fig. 7. (a) Measured hold retention characteristics. Even at 85 ◦C, data can be sustained for more than 100 ms. (b) Reported τg values with various channelmaterials. There is enough room to improve the retention when other channel materials are introduced.

Fig. 8. (a) Sensing margin according to the drain voltage. Although the sensing margin can be enhanced with an increase in the drain voltage, this may result insevere endurance problems. (b) Sensing margin according to the gate length. The sensing margin is increased as the gate length is scaled.

Fig. 9. States “0” and “1” as a function of the number of write cycles. Theamount of drain bias influences the device endurance; the low operation bias ofthe proposed scheme guarantees 1012 write operations at 85 ◦C.

In this paper, a primary purpose is to suggest carrier lifetimeengineering, and a detailed comparison with previous works isremained as a further work.

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Sungho Kim received the B.S. and M.S. degree, in2006 and 2008, respectively, from Korea AdvancedInstitute of Science and Technology, Daejeon, Korea,where he is currently working toward the Ph.D.degree in electrical engineering in the Department ofElectrical Engineering.

His current research interests are trap characteri-zation using the charge-pumping technique.

Sung-Jin Choi received the B.S. degree in elec-tronics and electrical engineering from ChungAngUniversity, Seoul, Korea, in 2007 and the M.S. de-gree, in 2008, from Korea Advanced Institute ofScience and Technology, Daejeon, Korea, where heis currently working toward the Ph.D. degree inelectrical engineering in the Department of ElectricalEngineering.

His current research interests include Schottkybarrier devices, capacitorless dynamic random ac-cess memory, biosensors, and nanowire electronics.

Dong-Il Moon received the B.S. degree fromKyungbook National University, Daegu, Korea, in2008. He is currently working toward the M.S. de-gree in the Department of Electrical Engineering,Korea Advanced Institute of Science and Technol-ogy, Daejeon, Korea.

His current research interests include silicon pho-tonic device and capacitorless 1T-DRAM rangingfrom device design to process development, simula-tion, and characterization.

Yang-Kyu Choi received the B.S. and M.S. degreesfrom Seoul National University, Seoul, Korea, in1989 and 1991, respectively, and the Ph.D. degreefrom the University of California, Berkeley, in 2001.

From January 1991 to July 1997, he was aProcess Integration Engineer with Hynix Semicon-ductor, Inc., Kyungki, Korea, where he developed4M, 16M, 64M, and 256M dynamic random-accessmemory devices. He is currently a Professor withthe in the Department of Electrical Engineering,Korea Advanced Institute of Science and Technol-

ogy, Daejeon, Korea. He has also worked on reliability physics and quantumphenomena for nanoscale complementary MOS. He has authored or coauthoredmore than 130 papers. He is the holder of seven U.S. patents and 100 Koreapatents. His research interests are multiple-gate metal–oxide–semiconductor(MOS) field-effect transistors, exploratory devices, novel and unified memorydevices, nanofabrication technologies for bioelectronics, and nanobiosensors.

Dr. Choi was the recipient of the Sakrison Award for the Best Dissertationfrom the Department of Electrical Engineering and Computer Sciences, Uni-versity of California, in 2002; and The Scientist of the Month for July 2006”from the Ministry of Science and Technology in Korea. His biographic profilewas published in the 57th Marquis Who’s Who in America.