CARLOSv3 0.25 m m Rad-Hard & ALICE SDD DAQ Chain Test

INFN Bologna 2003 - Davide Falchieri 1

CARLOSv3 0.25m Rad-Hard&

ALICE SDD DAQ Chain Test

Samuele Antinori - Davide Falchieri

Alessandro Gabrielli

Enzo Gandolfi – Massimo Masetti


CARLOSv3

GOL DES16

200 mDES

rx-ck

rxdata

CARLOSrx

DDL9+4

½ SDD½ SDD

AP

AP

9+4

tx_en16

32

JTAG

TTCrx

ck (40 MHz)

JTAG

TLK-1501

QPLL

cav, dav

serial back-link

CTPbusy

5

4

7

L0

JTAG5

CARLOSv3 GOL DES

16

200 mDES

rx-ck

rxdata

TLK-1501

9+4

½ SDD½ SDD

AP

AP

9+4

tx_en16

cav, dav

JTAG5

4JTAGserial back-link

QPLL

ck (40 MHz)

pRORC


State of the Art (June 2002 – June 2003)The main topics we have been facing are the following:

Design, realization and test of 2 digital ASICs: CARLOSv3 and LVDS-CMOS

converter rad-hard in 0.25m CMOS technology by CERN EP-MIC (Marchioro)

Test of CARLOSv3 and LVDS-CMOS on a dedicated test board with Tektronix

instruments

Test of CARLOSv3 with optical link (TX + RX from Lab. Elettronica INFN BO)

Design of a DAQ chain from CARLOSv3 to the CERN DDL:

interface board CARLOSv3_rx (VIRTEXII FPGA)

Test of the DAQ chain both in Bologna and at CERN

Even thanks to the portable DAQ chain we have been able to run the data acquisition through DDL at CERN: FOR THE SECOND YEAR THIS WAS THE FIRST ALICE DDL CHAIN TESTED AT CERN


CARLOSv3 pictures

Core

Final Layout

4x4 mm2

2D Compressor for

40 MHz SRAMs (2-Read 1-Write)

100 Pads

Full-Custom RAMs for the

2D-Compressor

CARLOSv3 chip yield 33 out of 35 packaged chips

40MHz Clock


2D Compressor HW Implementation

Up to 256 x 9-bit dual port Rad-Hard SRAMUp to 256 x 9-bit dual port Rad-Hard SRAM

HALF-DETECTOR matrix from AMBRA

Programmable up to 256

Time-Samples

Potential Clusters

Off border data are forced to zero!

5 data at a time are evaluated by taking into account the 2 thresholds of the 2D algorithmIf the requirements are met the central cluster position and its amplitude are packed and transmitted After each event data set received from AMBRA, CARLOS disables AMBRA for 256 clock period for emptying the successive FIFOs


CARLOSv3 with LVDS-CMOS Test Board (Sketch)

CARLOSv3LVDSCMOS

OUTPUT STRIP CONNECTOR

TEST STRIP CONNECTOR

INPUT STRIP CONNECTOR

Right Hybrid

Left Hybrid

DDL

o o o o o o o o o o o o o o o o



o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o




CARLOSv3_rx

TorinoBologna CERN/EP-AID

The board interfaces 2 AMBRAs


CARLOSv3 with LVDS-CMOS Test Board (Photo)

CARLOSv3LVDSCMOS

OUTPUT STRIP CONNECTOR

TEST STRIP CONNECTOR

INPUT STRIP CONNECTOR

Pattern Generator

State Analyzer

CARLOSv3 fully tested on:

JTAG,

Serial Back-Link

Data-Compression

Test Patterns made of: ten 50k-word events

Lvds-Cmos chip yield 15/15 ---- CARLOSv3 chip yield 33/35

50 packaged chips CQFP100

Sockets


Test of CARLOSv3 Optical-Link CARLOSv2_rx (Sketch)

SERIALIZERCARD

DESERIALIZERCARD

CARLOSv3CARD

CARLOSv2_rx

Bologna

GOLTLK 1501

Bologna INFN LAB CERN/EP-MIC CERN/EP-AID

SIMU

2002 CARLOSv2_rxOPTICAL

LINKPattern

Generator

StateAnalyzer

JTAG signals and Back-Link


Test of CARLOSv3 Optical-Link CARLOSv2_rx (Photo)

SERIALIZERCARD

DESERIALIZERCARD

CARLOSv3CARD

2002 CARLOSv2_rxOPTICAL

LINKSIMU

PatternGenerator

StateAnalyzer

GOL


DIU pRORC

CARLOSv3_rx Test Board (Sketch)

o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o

CARLOSv3_rxCONNECTOR

for DDLSTRIP

CONNECTOR







SIU

CARLOS v3

CARLOS v3

Final solution, still to be fully redesigned, will

receive data from about 22 CARLOS chips

PROM

SIMU

Bologna CERN/EP-AID


AMBRA CARLOSv3 CARLOSv3_rx DDL for TEST-BEAM (Sketch)

CARLOSv3_rxCARLOSv3

BOARDS

DIU pRORC

SIU

AMBRA

AMBRA

Bologna CERN/EP-AID

AMBRA

AMBRA

BolognaTorino

At CERN Serial Back-Link and JTAG signals must be provided

through DDL

Serial Back-Link

4-bit JTAG

SIMU

State Analyzer

Pattern Generator

Serial Back-Link

4-bit JTAG


Test of the chain with the DDL at CERN (06/06/03)

CARLOSv3

CARLOSv3_rx

SIU (DDL)

Optical Fiber to Linux PC

(DDL)

For the second year this was the first ALICE DDL chain tested at CERN: to be presented next week at DAQ meeting

test-bench (50-kword event)

Up to 3M events transferred


Test of the LAST YEAR chain with the DDL at CERN (14/06/02)CERN INTERNAL REPORT ALICE-INT-2002-24

This year we are planning to write

another internal note for the new DAQ test


CARLOSv4: further test chip before production:

estimated area always 4x4 mm2

Further tests at CERN for tuning the DAQ chain:

CARLOSv3-CARLOSv3_rx-DDL

Test-Beam on August 2003 with front-end electronics

(SDD Detector, Pascal, Ambra)

Design of the final versions of CARLOS chip, CARLOS_rx board

Bologna work plan 2003

CARLOSv3 0.25 m m Rad-Hard & ALICE SDD DAQ Chain Test

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