Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1

Carbon Nanotubes Blowing New Life Into NPDynamic CMOS Circuits

Yanan Sun, Student Member, IEEE, and Volkan Kursun, Senior Member, IEEE

Abstract—Low-power, compact, and high-performance NPdynamic CMOS circuits are presented in this paper assuming a16 nm carbon nanotube transistor technology. The performancesof two-stage pipeline 32-bit carry lookahead adders are evaluatedbased on HSPICE simulation with the following four differentimplementations: silicon MOSFET (Si-MOSFET) domino logic,Si-MOSFET NP dynamic CMOS, carbon nanotube MOSFET(CN-MOSFET) domino logic, and CN-MOSFET NP dynamicCMOS. While providing similar propagation delay, the totalarea of CN-MOSFET NP dynamic CMOS adder is reduced by35.53%, 77.96%, and 15.52% as compared to the Si-MOSFETdomino, Si-MOSFET NP dynamic CMOS, and CN-MOSFETdomino adders, respectively. Miniaturization of the CN-MOSFETNP dynamic CMOS circuit reduces the dynamic switching powerconsumption by 80.54%, 95.57%, and 25.66% as compared tothe Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, andCN-MOSFET domino circuits, respectively. Furthermore, theCN-MOSFET NP dynamic CMOS adder provides up to 99.98%savings in leakage power consumption as compared to the otheradder circuits that are evaluated in this study.

Index Terms—Carbon based electronics, carbon nanotube tran-sistor technology, domino logic, dynamic logic, electron mobility,high performance, hole mobility, low power.

I. INTRODUCTION

D YNAMIC CMOS circuits are commonly employed forenhanced propagation speed on the critical signal paths

of microprocessors [1]–[9]. Inputs are evaluated with a networkthat is composed of only NMOS transistors in an n-type dy-namic CMOS gate (see Fig. 1(a)). Alternatively, in a p-type dy-namic CMOS circuit (see Fig. 1(c)), the inputs are evaluatedwith a network of PMOS transistors. N-type dynamic CMOSgates are preferred for smaller silicon area and lower power con-sumption in traditional silicon-based integrated circuits [1]–[3],[5]–[9].An n-type dynamic logic gate produces a monotonically

falling output. N-type dynamic CMOS circuits however require

Manuscript received December 12, 2012; revised March 21, 2013; acceptedApril 24, 2013. This work was supported in part by a postgraduate scholar-ship through The Nanoscience and Technology Program of the School of En-gineering at the Hong Kong University of Science and Technology. This paperwas recommended by Associate Editor B.-H. Gwee.The authors are with the Department of Electronic and Computer Engi-

neering, The Hong Kong University of Science and Technology, Clear WaterBay, Kowloon, Hong Kong.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2013.2268131

monotonically rising inputs for proper operation. The outputof an n-type dynamic logic gate therefore cannot directly drivethe inputs of other n-type dynamic gates [5]. Two differenttechniques exist to satisfy the monotonicity requirement indynamic circuits: the domino logic circuit technique and NPdynamic CMOS circuit technique [4], [5]. The domino logiccircuit technique satisfies the monotonicity requirement byplacing a static CMOS inverter between two successive n-typedynamic logic gates as show in Fig. 1(b). Alternatively, anNP dynamic CMOS circuit is formed by cascading alternatingn-type and p-type dynamic logic gates as shown in Fig. 1(d).For proper operation, p-type dynamic CMOS circuits requiremonotonically falling inputs. The output of an n-type dynamiclogic gate can therefore directly drive the input of a p-typedynamic logic gate. Furthermore, a p-type dynamic CMOS gateproduces a monotonically rising output. Cascading alternatingstages of n-type and p-type dynamic logic gates thereforesatisfies the monotonicity requirements of inputs in dynamicCMOS circuits.In NP dynamic CMOS logic circuits, static CMOS inverters

on the critical data propagation path are avoided, thereby re-ducing the propagation delay as compared to standard dominologic circuits [4]. The NP dynamic CMOS circuits however typ-ically consume high power and occupy large area when imple-mented with the conventional silicon MOSFETs. The mobilityof holes is substantially lower as compared to electrons in sil-icon. In order to provide similar evaluation speed, the sizes ofp-channel Si-MOSFETs are enlarged in the pull-up transistornetworks of p-type dynamic logic gates as compared to the sizesof n-channel devices in the pull-down transistor networks ofn-type dynamic gates. The area and power consumption over-heads are therefore significant in NP dynamic CMOS circuitswith the conventional silicon CMOS technology. Furthermore,as the CMOS technology is scaled into the sub-22 nm regime,the short-channel effects and subthreshold leakage currents ofSi-MOSFETs are increased. With the scaling of Si-MOSFETtechnology, the reliability of CMOS circuits is degraded whilethe power consumption is increased [1], [10], [11]. Reducingpower consumption and miniaturizing silicon area while pro-viding high data processing speed are currently important chal-lenges in dynamic CMOS circuits [1]–[3], [10].Alternative materials and devices are needed to extend the

scaling of CMOS technology. Carbon nanotube MOSFETs(CN-MOSFETs) display desirable characteristics such as highercarrier mobility and smaller device footprint (area) as comparedto the conventional Si-MOSFETs [12]–[17]. While movingalong a carbon nanotube, electrons and holes display nearballistic transport with similar mobilities [15]. N-channel and

1549-8328/$31.00 © 2013 IEEE


2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 1. Dynamic CMOS circuits. (a) An n-type dynamic logic gate. (b) A domino logic circuit. (c) A p-type dynamic logic gate. (d) An NP dynamic CMOS circuit.

p-channel CN-MOSFETs with identical physical dimensionstherefore produce similar active currents in a carbon nanotubetransistor technology [13]–[15].The evaluation speed of a p-type CN-MOSFET dynamic gate

is comparable to the same sized n-type CN-MOSFET dynamicgate. The well-known area and power consumption disadvan-tages of NP dynamic CMOS circuits are therefore eliminatedby employing a carbon nanotube transistor technology. The NPdynamic CMOS logic family can be thereby rejuvenated as abetter alternative to the conventional domino logic for the im-plementation of future high speed digital integrated circuits withcarbon nanotube transistors.In this paper, low power, compact, and high performance

NP dynamic CMOS circuits with carbon nanotube transistorsare presented. The paper is organized as follows. Device pro-files of high-performance complementary CN-MOSFETs with16 nm channel length are presented in Section II. To demon-strate the advantages of NP dynamic CMOS circuit techniqueas compared to the domino logic circuit technique, 32-bit carrylookahead adders (CLAs) are designed with carbon nanotubetransistors. The adder circuits are described in Section III. Theperformances of the Si-MOSFET and CN-MOSFET adders arecompared in Section IV. Finally, some conclusions are offeredin Section V.

II. HIGH-PERFORMANCE COMPLEMENTARY CN-MOSFETS

The physical parameters of high-performance n-channeland p-channel CN-MOSFETs are presented assuming a 16 nmCMOS technology in this section. The active currents ,subthreshold leakage currents , overall switch perfor-mance , and subthreshold slopes of CN-MOSFETsare compared with the minimum sized bulk Si-MOSFETs.The 16 nm Predictive Technology Model for high-perfor-mance from the Arizona State University (PTM HP [18]) isused to evaluate the Si-MOSFETs. Alternatively, the evalu-ation of CN-MOSFETs is based on the Stanford UniversityCN-MOSFET HSPICE compact model [19]–[21].

The full set of physical parameters of 16 nm CN-MOSFETsis presented in [12]. Due to the high switching activity factor, power consumption of dynamic CMOS circuits are typi-

cally high [2], [3], [5], [22]. Dynamic CMOS circuits thereforetend to be located at or near the hot-spots in typical micropro-cessors [2], [3]. The die temperature is assumed to be 90 (atypical hot-spot temperature in current multi-core high-perfor-mance microprocessors [23]) in this study. The channel lengthsof all the transistors are 16 nm in this study. Thepower supply voltage is 0.7 V [12]–[14].The top view of a CN-MOSFET is shown in Fig. 2(a). The

carbon nanotubes (CNs) are heavily doped with donors (forn-channel) or acceptors (for p-channel) in the source and drainextension regions of a CN-MOSFET. The carbon nanotubesare undoped under the gate. Nanotube diameter andnanoarray pitch determine the performance and area of acarbon nanotube transistor [12]–[14]. N-channel CN-MOS-FETs with uniform nanotube diameter and uniform nanoarraypitch values that are suitable for VLSI are presented in [13]. Acomplementary study for p-channel carbon nanotube transis-tors with uniform diameter and pitch is provided in [14]. Theoptimum uniform diameter is 0.84 nm with a uniform pitchof 5.3 nm in both n-channel and p-channel CN-MOSFETs forachieving high performance while maintaining high integrationdensity in 16 nm technology node [13], [14].The substrate acts as a second (bottom) gate below the

thick oxide layer in a CN-MOSFET [12]–[14]. The substrateis shared by both n-channel and p-channel CN-MOSFETsin an integrated circuit as illustrated in Fig. 2(b). A sub-strate bias voltage that is half of the power supply voltage

is employed for producing similaractive currents with the n-channel and p-channel CN-MOS-FETs in this study.The strength of a CN-MOSFET is tuned by adjusting the

number of tubes that form the channel [12]. The active cur-rents , subthreshold leakage currents , overall switchperformance , and subthreshold slopes of n-channel


SUN AND KURSUN: CARBON NANOTUBES BLOWING NEW LIFE INTO NP DYNAMIC CMOS CIRCUITS 3

TABLE IIIMINIMUM SIZED HIGH-PERFORMANCE SI-MOSFETS AND CN-MOSFETS THAT PRODUCE SIMILAR .

Fig. 2. (a) Top-view of a CN-MOSFET. (b) Cross sectional view of astatic CMOS inverter with CN-MOSFETs. Circuit symbols of n-channel andp-channel CN-MOSFETs are indicated. The source/drain contact material:Chromium/Aurum (Cr/Au). The gate material: Platinum/Aurum (Pt/Au) [24].

TABLE I, , , AND SUBTHRESHOLD SLOPES OF OPTIMIZED

N-CHANNEL CN-MOSFETS.

TABLE II, , , AND SUBTHRESHOLD SLOPES OF OPTIMIZED

P-CHANNEL CN-MOSFETS.

All the device sizes for are considered in this study.However, only four transistor sizes are listed in Tables I and II due to thelimited space in the paper.

Fig. 3. (a) Symbol of a 32-bit carry lookahead adder. (b) Sum generator for theNP dynamic CMOS and domino logic CLAs.

and p-channel CN-MOSFETs with different numbers of tubesare listed in Tables I and II. A substrate bias voltage of 0.35 V,a uniform diameter of 0.84 nm, and a uniform pitch of 5.3 nm

are assumed for all the CN-MOSFETs in this study. As listed inTables I and II, similar active currents are produced by then-channel and p-channel CN-MOSFETs with identical numbersof tubes. In the on-state, the charge induced on the nanotubesthat form the channel array of a multi-tube CN-MOSFET in-teract [12]. Charge screening reduces the effective width of thechannel, thereby degrading the device current. The active cur-rent that is produced by a CN-MOSFET is not directly propor-tional to the number of tubes due to the charge screeningeffect in the carbon nanotube channel array [12], [20], [25].The total area of a CN-MOSFET is determined by the phys-

ical gate width [12]. is [12]

(1)

where is the uniform array pitch, is the number of tubesin a CN-MOSFET, is the uniform nanotube diameter, and

is the overhang width of the gate from the edge of CN arrayas shown in Fig. 2(a). In a Si-MOSFET, the overhang width ofthe gate from the edge of active region is typically [26]. As-suming a similar photolithographic manufacturing process forthe carbon-nanotube transistors, at each end is assumed tobe (16 nm) in this study. From (1), the physical gate width(including the overhangs) of a minimum sized CN-MOSFETwith only one nanotube in the channel is

. Alternatively, the minimum channel width of activeregion under the gate of a Si-MOSFET is assumed to be ac-cording to the photolithographic manufacturing process [26].The physical gate width (including the overhangs) of a min-imum sized Si-MOSFET is .The performances of CN-MOSFETs and Si-MOSFETs

are compared next. The numbers of tubes in the CN-MOS-FETs are adjusted to provide similar as compared to theminimum sized Si-MOSFETs. The , , , andsubthreshold slope of the transistors are listed in Table III (as-suming ). The leakage current that is producedby CN-MOSFETs is significantly suppressed as comparedto the Si-MOSFETs as listed in Table III. The subthresholdslope [1] is also reduced with the CN-MOSFET technologyas compared to the Si-MOSFET technology. Carbon nanotubetransistors thereby provide orders of magnitude higher perfor-mance as compared to the silicon transistors. Dueto the significantly higher hole mobility in carbon nanotubes[27], the gate width of a p-channel CN-MOSFET is smaller ascompared to a minimum sized p-channel Si-MOSFET whenthe two transistors are designed to produce similar , as listedin Table III.



Fig. 4. A multi-stage NP dynamic CMOS pipeline with carbon nanotube transistors. The output of latch of CLK-stage drives the first level of gates inthe following CLKB-stage.

III. 32-BIT CARRY LOOKAHEAD ADDERS WITH NP DYNAMICCMOS AND DOMINO LOGIC CIRCUIT TECHNIQUES

Carry lookahead adders (CLAs) are commonly used inmodern processors [2], [3]. To demonstrate the advantagesof NP dynamic CMOS circuit technique as compared to thedomino logic circuit technique in a carbon nanotube transistortechnology, two 32-bit carry lookahead adders are describedin this section. The adders are designed as two-stage pipelinesfor high speed operation. For a fair comparison, each pipelinestage contains 5 levels of dynamic logic gates and 5 levels ofdomino logic gates in the NP dynamic CMOS and dominoadders, respectively.The input vectors of a 32-bit CLA are denoted as ( to) and ( to ) as shown in Fig. 3(a). The carry input

and clock input of the adder are denoted as and ,respectively. The sum output and carry output for each bit posi-tion are denoted as and , respectively. Thecarry output of the 32-bit CLA is as illustrated in Fig. 3(a).Since the sum outputs ( to ) are not on the critical prop-agation delay path, each sum bit is produced by two staticCMOS XOR gates as shown in Fig. 3(b). The structures of theadders with NP dynamic CMOS and domino logic circuit tech-niques are presented in Sections III-A and III-B, respectively.

A. NP Dynamic CMOS Adder

An NP dynamic CMOS circuit is formed by cascading alter-nating n-type and p-type dynamic logic gates as illustrated inFig. 1(d). The NP dynamic CMOS logic circuits are used to im-plement race-free pipelines [4]. In a multi-stage NP dynamicCMOS pipeline, a -stage is preceded and followed by a

-stage as illustrated in Fig. 4. In the -stage, theprecharging and evaluation of the n-type dynamic logic gatesare controlled by the true phase of the clock signal . Al-ternatively, the predischarging and evaluation of the p-type dy-namic logic gates are controlled by the inverted clock signal

. In the -stage, and signals are in-terchanged as compared to the -stage as shown in Fig. 4.To form an NP dynamic CMOS pipeline with proper operation,the output information of each stage should be held constantduring the evaluation of the following pipeline stage. ClockedCMOS latches are used to store the output informa-tion of each stage, thereby guaranteeing race free operation inan NP dynamic CMOS circuit [4] as illustrated in Fig. 4.

The 32-bit carry generator of the NP dynamic CMOS adder isshown in Fig. 5(a). The first level of each pipeline stage is com-posed of 16 n-type footed dynamic propagate and 16 n-typefooted dynamic generate circuits. The dynamic propagateand generate circuits are shown in Fig. 5(c). The propagate andgenerate circuits are followed by alternating p-type and n-typefootless dynamic 4-bit multiple-output carry generators [9], [28]as shown in Fig. 5(a). The n-type and p-type carry generators areillustrated in Fig. 6(a) and (b), respectively.The clock signals are properly delayed to eliminate the

short-circuit current paths at each level of footless dynamiclogic gates. The circuit that is used to generate the andcomplementary is shown in Fig. 5(b). The clock input

is a 1.5 GHz square wave with 50% duty cycle.Transmission gate is used as a delay element to control theskew between and . The enable signal ismaintained high during the active mode. Alternatively, isgated low to disable the local clock signals ( and )in the idle mode.The operation of the NP dynamic CMOS adder is as

follows. When the clock signal is low, the complemen-tary clock signal is high. The pipeline-stageis in precharging/predischarging phase, while thepipeline-stage is in evaluation phase. In the -stage, thedynamic nodes ( , , ,and ) of the n-type dynamic logic gates areprecharged to V through the corresponding p-channelprecharge transistors. Alternatively, the dynamic nodes( and ) of the p-type dynamic logicgates are predischarged to 0 V through the n-channel pre-discharge transistors. The latch at the end of the

-stage is opaque. The output information of the-stage is therefore held constant by the latch

during the evaluation of the following -stage. In thepipeline-stage, the inputs of the dynamic gates are

evaluated. If the pull-down transistor networks of the n-typedynamic logic gates are turned off by the corresponding inputvectors, the dynamic outputs ( , ,

, and ) are maintained atby the p-channel keepers. Alternatively, the dynamic out-puts are discharged if the pull-down transistor networks ofthe n-type logic gates are activated. Similarly, the dynamicoutputs ( and ) are maintained at 0 Vby the n-channel keepers provided that the pull-up transistor



Fig. 5. Various components of two-stage pipeline 32-bit carry lookahead adders. (a) 32-bit carry generator of the NP dynamic CMOS CLA. (b) ‘CLK’ and ‘CLKB’signals generator for the NP dynamic CMOS and domino logic adders. ‘EN’ is enable signal (active high). (c) N-type footed dynamic propagate (Pi) and generate(Gi) circuits. For Si-MOSFET technology: . W: the physicalgate width excluding the overhangs of a Si-MOSFET. For CN-MOSFET technology:

. N: the number of tubes in a CN-MOSFET. The critical propagation delay paths are illustrated with dashed lines.

networks of p-type dynamic gates are cut off. Alternatively,the dynamic nodes are charged to if the pull-up transistornetworks of the p-type logic gates are activated. Thelatch at the end of the -stage is transparent. The carryoutput of the 32-bit CLA is determined by ,

, , , and .The sum outputs to are determined by ,

, , , , and.

Subsequently, when and transition to highand low, respectively, the inputs of the dynamic gates inthe -stage are evaluated while the -stage is inprecharging/predischarging phase. The latch at theend of the -stage becomes transparent while thelatch at the end of the -stage is opaque. The outputof the latch in the -stage is deter-mined by the inputs , , ,

, and . The sum outputs to are deter-mined by , , , ,

, and .

B. Domino Logic Adder

The 32-bit carry generator of the two-stage pipeline CLA thatis implemented with the conventional domino logic circuit tech-nique is shown in Fig. 7. Domino logic circuits are typicallyconstructed with n-type dynamic gates due to the higher elec-

tron mobility as compared to the hole mobility in silicon CMOStechnology. For a fair comparison with the silicon transistortechnology, the CN-MOSFET domino adder is also composedof only n-type dynamic gates in this study. The clock signals areproperly delayed to eliminate the short-circuit current paths ateach level of footless n-type dynamic CMOS gates [1] as shownin Fig. 7. The operation of the domino logic CLA is similar tothe NP dynamic CMOS CLA.

IV. COMPARISON OF NP DYNAMIC CMOS AND DOMINOLOGIC CIRCUITS WITH CARBON NANOTUBE AND SILICON

TRANSISTOR TECHNOLOGIES

In this section, the propagation delay, total transistor area,dynamic switching power consumption, and leakage powerconsumption of adders with the following four different imple-mentations are evaluated and compared: Si-MOSFET dominologic, Si-MOSFET NP dynamic CMOS, CN-MOSFET dominologic, and CN-MOSFET NP dynamic CMOS. The adders aredesigned to operate with a 1.5 GHz clock. The transistor sizingfor achieving similar propagation delay with the four adders ispresented in Section IV-A. The total transistor area, dynamicswitching power consumption, and leakage power consumptionof the adders are compared in Sections IV-Bto IV-D.

A. Transistor Sizing in Dynamic Adders

For all of the four adders, the transistors are sized to achievesimilar (within 2%) propagation delay along the critical signal



Fig. 6. 4-bit multiple-output carry generators. (a) N-type footless dynamic 4-bit multiple-output carry generator. For Si-MOSFET technology:, ,

. For CN-MOSFET technology: ,, . (b) P-type footless dynamic 4-bit multiple-output carry generator. For Si-MOSFET technology:

, , .For CN-MOSFET technology: , ,

. The critical propagation delay paths for and are illustrated with dashed lines.

paths. The load capacitors at sum outputs ( to ) and carryoutput are assumed to be 0.25 fF (which is equal to thegate capacitance of a Si-MOSFET inverter that is 4 larger ascompared to the minimum sized un-skewed static CMOS in-verter). The physical gate widths (including the overhangs) ofSi-MOSFETs in the minimum sized un-skewed static CMOSinverter are: and .Precharge and predischarge delays are not critical in dy-

namic CMOS circuits [1], [4], [5]. Alternatively, the delays ofthe worst-case pull-down paths of the n-type dynamic logicgates and the worst-case pull-up paths of the p-type dynamiclogic gates are critical in determining the evaluation speed ofa dynamic CMOS circuit. The critical evaluation (discharge)path of the n-type dynamic 4-bit carry generator is along the

path as illustrated in Fig. 6(a). Alternatively,the critical evaluation (charge) path of the p-type dynamic4-bit carry generator is along the path as shownin Fig. 6(b). In every dynamic gate, the precharge or predis-charge device is sized to provide approximately half [5] of thestrength of the worst-case evaluation path. In the domino logicadders, the output static CMOS inverter of each domino gate ishigh-skewed since the high-to-low transition of domino outputis not critical. The size of the n-channel transistor in each outputstatic CMOS inverter is tuned to have approximately half ofthe strength of the p-channel device.The keeper in each dynamic logic gate is designed to provide

approximately 10% [5] of the strength of the worst-case pull-down (for n-type dynamic gate) or pull-up (for p-type dynamicgate) transistor stack. For small dynamic gates, the keeper isweaker than the minimum sized transistor. The weak keeper iscomposed of two transistors that are connected in series [5] asshown in Figs. 5(c) and 6.The longest propagation delay path is observed for the

output in all four adders. The propagation delay path foris excited withwhen the enable signal is high. The propagation delay

of is the time interval from 50% high-to-low transitionof the clock input ( transitions from lowto high) until the carry output is pulled up tofrom 0. The critical propagation delay paths of the NP dy-namic CMOS and domino logic adders are illustrated withdashed lines in Figs. 5(a) and 7, respectively, assuming

.The design criteria for the conventional Si-MOSFET domino

adder are described next. The precharge devices are minimumsized in all of the n-type dynamic gates. The strengths of theworst-case pull-down paths of all the n-type gates are tuned toprovide approximately twice [5] the strengths of the prechargedevices. The physical gate widths (including the overhangs) ofn-channel transistors along the worst-case pull-down path ofeach n-type dynamic gate in the Si-MOSFET domino adder arelisted in Table IV. Both - and -stages are endedwith the same sized latches. The propagation delay for

is 302 ps in the Si-MOSFET domino adder.For a fair comparison, the transistor sizes of the Si-MOSFET

NP dynamic CMOS CLA are tuned to achieve similar prop-agation delay as compared to the Si-MOSFET domino logicadder. In the 32-bit carry generator of Si-MOSFET NP dynamicCMOS adder, the required physical gate widths (including theoverhangs) of Si-MOSFETs along the worst-case pull-downpath of each n-type dynamic gate and the worst-case pull-uppath of each p-type dynamic 4-bit carry generator are listedin Table IV. The mobility of holes is substantially lower ascompared to electrons in silicon. In order to provide similarevaluation speed with the n-type and p-type dynamic carrygenerators, the p-channel Si-MOSFETs ( : 1880nm) are enlarged as compared to the n-channel Si-MOSFETs( : 944 nm) as listed in Table IV. The NMOS transis-tors in the n-type dynamic gates are sized sufficiently wide to beable to drive the huge PMOS transistors of the following p-typedynamic gates while satisfying the propagation delay goal. Thetransistors are therefore significantly larger in the Si-MOSFET



Fig. 7. 32-bit carry generator of the domino logic CLA. The critical propagation delay paths are illustrated with dashed lines.

NP dynamic CMOS adder as compared to the Si-MOSFETdomino adder, as listed in Table IV. The propagation delay for

is 306 ps in the Si-MOSFET NP dynamic CMOS CLA.The numbers of tubes are tuned to achieve similar prop-

agation delay with the CN-MOSFET domino logic CLA ascompared to the Si-MOSFET circuits. The required numbersof tubes and physical gate widths (including the overhangs)of n-channel CN-MOSFETs along the worst-case pull-downpath of each n-type dynamic logic gate are listed in Table IV.The propagation delay for is 301 ps in the CN-MOSFETdomino adder.The numbers of tubes are also tuned in the CN-MOSFET

NP dynamic CMOS CLA in order to provide similar propa-gation delay as compared to the Si-MOSFET circuits. The re-quired numbers of tubes of transistors are listed in Table IV. Un-like the conventional silicon CMOS technology, electrons andholes have similar mobilities in the carbon nanotube transistortechnology [15]. As listed in Table IV, the required numbersof tubes of p-channel CN-MOSFETs are there-fore equal to the n-channel CN-MOSFETs inthe multiple-output carry generators. The propagation delay for

is 299 ps in the CN-MOSFET NP dynamic CMOS CLA.Unlike the CN-MOSFET domino circuit, the static CMOS in-verters are avoided on the critical propagation delay path of theCN-MOSFET NP dynamic CMOS CLA. The required numbersof carbon nanotubes are thereby reduced and the transistor sizesare miniaturized in the CN-MOSFETNP dynamic CMOS adderas compared to the CN-MOSFET domino logic adder, when thetwo circuits are designed for similar propagation delay, as listedin Table IV.

B. Overall Transistor Area

The total transistor areas of the adders are listed in Table V.The area of an adder is a rough estimate based on the sum-mation of the area of each individual transistor in the circuit

. The mobility ofholes is substantially lower as compared to electrons in silicon.In order to provide similar propagation delay, the sizes of tran-

sistors are significantly enlarged in the p-type dynamic logicgates of the NP dynamic CMOS adder with the conventionalsilicon transistor technology. In order to drive the inputs ofthese p-type Si-MOSFET dynamic gates with sufficient speedto satisfy the propagation delay goal, the NMOS transistorsin the n-type dynamic CMOS gates are also sized sufficientlylarge as listed in Table IV. The cumulative transistor area ofthe Si-MOSFET NP dynamic CMOS adder is therefore 2.92larger as compared to the Si-MOSFET domino logic circuitas listed in Table V. Alternatively, the mobilities of electronsand holes are similar in carbon nanotube transistors. The samesized n-type and p-type dynamic logic gates therefore producesimilar currents in a carbon nanotube transistor technology. Theoverall transistor area of the CN-MOSFET NP dynamic adderis 35.53% and 77.96% smaller as compared to the Si-MOSFETdomino logic and Si-MOSFET NP dynamic CMOS adders,respectively, due to the higher mobilities of charge carriers incarbon nanotubes as compared to silicon. Furthermore, thereare no static CMOS inverters on the critical data propagationpath of the NP dynamic CMOS adder. The cumulative tran-sistor area of the CN-MOSFET NP dynamic CMOS circuit istherefore reduced by 15.52% while providing similar propa-gation delay as compared to the CN-MOSFET domino logiccircuit as listed in Table V.

C. Dynamic Switching Power Consumption

The dynamic switching power consumption ofthe four adders is measured for

when the enable signalis high. The dynamic output switching power

consumption is

(2)

where is the switching activity factor, is thecapacitive load at the dynamic output, and is the clock fre-quency. Since the dynamic output needs to be charged and dis-charged every clock cycle, the activity factor is maximized



TABLE IVPHYSICAL GATE WIDTHS (INCLUDING THE OVERHANGS) OF CRITICAL TRANSISTORS IN SI-MOSFET AND CN-MOSFET 32-Bit ADDERS THAT ARE DESIGNED

FOR SIMILAR PROPAGATION DELAY.

TABLE VPROPAGATION DELAY, DYNAMIC SWITCHING POWER CONSUMPTION, POWER-DELAY PRODUCT, LEAKAGE POWER CONSUMPTION, AND TOTAL TRANSISTOR

AREAS OF CN-MOSFET AND SI-MOSFET 32-Bit CARRY LOOKAHEAD ADDERS.

with .Due to the smaller sizes of transistors in the CN-MOSFET NPdynamic CMOS CLA as listed in Table V, the parasitic ca-pacitors at the dynamic nodes are also smaller as compared tothe other adders. As listed in Table V, the dynamic switchingpower consumption of the CN-MOSFET NP dynamic CMOSCLA is 80.54%, 95.57%, and 25.66% lower as compared to theSi-MOSFET domino logic, Si-MOSFET NP dynamic CMOS,and CN-MOSFET domino logic adders, respectively.

D. Leakage Power Consumption

In an idle dynamic logic circuit, the enable signalis gated low. and are thereby gated

high. The precharge/predischarge transistors are cut-offin the idle mode. The leakage power consumptions ofthe idle adders are measured with two input vectors

and (1, FFFFFFFF,FFFFFFFF). The average leakage power consumption for thetwo input vectors is evaluated. Leakage power consumed by theidle adders are listed in Table V. The CN-MOSFETNP dynamicCMOS adder provides 99.94% and 99.98% savings in leakagepower consumption as compared to the Si-MOSFET dominologic and Si-MOSFET NP dynamic CMOS circuits, respec-tively, as listed in Table V. The significantly reduced leakagepower consumption is due to the steeper subthreshold slopesand smaller sizes of CN-MOSFETs as compared to Si-MOS-FETs. The leakage power consumption of the CN-MOSFETNP dynamic CMOS circuit is suppressed by 36.54% due to thesmaller sizes of transistors as compared to the CN-MOSFETdomino adder as well.

V. CONCLUSIONS

Low-power, compact, and high-performance NP dynamicCMOS circuits with a 16 nm carbon nanotube transistor tech-nology are presented in this paper. The performances of four32-bit carry lookahead adders with different circuit techniquesand technologies are characterized: Si-MOSFET domino logic,Si-MOSFET NP dynamic CMOS, CN-MOSFET domino logic,and CN-MOSFET NP dynamic CMOS. The well-known areaand power consumption disadvantages of the NP dynamicCMOS circuits are eliminated by employing a carbon nanotubetransistor technology. The CN-MOSFET NP dynamic CMOScircuit effectively suppresses both dynamic switching andleakage power consumption while providing similar propa-gation delay and miniaturizing the area as compared to bothsilicon and carbon nanotube domino logic circuits. The NPdynamic CMOS logic family is recommended as a better alter-native to the conventional domino logic for the implementationof future high speed digital integrated circuits with carbonnanotube transistors.The total area of the CN-MOSFET NP dynamic CMOS

adder is reduced by 35.53%, 77.96%, and 15.52% whileproviding similar propagation delay as compared to theSi-MOSFET domino logic, Si-MOSFET NP dynamic CMOS,and CN-MOSFET domino logic circuits, respectively. Minia-turization of the CN-MOSFET NP dynamic CMOS circuitreduces the dynamic switching power consumption by 80.54%,95.57%, and 25.66% as compared to the Si-MOSFET dominologic, Si-MOSFET NP dynamic CMOS, and CN-MOSFETdomino logic circuits, respectively. Furthermore, the leakagepower consumption of the carbon-based NP dynamic CMOSadder is suppressed by up to 99.98% as compared to the con-ventional silicon-based dynamic circuits, due to the steeper



subthreshold slopes and smaller sizes of CN-MOSFETs ascompared to Si-MOSFETs.

REFERENCES

[1] V. Kursun and E. G. Friedman, Multi-Voltage CMOSCircuit Design.New York, NY, USA: Wiley, 2006.

[2] S. B.Wijeratne, N. Siddaiah, S. K.Mathew,M. A. Anders, R. K. Krish-namurthy, J. Anderson, M. Ernest, and M. Nardin, “A 9-GHZ 65-nmIntel Pentium 4 processor integer execution unit,” IEEE J. Solid-StateCircuits, vol. 42, no. 1, pp. 26–37, Jan. 2007.

[3] S. Mathew, M. Anders, R. K. Krishnamurthy, and S. Borkar, “A 4-GHz130-nm address generation unit with 32-bit sparse-tree adder core,”IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 689–695, May 2003.

[4] N. F. Goncalves and H. J. De Man, “NORA: A racefree dynamicCMOS technique for pipelined logic structures,” IEEE J. Solid-StateCircuits, vol. SC-18, no. 3, pp. 261–266, Jun. 1983.

[5] N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits andSystems Perspective. Boston, MA, USA: Pearson/Addison-Wesley,2005.

[6] Z. Liu and V. Kursun, “Shifted leakage power characteristics ofdynamic circuits due to gate oxide tunneling,” in Proceedings of theIEEE International Systems on Chip (SOC) Conference, Sep. 2005,pp. 151–154.

[7] V. Kursun and E. G. Friedman, “Domino logic with dynamic bodybiased keeper,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2002, pp.675–678.

[8] Z. Liu and V. Kursun, “Leakage biased PMOS sleep switch dynamiccircuits,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp.1093–1097, Oct. 2006.

[9] V. Kursun and E. G. Friedman, “Variable threshold voltage keeperfor contention reduction in dynamic circuits,” in Proc. IEEE Int.ASIC/SOC Conf., Sep. 2002, pp. 314–318.

[10] B. H. Calhoun, Y. Cao, X. Li, K.Mai, L. T. Pileggi, R. A. Rutenbar, andK. L. Shepard, “Digital circuit design challenges and opportunities inthe era of nanoscale CMOS,” Proc. IEEE, vol. 96, no. 2, pp. 343–365,Feb. 2008.

[11] J. W. McPherson, “Reliability challenges for 45 nm and beyond,” inProc. ACM/IEEE Design Automation Conf., Jul. 2006, pp. 176–181.

[12] Y. Sun and V. Kursun, “N-type carbon-nanotubeMOSFET device pro-file optimization for very large scale integration,” Trans. Electri. Elec-tron. Mater., vol. 12, no. 2, pp. 43–50, Apr. 2011.

[13] Y. Sun andV. Kursun, “Uniform diameter and pitch co-design of 16 nmn-type carbon nanotube channel arrays for VLSI,” in Proc. IEEE/ACMAsia Symp. Quality Electronic Design, Jul. 2011, pp. 211–216.

[14] Y. Sun and V. Kursun, “Uniform carbon nanotube diameter andnanoarray pitch for VLSI of 16 nm p-channel MOSFETs,” in Proc.IEEE Int. Conf. VLSI System-on-Chip (VLSI-SoC), Oct. 2011, pp.226–231.

[15] H.-S. P. Wong and D. Akinwande, Carbon Nanotube and GrapheneDevice Physics. Cambridge, U.K.: Cambridge Univ. Press, 2011.

[16] P. Avouris, Z. Chen, and V. Perebeinos, “Carbon-based electronics,”Nature Nanotechnol., vol. 2, pp. 605–615, Oct. 2007.

[17] S. Lin, Y. Kim, and F. Lombardi, “CNTFET-based design of ternarylogic gates and arithmetic circuits,” IEEE Trans. Nanotechnol., vol. 10,no. 2, pp. 217–225, Mar. 2011.

[18] [Online]. Available: http://ptm.asu.edu/[19] [Online]. Available: https://nano.stanford.edu/stanford-cnfet-model-

hspice[20] J. Deng and H.-S. P. Wong, “A compact SPICE model for carbon-nan-

otube field-effect transistors including nonidealities and its applica-tion—Part I: Model of the intrinsic channel region,” IEEE Trans. Elec-tron Devices, vol. 54, no. 12, pp. 3186–3194, Dec. 2007.

[21] J. Deng and H.-S. P. Wong, “A compact SPICE model for carbon-nan-otube field-effect transistors including nonidealities and its ap-plication—Part II: Full device model and circuit performancebenchmarking,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp.3195–3205, Dec. 2007.

[22] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-powerCMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, no. 4, pp.473–484, Apr. 1992.

[23] B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H.Loh, D. McCauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J.Rupley, S. Shankar, J. Shen, and C. Webb, “Die stacking (3D) microar-chitecture,” in Proc. IEEE/ACM Int. Symp. Microarchitecture, Dec.2006, pp. 469–479.

[24] I. Amlani, K. F. Lee, J. Deng, and H.-S. P. Wong, “Measuring fre-quency response of a single-walled carbon nanotube common-sourceamplifier,” IEEE Trans. Nanotechnol., vol. 8, no. 2, pp. 226–233, Mar.2009.

[25] C. Kshirsagar, H. Li, T. E. Kopley, and K. Banerjee, “Accurate intrinsicgate capacitance model for carbon nanotube-array based FETs consid-ering screening effect,” IEEE Electron Device Lett., vol. 29, no. 12, pp.1408–1411, Dec. 2008.

[26] [Online]. Available: http://www.mosis.com/files/scmos/scmos.pdf[27] M. S. Fuhrer, B. M. Kim, T. Dürkop, and T. Brintlinger, “High-mo-

bility nanotube transistor memory,” Nano Lett., vol. 2, no. 7, pp.755–759, May 2002.

[28] I. S. Hwang and A. L. Fisher, “Ultrafast compact 32-bit CMOS addersin multiple-output domino logic,” IEEE J. Solid-State Circuits, vol. 24,no. 2, pp. 358–369, Apr. 1989.

Yanan Sun (S’09) received the B.E. degree in mi-croelectronics from Shanghai Jiao Tong University,Shanghai, China, in 2009. She is currently pursuingthe Ph.D. degree in electronic and computer engi-neering from the Hong Kong University of Scienceand Technology, Hong Kong, under the supervisionof Prof. V. Kursun.Her research interest is VLSI circuit design with

carbon nanotube transistor technology for low power,high performance, and manufacturability.

Volkan Kursun (S’01–M’04–SM’11) received theB.S. degree in electrical and electronics engineeringfrom the Middle East Technical University, Ankara,Turkey, in 1999, and the M.S. and Ph.D. degrees inelectrical and computer engineering from the Univer-sity of Rochester, NewYork, USA, in 2001 and 2004,respectively.He performed research on mixed-signal thermal

inkjet integrated circuits with Xerox Corporation,Webster, New York, USA in 2000. During thesummers of 2001 and 2002, he was with Intel

Microprocessor Research Laboratories, Hillsboro, OR, USA, where he wasresponsible for the modeling and design of high frequency monolithic powersupplies. During the summer of 2008, he was a visiting professor at the ChuoUniversity, Tokyo, Japan. He served as a tenure-track assistant professor inthe Department of Electrical and Computer Engineering at the University ofWisconsin—Madison, USA from August 2004 to August 2008. He has beena tenure-track assistant professor in the Department of Electronic and Com-puter Engineering at the Hong Kong University of Science and Technology,China since August 2008. His current research interests are in the areas ofgigascale 2D and 3D systems-on-chip integration with nanoscale devices andinterconnect. He has more than 130 publications and 7 issued U.S. patents inthe areas of low-power and high-performance integrated circuits and novelsemiconductor devices. He is the author of the book Multi-Voltage CMOSCircuit Design (Wiley, 2006).Dr. Kursun received the Institute of Electronics Engineers of Korea (IEEK)

Systems-on-Chip Design Group Award in 2012. He is a member of thetechnical program and organizing committees of a number of IEEE and ACMconferences. He served as the Technical Program Committee Chair of theAsia Symposium on Quality Electronic Design in 2010 and 2011. Dr. Kursunserved on the editorial boards of the IEEE TRANSACTIONS ON CIRCUITS ANDSYSTEMS—I: REGULAR PAPERS, IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS—II: EXPRESS BRIEFS, and JOURNAL OF CIRCUITS, SYSTEMS, ANDCOMPUTERS from 2007 to 2010, 2005 to 2008, and 2005 to 2011, respectively.He currently serves on the editorial boards of the IEEE TRANSACTIONS ONVERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and Journal of Low PowerElectronics and Applications.

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

Documents

Transcript of Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits