Camera Auto FocusPresentation 6, February 28th, 2007

Team W1:Tom Goff (W11)David Hwang (W12)Kate Killfoile (W13)Greg Look (W14)

Design Manager: Bowei GaiProject Goal: Design a low-power, small auto focus chip for

a camera or other hand-held device

Status

• Last Time– Exhaustive simulations– Schematic

• This WeekRigorous schematic testingControl logic structural VerilogSub-module layout

• In Process…LayoutSchematic of control logic

• UnfinishedExtraction, LVS, post-layout simulation

Design Decisions

• Split up FSM logic (detailed later)

• Decided on an adder

• Settled on sense amp registers

• Crazy optimizations of schematic

Updated Transistor Count

Component Full Chip Count

AG Preprocessor 2,274

Delta I Preprocessor 2,624

FP multiplier 5,832

FP adder 994

Power control ~1,000

Buffers 2,000

Total ~17,182

Still fluctuating…

Control Logic FSM’s

Compare [1:0]

Enable

Global rst

FSM1

Next State Logic

Pulse Generator

Next state

Output Logic

Reg[1] Reg[0]Enable next FSM

Reset Clock

Compare [3:2]

Enable FSM1

Global rst

FSM2

More complicated next state

logic

Pulse Generator

Next state [2:0]

Output Logic

Reg[3] Reg[2]Mux Lines [6:0]

Reset Clock

Bus Widths

Counter[?:0]

Compare 0

Compare 1

FSM1 FSM2

Global rst

Clk

Reset Line

Enable FSM2

Bus Path Bits

To FSM1 3

To FSM2 2

To Counter 1

Schematic Verification

• Every module completely tested

• Excluding power logic

Layout Progress

Modules Layout Completed

Basic gates 100%

Registers 100%

Muxes 100%

Adders 25%

Shifters 0%

Integer multiplier 0%

Full Adder

Full Adder

Registers

Registers

Muxes

Next Steps

• Sleep briefly

• Continue laying out modules

• Complete control logic schematic

Problems

• Pass transistors make for terrible layouts

• Shared libraries are a pain

• Selfish cluster users crowding our space; many deaths

• Difficult to synchronize FSM’s

Questions

References

• None this week