Calorimeter upgrade meeting – CERN – October 5 th 2010 Analog FE ASIC: first prototype Upgrade...

Calorimeter upgrade meeting – CERN – October 5th 2010

Analog FE ASIC: first prototype

Upgrade of the front end electronics of the LHCb calorimeter

E. Picatoste, A. Sanuy, D. Gascón

Universitat de Barcelona

Institut de Ciències del Cosmos ICC-UB

5/October/2010 LHCb Upgrade 2

Outline

(1) Introduction(2) Current Mode Preamplifier(3) Integrator

• FDOA• Switched Integrator

(4) Linearity(5) Noise(6) IC Implementation Details


Introduction

• ECAL analogue FE IC: channel architecture

MP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I

Current amplifier (mirrors)

TH

TH

AnalogueMultiplexer

Drv

ADC driver

Switched integrator

Track and Hold

First Prototype


Introduction

• IC sent: ICECAL

Current preamp

Integrators


Current mode preamplifier

• Pros:– “Natural” current processing

– Lower supply voltage

– All low impedance nodes:

• Pickup rejection

– No external components

– No extra pad

• Cons:– Trade-off in current mirrors: linearity

vs bandwidth

• Low voltage– Only 1 Vbe for the super common

base input stage

• Better in terms of ESD:– No input pad connected to any

transistor gate or base

MP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I

Current amplifier (mirrors)

TH

TH

AnalogueMultiplexer

Drv

ADC driver

Inner loop: lower input impedance

Outer loop: control input impedance

fem

i mRK

K

K

RgZ

11

1 1



• Simulations based on the extracted RC

|Zin|

Zin phase

Gain+Gain-

Possible compensations:

• Parallel R

• current ladder

|Gain|

Gain phase Gain+

Gain-



• Simulations based on the extracted RC: linearity vs. Ii,peak

Ga

in+

Ga

in-

Operation range



• Linearity error after integration (ideal) vs input charge

Linearity errror residue

-0,08

-0,06

-0,04

-0,02

0

0,02

0,04

0,06

0E+00 1E-11 2E-11 3E-11 4E-11 5E-11 6E-11

Qpmt [C]

Err

or [

%]


Integrator

• Switched integrator architecture

+

-

-

+

In+

In-Out+

Out-

FDOA

FDOA specifications

Parameter Value

Gain bandwidth

500 MHz

Phase margin > 65º

Slew rate > 2 V/μs

VCM 1.65 V

CMOS switches


M

M

Vin+

M

Vcas

VrefCE

Vout+

M

M

M

M

Vin-

M

Vcas

VrefCE

Vout-

M

MM

M

Vcmref

M

M

Vb1

Vb2 Vb2Vb2

Vb1

Vb2

FDOA: design

• Fully differential Operational Amplifier

Folded cascode

NPN CE amp

Pole compensation

RDegenertion

Common Mode

Feedback


FDOA: open loop post layout simulations

GLF (dB)

BW (KHz)

GBW (MHz)

PM (º)

G (dB)

Phase (º)

• IbCE = 900uA• Load capacitor

between 150fF and 5.1pF


FDOA: closed loop post layout simulations

• IbCE = 900uA• Load capacitor

between 150fF and 5.1pF

trise (ns)

overshoot

SR (V/ns)


Integrator: pulse response• Simulations based on extracted RC• Cl = 5pF

Vout (V)

Vint,ideal

(V)

ViD (mV)

Iin (mA)


Integrator: Linearity

• Simulations based on extracted RC• Cl = 5pF

Error (%)

Vout

(V)


Front End simulations (Preamp+integrator)

• Simulations based on extracted RC of complete IC• Includes PM signal (TDR) and cable effects

PM signal

Clipping line

cable

Preamp + integrator


Front End simulation (Preamp+integrator)• Simulations based on extracted RC of complete IC• Includes PM signal (TDR) and cable effects

VPM

VoD2

VoD1

IPM

Icable

(clipped)

Vi


Front End simulation: linearity

49,7

49,75

49,8

49,85

49,9

49,95

50

50,05

50,1

50,15

0E+00 2E-11 4E-11 6E-11

total QMP (C)

|Zi|

(O

hm

)Dynamic deviation of the input impedance


Front End simulation: linearity

-0,5

-0,4

-0,3

-0,2

-0,1

0

0,1

0,2

0,3

0,4

0E+00 2E-11 4E-11 6E-11

total QMP (C)

lin

ear

erro

r (%

)

0,0000

0,0005

0,0010

0,0015

0,0020

0,0025

0,0030

0,0035

0,0040

0,0045

0,0050

0E+00 2E-11 4E-11 6E-11

total QMP (C)

Vo

D (

V)

VoD1

0

0,5

1

1,5

2

2,5

3

0E+00 2E-11 4E-11 6E-11

total QMP (C)

Vo

D (

V)

VoD2

Linear error


-1,27 -1 -0,73 -0,46 -0,19 0,09 0,36 0,63 0,9 1,170

5

10

15

20

25

30

V(T0)-V(T2) (mV)

Noise after dynamic pedestal subtraction

σ = 479 μV

-0,95 -0,74 -0,52 -0,31 -0,1 0,12 0,33 0,54 0,75 0,970

5

10

15

20

25

30

V(T0) (mV)

σ = 377 μVNoise

Front End simulation: noise

• Transient noise analysis

Integrator 1 output

Clock

Sampling time t1 Sampling time t2

• Noise at output: distribution of V(t2)

• Noise after dynamic pedestal subtraction: distributon of V(t1)- V(t2)


IC Implementation details

• AMS SiGe BiCMOS s35• QFN package

– Substrate connected to central pad (gnd)

• When taking into account the bonding parasistics: – 3 * nominal L ⇒ danger

of ringing

• Solutions:– Include R in series with

decoupling capacitor of Vref

– Increase number of gnd pins

– Downbonds for gnd

Downbond


Prototype test PCB

• PCB designed for tests– 4 layers– 2 socket compatible– About 8x9 cm

• Chips arrived on 1st October.

Calorimeter upgrade meeting – CERN – October 5 th 2010 Analog FE ASIC: first prototype Upgrade...

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