Using NCLaunch

NCLaunch is a graphical user interface that can help you configure and launch

the compiler, elaborator, and simulator. You can also run other tools from

NCLaunch, such as the SDF Compiler, HDL Analysis and Lint, Code Coverage

Analyzer, NCBrowse, and Comparescan.

To compile, elaborate, and simulate the design with NCLaunch:

1. Start NCLaunch from the directory that contains the tutorial source files.

Use the -new option to specify that this is a new design:

% nclaunch -new &

At startup, NCLaunch displays a list of modes in which you can run the tool.

Multiple Step mode uses the ncvlog, ncvhdl, ncelab, and ncsim commands to

compile, elaborate, and simulate your design; Single Step mode uses irun to

perform these operations with one command line.

2. Click Single Step. NCLaunch displays its main window.

The left side of the window shows all of the files in the current directory.

The right side will show the design libraries, after you have compiled the

source files and elaborated the design. The top of the window contains menus

and buttons for starting the tools.

The NCLaunch main window gives you access to the tools you need to compile and

elaborate the design, as well as access to several utilities. You access the

tools and utilities by using the Tools or Utilities menu, or by clicking the

appropriate button on the toolbar. Buttons give you fast access to the tools

and utilities, by using default commandline options. Accessing forms through

the menus lets you specify non-default options.

if you do not see all of the source files that make up the design, check the

Filters setting. Make sure it is set to *.v*. You can enter the filter setting

in the text field or choose a setting from the drop-down menu attached to the

field.

3. Select the Verilog design source file:

dkm.v

Then click the right arrow, , to add the file to the Design area.

4. Select the VHDL testbench source file:

dkm_test.vhdl

Then click the right arrow, , to add the file to the Design area.

5. Choose Tools IRUN. This opens the IRUN form, where you can specify options

to the irun command. For this example, you must specify the top-level module in

the simulation.

6. Enable Other Options, and enter the following option in the text field:

-top dkm_test

7. Click OK.

After it compiles and elaborates the design, irun invokes the simulator in

graphical mode. The SimVision Design Browser and the Console windows appear.

You access your design hierarchy in the Design Browser, and enter SimVision and

simulator commands in the Console window.

In the sidebar on the left side of the Design Browser window, SimVision places

the simulation at the top of the hierarchy and assigns it the name simulator.

The top-level of the design hierarchy is placed below the simulation. In this

example, it is named dkm_test.

At startup, the Console window has two tabs. The SimVision tab lets you enter

SimVision commands, and the simulator tab lets you enter simulator commands. As

you run the simulation, the Console window also displays messages from

SimVision and the simulator.

Using the Compiler, Elaborator, and Simulator Command-

Line Interfaces

You can compile, elaborate, and simulate your design with the individual

command-line interfaces. This is useful when you want to run your simulation in

batch mode.

To compile, elaborate, and simulate the drink machine:

1. Compile the testbench with the following ncvhdl command:

% ncvhdl dkm_test.vhdl

2. Compile the Verilog design with the following ncvlog command:

% ncvlog dkm.v

3. Elaborate the design with the following ncelab command:

% ncelab -access rwc dkm_test

The -access rwc option gives you read, write, and connectivity access to the

design objects. This makes it possible for you to probe signals and display

their values in SimVision.

4. Run the simulator with the following ncsim command:

% ncsim -gui dkm_test &

The -gui option invokes SimVision at the start of simulation.

Using the irun Command-Line Interface

The irun utility lets you run the simulator by specifying all input files and

command-line options on a single command line. The utility simplifies the

invocation process by letting you use one tool to invoke the simulator instead

of invoking multiple tools separately to piece together the snapshot to be

simulated.

To compile, elaborate, and simulate the drink machine with irun:

Issue the following command:

% irun -access rwc -gui -top worklib.dkm_test:vhdl dkm_test.vhdl dkm.v &

The -access rwc option gives you read, write, and connectivity access to the

design objects. This makes it possible for you to probe signals and display

their values in SimVision.

The -gui option invokes SimVision at the start of simulation.

The -top option specifies the top-level design unit that you want to simulate.

You must use this option when your top level is written in VHDL. When it is

written in Verilog, irun can determine the top level by analyzing the design.

Specman

Verilog Example

The two files are:

xor.v Behavioral XOR model written in Verilog. This XOR design takes two

input bits and computes one output bit, which is the exclusive-or of the two

inputs.

xor_verify.e Testing environment for the design, written in e.

Running with Interpreted e Code

You can use irun to simulate this design with interpreted e code that is, e

code loaded into Specman, rather than compiled. The following command loads the

e file into Specman, generates the HDL stubs file, invokes ncvlog to compile

the Verilog files, and then invokes the elaborator and simulator.

% irun xor.v -snload xor_verify.e

You can include the -gui option to invoke the SimVision and Specview GUIs.

Running with Compiled e Code

You can precompile e files and then run Specman. If you use irun, the following

command calls sn_compile.sh to compile the e file into a shared library, loads

the e file into Specman, generates the HDL stubs file, invokes the Verilog

compiler, the elaborator, and then the simulator. The simulator automatically

loads the shared library.

% irun xor_verify.e xor.v

VHDL Example

The two files are:

xor.vhd Behavioral XOR model written in VHDL.

xor_verify.e Testing environment for the design, written in e.

To simulate this design with interpreted e code that is, e code loaded into

Specman, rather than compiled, use the following irun command:

% irun xor.vhd -snload xor_verify.e -top worklib.xor_try

This command generates the Specman stubs file, loads the e file, invokes ncvhdl

to compile the VHDL files, and then invokes the elaborator and simulator. It is

not necessary to instantiate SPECMAN_REFERENCE in your VHDL code. The -top

option is required because the top-level unit is VHDL.

Mixed-Language Example

The three files are:

xor_specman.vhd Defines the topmost VHDL entity xor_top, which instantiates

xor_try (Verilog module) and the Specman foreign entity.

xor.v Behavioral XOR model written in Verilog.

xor_verify.e Testing environment for the design, written in e.

The following irun command generates the Specman Verilog and VHDL stubs file,

loads the e file, invokes ncvlog to compile the Verilog files, invokes ncvhdl

to compile the VHDL files, and then invokes the elaborator and simulator. It is

not necessary to instantiate SPECMAN_REFERENCE in your VHDL code. The -top

option is required because the top-level unit is VHDL.

% irun xor.v xor_specman.vhd -snload xor_verify.e -top xor_top

Debugging HDL and e Code

If the design includes Specman e files, the -gui option will also invoke the

Specview GUI so that you can debug your e code. For example, the following

command invokes the simulator with both SimVision and Specview.

% irun -gui xor_verify.e xor.v xor_specman.vhd -top xor_top &

If you do not need to debug e code, you can invoke the simulator with only

SimVision by using the -nospecview option.

% irun -gui -nospecview xor.v xor_verify.e

To invoke the Specview GUI without SimVision, use the -specview option.

% irun -specview xor.v xor_verify.e