Cadence® SPB: What’s New in 16.6 QIR 4 (HotFix 16) · Cadence SPB: What's New in 16.6 Quarterly...

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4

Cadence® SPB: What’s New in 16.6 QIR 4 (HotFix 16)

This document describes the new features and enhancements in Cadence® SPB products in 16.6 Quarterly Incremental Release (QIR) 4. The products covered are:

■ Allegro® PCB Editor

■ Cadence® SiP Layout and Allegro® Package Designer (APD)

■ Allegro® Design Entry HDL

■ Allegro® FPGA System Planner

■ OrCAD® Capture

■ Cadence® PSpice®

■ Allegro® Sigrity®

September 2013 9 Product Version 16.6

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4Allegro® PCB Editor

Allegro® PCB Editor

This document describes the new features and enhancements in Allegro PCB Editor16.6 QIR 4.

■ Step Model Viewing Enhancements on page 11

■ Route Interconnect Optimization on page 14

■ IPC2581 Enhancements on page 17

■ Productivity Enhancements on page 17

■ RF PCB Enhancements on page 20



Step Model Viewing Enhancements

The 3D viewer of Allegro PCB Editor has the capability of viewing footprint and mechanical models in more detail by use of STEP model mapping. This capability allows you to assign a Primary and Secondary STEP model to a footprint through use of a mapping tool at library creation or with the board drawing.

When the 3D viewer is launched, the STEP models are displayed showing a higher level of detail, dependent upon the data contained within the STEP model.

Primary and Secondary models allow the use of different versions of a STEP model based on detail or mounting variation. External mechanical STEP models, such as frames, housing, and so on, can also be mapped. They can be mapped within the board drawing without the requirement of creating and placing board symbol from the library.



PCB designers get a more realistic view of the design in the 3D view using the combination of STEP models for footprint packages and mechanical enclosures. The issues can be observed and resolved earlier in the design process.

Allegro STEP Export

Allegro PCB Editor provides the ability to export an Allegro PCB design as a STEP model. Exporting an Allegro design as a STEP model provide graphical description of the board as 3D data. This data can be imported into a mechanical tool to verify the design in it’s 3D simulated environment.



Export options include Board only, Board and mounting holes, External copper, components with and without STEP models, secondary STEP models, mechanical enclosure, and highlighted symbols only.

A workshop for STEP model mapping, viewing and export is available in the Allegro SPB tools install $CDSROOT/share/pcb/step directory.



Route Interconnect Optimization

A major effort targeted at improving the productivity and efficiency aspects of the interactive routing environment continues into the post 16.6 Quarterly Incremental Releases.

■ Allegro Timing Environment (High Speed Product Option)

Allegro Timing Environment (High Speed Product Option)

Introduced over the last several QIRs as unsupported prototypes, the ATE suite of features are now available.

The ATE suite includes:

Timing Vision

Timing Vision is an environment that allows you to graphically see real-time delay and phase information directly on the routing canvas. Traditionally, evaluating timing/length related issues required numerous trips to Constraint Manager and/or use of the Show Element command to evaluate the DRC condition. The new Timing Vision environment uses special



graphic techniques such as: custom cline coloring; stipple patterns and customized data tip information to define the delay problem in the simplest terms possible.

Menu Path

Route – Timing Vision

Figure 1-1 Interface constrained routes in Timing Vision Mode

Auto-Interactive Phase Tune (AiPT)

With an ever increasing amount of Differential Pairs associated with current Interface protocols, design tools need to be enhanced to support the requirements related to tuning and matching. Allegro PCB Editor currently supports very good interactive tools (delay tune and phase tune) to perform tuning on selected Diff Pairs or stand-alone nets. The increase in Diff Pair quantity has made is necessary to introduce an auto-interactive method to perform tuning across all Diff Pairs associated with a group or Interface.

Auto-interactive Phase Tuning works with a set of parameters that allows several options for trace lengthening or shortening.



Menu Path

Route – Auto-interactive Phase Tune

Figure 1-2 Timing Vision/Phase compensation at gathering point

Auto-Interactive Delay Tuning (AiDT)

Auto-interactive Delay Tuning is the third step in the ATE flow. It lessens the time to meet timing constraints on advanced standards-based interfaces, such as DDR3, by 30-50 percent. AiDT allows users to rapidly adjust the timing of critical high-speed signals on an interface-by-interface basis, or apply it at byte-lane level, reducing the need to tune the traces on a PCB from days to hours. Users can interactively select clines or cline segments for tuning then AiDT computes the required length for the selection set to meet timing constraints. The application utilizes controlled push/shove techniques while adding tuning patterns based on user guided parameters.

Menu Path

Route – Auto-interactive Delay Tune



IPC2581 Enhancements

■ Shorted Nets: Nets shorted by the NET_SHORT property will be exported to the element <PhyNetPoint> as a comment.

■ BOM populate support: If the property BOM_IGNORE is set to a component instance, Allegro PCB Editor will export <RefDes name = "***" populate = "FALSE"/> under <BomItem> in the IPC2581 output file.

■ Old style flash symbols: IPC2581 will now support the output of old style flash symbols on negative layers. An error is reported if Allegro PCB Editor cannot find the .bsm file referenced in the padstack.

■ RF Super Net Names: Currently in Allegro PCB Editor, the actual RF net is broken into multiple point to point nets. These different nets appear to be shorted together but properties inhibit DRC errors. When this connectivity is sent to a CAM CAD system, these shorted nets generate multiple errors. In these cases, Allegro PCB Editor creates a super net that combines all these nets and their member elements into a single net.

A super net is created when the following conditions are met:

❑ The design must have RFPCB elements!

❑ A net has one or more of its shape or pin elements containing the NET_SHORT property.

❑ The value of the NET_SHORT property starts with RFETCH.

If these cases are met, the net name is replaced with name RFETCH. All members of the net (pins, vias, clines and shapes) also report this as their net name.

Productivity Enhancements

■ Voids in Keepout Shapes

■ Artwork Control Form update

■ Allegro PDF Publisher

■ Relative Snapping

■ Ref-Des Layer Visibility Control

■ Dynamic Shapes

■ Testprep – Add Scan and Highlight update



Voids in Keepout Shapes

User defined voids are now permitted in Package, Route, and Via Keepout Shapes and No Probe Areas. The following restrictions apply:

■ The auto-routers will treat the keepout areas as solid shapes; voids are not recognized.

■ The IDF standard does not support voids in keepout shapes. IDF will continue to output just the shape outline. Customers who need to transfer these voids should consider migrating to the IDX MCAD-ECAD standard.

Artwork Control Form update

A new field, PDF Sequence has been added to the artwork control form. This allows the user to control the order of films in PDF output. Allegro will auto-number the films but the user can override the order. If two films share the same sequence number, alphabetical ordering will be used.

Allegro PDF Publisher

New options Filter Header/Footer and Filter Drawing Origin are available in the PDF Export form. (File – Export – PDF)



Relative Snapping

A new Snap pick to option permits a selected object to be offset from the specified position.

Ref-Des Layer Visibility Control

When moving a symbol, the default ref-des display is based on assembly-text. A new user preference variable, display_refdes_subclass allows the user to specify a preferred display layer for refdes text; (assembly, silkscreen or display). Variable is located in the User Preference Editor – Display – General folder.

Dynamic Shapes

The VOID_SAME_NET property has been extended to support the overlapping of same net shapes.



Testprep – Add Scan and Highlight update

Allegro now remembers the already scanned nets so not to reprocess them on subsequent runs.

RF PCB Enhancements

In this release, several enhancements have been made in RF PCB to increase productivity.

■ Layout Enhancements

■ Autoplace Enhancements

■ Discrete Library Translator Enhancements

■ Miscellaneous Enhancements

Layout Enhancements

This module includes the enhancements in the following commands:

■ Modify Connectivity

■ Enhanced Grouping Functionality



Modify Connectivity

The rf_modify_net command is enhanced to support swapping of nets on the pins of an RF component with autoshove functionality.

Enhanced Grouping Functionality

In this QIR, the RF group commands are improved as follows:

■ Group – Add: create a generic group and adds components to it. A warning is displayed if the generic group with the same name already exists. An option is provided to merge the groups.

■ Group – Disband: disband the generic group as well. You can also select the group to disband by clicking on the design canvas.

■ Group – Exclude: exclude the selected components from the generic group as well.

Group – Display: display a warning if any component is added to the generic group.

Autoplace Enhancements

■ Add Module Support

■ Enhanced Fix Placed Symbol Functionality



Add Module Support

This release removes the limitation of module placement using autoplace command. The autoplace functionality:

■ now supports placement of unplaced modules before autoplacement of RF components.

■ continues autoplacement even if some modules are not placed.

■ does not display the components that are contained in a module in any of the groups in the autoplacement UI

Enhanced Fix Placed Symbol Functionality

The Fix placed symbol has changed to Fix selected symbol/pin.

It is now easier to pick a symbol/pin for autoplacement of a group. When Fix selected symbol/pin is checked, the placed components are displayed with pin numbers.



You can now choose the symbol/pin from the design canvas as a start point using new RMB options.

Note: If this option is checked, the Enable relative rotation for non RF is disabled.



Discrete Library Translator Enhancements

A global option is added to the Allegro Discrete Library to Agilent ADS Translator. This option specifies the schematic version of the symbols for translation.

Miscellaneous Enhancements

■ Replicated block and module support

■ Support for Processing Unit Scale Factors and Tune Parameters

Replicated block and module support

■ You can now perform RF clearance initialization and assembly commands on the modules.

■ The rf_add_connect command is enhanced to support routing from the interface pin of a module.



Support for Processing Unit Scale Factors and Tune Parameters

Import IFF now supports processing of unit scale factors. The unit scale factors are defined in ADS and are used to define property value expressions or variable definition expressions.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4Cadence® SiP Layout and Allegro® Package Designer (APD)

Cadence® SiP Layout and Allegro® Package Designer (APD)

This section describes the new features and enhancements in SiP Layout and Allegro Package designer (APD) 16.6 QIR 4.

■ Displaying IC Details on page 27

■ 3D Viewer Enhancements on page 28

■ Aligning Selected Drivers while Editing on page 29

■ Preserving Existing Rat Bundles on page 30

■ Exporting Stack Level Information to the Wire Bond Configuration File on page 30

■ Adding the LOCKED Property to Via Structure Instances on page 31

■ Selecting Polygon Multi-Trace for Cline Change Width on page 31

■ New Display Modes for the dpn Command on page 32

■ Co-Design Die LOCKED Property Changes on page 32

■ Displaying Information in the Show Element Window for Co-Design Dies on page 32

■ Picking a New Cell Master on page 32

■ Synchronizing IC and Package Net Names for Co-design Dies on page 33

■ Applying Pin Background Color to Nets on page 34

■ NA2/SPD2 Enhancements on page 35



Displaying IC Details

In 16.QIR 4 you can view details – such as drivers, RDL routings, and shapes – of IC components. You can then hide the visible read-only structures. To be able to access the Show IC Details (View Only) pop-up option, set the symed_ic_details variable under Early_adopter in the Ic_Packaging category of the User Preferences Editor.

The IC details are shown as shapes on the following Component Geometry classes and subclasses:

■ Drivers and driver pins: Component Geometry / Drivers

■ RDL routing: <layername>_Rdl

Example: RDL routing on the layer Metal8 will appear on subclass Metal8_Rdl

■ Shapes: SHAPE elements in the die abstract contain a LAYER element, so that layer will show up as a subclass, <layername>_Shape

Example: A shape on a layer LOGO will appear on a subclass LOGO_Shape

Based on the objects you want to see as read-only structures on a selected die component, you can set one or more of the following environment variables in the Early_adopter category under Ic_packaging:

You can view the IC details of more than one die in a design; for example, you might want to show to the details of a co-design die and refer to its structure while editing another die in your design.

symed_ic_details_drivers Set to see a read-only view of the I/O drivers on a selected die component.

symed_ic_details_routing Set to see a read-only view of the RDL routing on a selected die component.

symed_ic_details_shapes Set to see a read-only view of the IC shape objects on a selected die component.



3D Viewer Enhancements

■ Viewing Nets within Selected Regions

■ Viewing Pre-Selected Objects

Viewing Nets within Selected Regions

You can now window around a region in a design and view selected nets within the region in the 3D Viewer. A new option Nets has been added to enable net selection within a Window. The option is available in the 3D Viewer Design Configuration dialog box.



Viewing Pre-Selected Objects

You can launch 3D Viewer directly without displaying the configuration dialog box by selecting items in the design and then choosing 3D Model from the View menu. 3D Viewer will show only the selected items.

Aligning Selected Drivers while Editing

You can now align a group of selected drivers while in the die editor environment. The group maintains relative positions. To enable this functionality, select the Align as group option in the die editor form when in the align driver mode.



Preserving Existing Rat Bundles

You can preserve existing rat bundles in the optimize mode of the auto assign net command.

The bundles are preserved within the command for the Nearest Match and Router Based algorithms.

Note: Ensure that Invoke route feasibility on results is not selected under Routing options.

Exporting Stack Level Information to the Wire Bond Configuration File

The wire bond configuration (.wbt) file created on exporting wire bonds now contains stack level for wire starts and ends that connect to a die stack object such as a wire bond die's pins or an interposer's finger pads.

The stack level is the offset in the die stack of the die or interposer that the bond wire connects to at the end.

<wire>

<profile>PROFILE1</profile>



<diameter>25.4 UM</diameter>

<wire_start>

<loc_x>4655.27 UM</loc_x>

<loc_y>4354.93 UM</loc_y>

<stack_level>1</stack_level>

</wire_start>

<wire_end>

<loc_x>8300 UM</loc_x>

<loc_y>5111.43 UM</loc_y>

</wire_end>

</wire>

Adding the LOCKED Property to Via Structure Instances

You can now set the via_struct_auto_lock variable under Ic_packaging in the User Preferences Editor to add the LOCKED property to via structure instances placed using the add via structure (Route – Via Structure – Add) command. The LOCKED property prevents unintended changes to the placed instances.

Selecting Polygon Multi-Trace for Cline Change Width

When using the cline change width (Edit – Cline Change Width) command, you can now select a polygon region for multi-trace in addition to window-based.



New Display Modes for the dpn Command

The dpn (Manufacture – Documentation – Display Pin Text) command now has two additional display modes, Die Port Name and Package Port Name.

Co-Design Die LOCKED Property Changes

Now, co-design dies are not locked when placed. You can lock them by choosing Edit – Properties – LOCKED. You can also remove the LOCKED property from a co-design die.

In the Symbol Edit application mode, if you right-click on a locked co-design die, you will be prompted to either retain the lock or unlock the die.

Displaying Information in the Show Element Window for Co-Design Dies

In the Die Editor, now you can click Show Elem and then pick, window, or temp-group objects on the canvas to display information about the selected objects in the Show Element window.

Show Elem should not be used to get information on the individual pins and drivers of a die, as the die has been exploded while in the die editor.

Picking a New Cell Master

When modifying a pin, now you can select the new LEF macro field on the Pins tab of die editor in distributed co-design to be able to pick a new cell master. Picking a new cell master



does not impact the package padstack representing the landing site for the ball on the package substrate.

Note: Bump master changes are supported only by Virtuoso.

Synchronizing IC and Package Net Names for Co-design Dies

The new Synchronize IC and Package nets option for the die properties command (Edit – Die Properties) synchronizes IC and package net names of a co-design die. This option is equivalent to the Import net assignments option of the Place Co-Design Die dialog box of the add codesign die command. The selection state of the Synchronize IC and Package nets option reflects the Import net assignments option.



Applying Pin Background Color to Nets

When you import a spreadsheet using the symbol from spreadsheet (File – Import– Symbol Spreadsheet) command, a new option Assign cell colors to nets applies the background color of an imported pin to the net as a custom color highlight in the design.

The option is not selected by default and is available only if you select XML as File type.



NA2/SPD2 Enhancements

The na2 import (File – Import – SPD2/NA2) has been enhanced to import Artwork layers.

The following table lists the mapping of UPD (.spd2) layers to APD and SiP layers.

UPD SiP/APD

CLASS SUBCLASS CLASS SUBCLASS

ARTWORK BODYOUTLINE SUBSTRATE GEOMETRY

OUTLINE

ARTWORK BOTTOMSOLDERMASK SUBSTRATE GEOMETRY

SOLDERMASK_BOTTOM

ARTWORK BOTTOMSOLDERPASTE COMPONENT GEOMETRY

PASTEMAST_BOTTOM

ARTWORK CONSTRAINTAREAS CONSTRAINT REGIONS

ALL

ARTWORK RULER DRAWING FORMAT

ARTWORK TOPSOLDERMASK SUBSTRATE GEOMETRY

SOLDERMASK_TOP

ARTWORK TOPSOLDERPASTE COMPONENT GEOMETRY

PASTEMAST_TOP

DIELECTRIC BOTAIR CONDUCTOR OUTLINE

DIELECTRIC DIELECTRIC2 CONDUCTOR DIEELECTRIC2

DIELECTRIC TOPAIR DIELCTRIC

DIELELECTRIC DIELECTRIC1 CONDUCTOR DIELECTRIC1

JUMPER WBOND DIE/DIESTACK WIREBOND

SIGNAL BOTTOM CONDUCTOR BOTTOM

SIGNAL M1 CONDUCTOR M1


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4Allegro® Design Entry HDL

Allegro® Design Entry HDL

This section describes the new features and enhancements in Allegro Design Entry HDL 16.6 QIR 4.

■ Hierarchical Split Symbols

■ Page Setup Options in Design Publisher

Hierarchical Split Symbols

Large hierarchical block symbols can become difficult to manage because of the substantial number of pins coming out of a single symbol. Allegro Design Entry HDL now provides a solution to manage large hierarchical block symbols by splitting them into multiple split symbols. Therefore, instead of generating one difficult-to-manage large symbol, you can now split the ports of a hierarchical block across multiple symbols. This support for hierarchical split symbols reduces the size of the block symbol.

For more information, refer to Working with Hierarchical Split Symbols in Allegro Design Entry HDL User Guide.

Page Setup Options in Design Publisher

The Allegro Design Publisher solution now provides support for specifying page setup options, such as measurement unit, page size, orientation, margins, and scaling factor at the time of generating a PDF document. This functionality is available from the UI as well as the command line.

For more information, refer to Allegro Design Publisher User Guide.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4Allegro® FPGA System Planner

Allegro® FPGA System Planner

This section describes the new features and enhancements in Allegro FPGA System Planner16.6 QIR 4.

■ The Design Connectivity Window on page 38

■ The Properties Window on page 39

■ The Power Connections Window on page 39

■ Cross-Probing between the Windows on page 39

■ The Synthesis Failure Report window on page 40

■ Accessing TCL Help on page 40

■ Configuring Menus and Toolbars on page 41

■ Enhanced Swap Group Function for Design Connectivity on page 41

■ Enhanced External Ports Function and New Internal Hard Connection Type on page 42

■ Enhancements in the Preferences window on page 43

■ GUI Enhancements on page 43



The Design Connectivity Window

In the current release, FSP provides you a new design environment, Design Connectivity window that helps you to edit the design in a spreadsheet-based view. The Design Connectivity window displays the complete design, that is, targeted connections to FPGAs, terminations, power connections, and properties, in a spreadsheet view. This view allows you to quickly capture or modify connectivity information in the design. You can also quickly work with the properties and constraints across your design. The Design Connectivity window is very effective for capturing designs with high pin count components and devices. In addition, the Design Connectivity window offers various context-sensitive menus and features which helps you work faster. These menus and features provides you capabilities to quickly connect component pins to signals, apply terminations and power regulators, and add and remove components.

Besides providing you the spreadsheet view interface, the Design Connectivity window also provides you multiple views to capture the design. These multiple views are categorized into different functional views. Each view represents the different aspects of the design information. For example, Pin View displays and lets you modify the design connections and details at instance pin level and Net View lets you to modify the connectivity information of various FPGA instances in the design.



The Design Connectivity window also provides:

■ Filter and search features

■ Export and import comma separated values (csv) data

For detailed information about the Design Connectivity window, see the Design Connectivity section in the Workspace chapter of the Allegro FPGA System Planner User Guide.

The Properties Window

In the current release, a new window is introduced, Properties. The Properties window lets you view and modify the properties of the instances, groups, banks, and pins in the design. The properties that appear in the Properties window depends on the items you select in the Design Connectivity window and on the Canvas. For example, if you click on a pin, the properties of the selected pin appear in the Properties window. When you modify the properties in the Properties window, the changes are immediately reflected in the Design Connectivity window and on the Canvas.

For detailed information about the Properties, see the Properties section in the Workspace chapter of the Allegro FPGA System Planner User Guide.

The Power Connections Window

In the earlier release, you define and map the power regulators using multiple windows. In the current release, the functionalities defining and mapping power regulators are merged and enhanced to a single window, Power Connections. The Power Connections window lets you define, add, delete, or reset the power connections in a project.

For detailed information about the Properties, see the Power Connections section in the Workspace chapter of the Allegro FPGA System Planner User Guide.

Cross-Probing between the Windows

In the earlier release, a large number of signals aliased to each other on the same instance or different instances present on the Canvas. This makes it difficult to quickly identify the signals and view their connectivity for debugging process.

The current release comes with the cross-probing functionality. The Design Connectivity window lets you quickly navigate the signals to view its connectivity on the Canvas. You can



select a net in the Design Connectivity window and view all synonyms of the selected net across the opened windows. This functionality is extended to the Canvas, Die View, and Synthesis Failure Report windows as well. For example, when you select a net, group, bank, pin, or instance on the Canvas, the details of the selected net or instance are displayed in the Design Connectivity and Die View windows.

The Synthesis Failure Report window

The current release brings you verbose synthesis failure report. The Synthesis Failure Report tab displays a detailed synthesis failure report for each of the failed interface or protocol connections. This failure report is displayed when you click on the Failed hyperlink against the interface pin under Status column in the Design Connectivity window. The Synthesis Failure Report lets you browse, view, and analyze the reasons for the failed connections.

The report is displayed in a tree view structure. You can expand or collapse the branches of the tree by clicking the + and - buttons beside them, respectively. The tree structure illustrates the contextual flow of the FSP synthesis engine. The contextual path of each message helps you understand the content under which the message was thrown.

For detailed information, see the Synthesis Failure Report section in the Workspace chapter of the Allegro FPGA System Planner User Guide.

Accessing TCL Help

To assist you learn FSP TCL commands, the current release provides you complete details about each of the TCL commands in FSP.

You can use the syntax <command> -help to access more help about the specified command. For example, type addnet -help and press Enter. The help provides the complete detail about the specified command, such as description, syntax, brief explanation of the command arguments, and examples if any.

Important

You can also find the complete detail about all FSP’s TCL commands in the FSP TCL Command Reference guide.



Configuring Menus and Toolbars

In the current release, significant enhancements have been made in the toolbars and menu bar to provide you an improved usability experience.

You can now customize the toolbars in FSP, using the Customize Toolbar dialog box. You can rearrange the location of the toolbar icons within the toolbar strip. You can group the icons based on their usage and separate the groups using separator. You can also undock the toolbar and reposition it in your workspace.

The following section lists the enhancements made to the FSP menu bar and toolbar.

■ In the Design menu, the Reset Specify Net Name command name is renamed to Clear Cached Net Names.

■ The Define External Ports dialog box is no longer supported through the Tools menu. You can now directly specify the external and internal ports in the Design Connectivity window.

■ The Define Power Regulators and Define Power Mapping is merged into a single menu command, Power Connections.

■ All the windows such as Design Connectivity, Die View, and Properties that appears within the Canvas perimeter are now accessible through the Windows menu.

Enhanced Swap Group Function for Design Connectivity

In the earlier release, the interface’s groups were allowed to be swapped through an individual window. Moreover, the changes were immediately reflected on the Canvas.



In the current release, the earlier Swap Group dialog box is now optimized into a simple and intuitive window that is accessible through the context menu options in the Design Connectivity window. Now the changes can be observed in both the Canvas and Design Connectivity window.

Note: The swap group functionality remains unchanged.

Enhanced External Ports Function and New Internal Hard Connection Type

In the current release, defining external ports for routed and unrouted pins through the independent dialog box are no longer supported.

In the new implementation, the ports are now available as the following set of pre-defined values.

■ Fixed Internal Connections

■ Fixed External Port

■ Extend as External Port



■ Preserve Pin

■ Do Not Connect

These pre-defined values are available as a drop-down list in the cell(s) of Connection Type column in Design Connectivity window. The values are filtered and displayed based on the connections status of the pin. You can apply the ports to the individual pins by selecting them from the drop-down list.

Fixed Internal Connection Type

The fixed internal connection type is applicable for un-routed nets (or pins).

In this method of connection type, the pins are shorted together to form a single net with the same name.

Enhancements in the Preferences window

The following enhancements have been made in the Preferences window.

■ Two new options, Highlight Pins marked as Do Not Connect (or preserve) on canvas or Use Group or bank color to draw nets on canvas are appended to the list of Misc Settings section in Display tab.

■ The confirmation dialog settings options are now available in Design tab.

GUI Enhancements

Several minor enhancements have been made in the current release of FSP.

■ The Group Settings for interfaces and Bank Settings for devices are now available as independent windows.



■ The pattern generator toolbar order is revised. In addition, a new info icon is added to the toolbar. The info icon provides more information about each toolbar options.

Note: The Pattern Generator feature is a graphical solution to define pin types on the single ended pins and differential pair pins of the connector.

■ A new Manage Protocol window is introduced in Design Connectivity. The Manage Protocol window lets you manage the protocol creation.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4OrCAD® Capture

OrCAD® Capture

This section describes the new features and enhancements in OrCAD Capture 16.6 QIR 4.

Capture 16.6 QIR4 brings you the following new features:

■ Mechanical Parts in Capture - Allegro Flow on page 46

■ Enhancements in Display Properties dialog box on page 47

■ Enhancement in Comment Text on page 48

■ Capture Viewer on page 48

■ Capture - Sigrity SI flow license on page 49

■ Miscellaneous Enhancements on page 49



Mechanical Parts in Capture - Allegro Flow

From 16.6 QIR4 onwards, you can include a zero pin mechanical part, such as bar codes, mechanical holes, and fiducials, in Capture - Allegro flow. These parts should have CLASS=MECHANICAL property.



Enhancements in Display Properties dialog box

In Capture, Display Properties dialog box has a new Display format called Value if Value Exists, which displays value only if value exists.

The new display format can be used for those properties where the name should not be visible. For example, now a tolerance property could be specified using Value if Value Exists display format, which ensures that only tolerance value is displayed, if it exists.



Enhancement in Comment Text

From 16.6 QIR4 onwards, a comment text in Capture can be netlisted to PSpice by adding @PSpice: at the start of the comment.

Note: The comment directive(s) should only be used on the top level page of the design. Also only for those parameters, which are not added using PSpice Setup.

Capture Viewer

Using Capture Viewer you can now view Capture design files as read-only. To view Capture design files as read-only, enter capture -viewer on the command prompt. Capture Viewer does not checkout any license. Capture Viewer is different from OrCAD Lite as it does not limit the size of the design being viewed.



Note:

■ No CIS data is viewable using Capture Viewer.

■ Before executing Capture Viewer command on command prompt, ensure that Capture is not running.

Capture - Sigrity SI flow license

From 16.64 QIR onwards, you can invoke Signal Explorer from Explore Signal menu, in Capture, to run Sigrity SI using PA7500 license.

Miscellaneous Enhancements

■ Accelerator Support on page 49

■ Double quotes support in part references of variant.lst on page 50

■ Enhancements in Capture INI Manager on page 50

Accelerator Support

In TCL Interface, accelerator support has been added for user added menus. For more information, see TCL API Guide.



Double quotes support in part references of variant.lst

In SKILL, now text without double quotes, such as TP850-1 is intrerpreted as list, not as string. This can be implemented using this TCL command:

SetOptionString ExportQuotedRefDesVariant = TRUE

Enhancements in Capture INI Manager

Capture INI Manager, a downloadable utility in OrCAD Marketplace, now supports color settings in .ini file.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4Cadence® PSpice®

Cadence® PSpice®

This section describes the new features and enhancements in Cadence PSpice 16.6 QIR 4.

■ Expression support in .TRAN, .OPTIONS, and .FOUR commands on page 52

■ Parameter support in .PROBE command on page 52

■ New Convergence options in .OPTIONS command on page 52

■ TCL Functions support in circuit file on page 54

■ Ignore DML check in IBIS2Spice on page 54

■ Global Parasitic Support on page 55

■ Enhancements in Learning PSpice on page 54

■ Frequency Response Analysis on page 56

■ Documentation Enhancements on page 57



Expression support in .TRAN, .OPTIONS, and .FOUR commands

Expression support is provided for the following commands:

■ .TRAN - for TSTART, TSTEP, and TSTOP

■ .FOUR - for fundamental frequency

■ .OPTIONS - for MINSIMPTS

Note: For more information, see FRA example at <Installation>\tools\pspice\capture_samples\anasim\fra.

Parameter support in .PROBE command

In PSpice, you can now add parameter, defined using .PARAM command, in .PROBE command, such as .PROBE64 P(FREQ).

For more information, see FRA example at <Installation>\tools\pspice\capture_samples\anasim\fra.

Note: This is may be added as PSpice Directive in Capture Schematic using comment text.

New Convergence options in .OPTIONS command

You now have following new convergence options available in .OPTIONS command:

■ PREORDERMODE option

■ MINSIMPTS option

■ RMIN option

■ BPPseudoTran option

■ TRANCONV1 option

PREORDERMODE option

PSpice SOLVER = 1 uses PREORDER only once in the simulation, that is, at the start of the simulation. But now by enabling PREORDERMODE option, PREORDER gets executed in every simulation iteration.



Using PREORDERMODE option improves accuracy and convergence properties of the simulation server.


MINSIMPTS option

Using MINSIMPTS you can override default 50 time points for any given TSTOP value. This option allows user to control minimum points that must be executed in a simulation run. For example, setting MINSIMPTS=1000 ensures that at least 1000 points are generated at equal timestep (The simulator may take a shorter timestep for accuracy reasons).

MINSIMPTS option is useful if expression is used for TSTOP and if transient analysis data is required for post-processing of algorithms, such as Fourier Analysis.

For more information, see FRA example at <Installation>\tools\pspice\capture_samples\anasim\fra.

RMIN option

PSpice implements an internal minimum timestep (delta) value, which if reached can result in convergence failure, but now RMIN allows user to override the minimum timestep value.

When used with other transient convergence options, a higher RMIN value can improve performance depending upon the circuit. The higher RMIN value forces the simulator to move to different convergence continuation methods rather than going to lower Delta value. A lower RMIN value may resolve some convergence issues as well.

BPPseudoTran option

A Biaspoint convergence may be slow due to absence of capacitors and indictors from the circuit, such as circuits using behavioral elements. BPPseudoTran option forces PSpice simulator to use PseudoTran algorithm instead of regular biaspoint algorithm.


TRANCONV1 option

This option enables an internal continuation method to fix convergence failure during transient analysis.



TCL Functions support in circuit file

Now PSpice allows execution of TCL script from PSpice Engine. PSpice supports the following TCL function:

■ .TCLPOSTRUN command

.TCLPOSTRUN command

This command is called after simulation and using TCL file any operation can be performed after simulation, such as post-processing of the DAT file. An example for .TCLPOSTRUN command is .TCLPOSTRUN postrun.tcl.

Note: .TCLPOSTRUN command may be added as PSpice Directive in Capture Schematic using comment text.

Ignore DML check in IBIS2Spice

For orPSpiceParsers, a new parameter, -skipDMLCheck has been added to ignore DML check errors while generating output file from IBIS file.

Enhancements in Learning PSpice



A new book called Power Electronics Design Examples is available in Learning PSpice. This new book explains Single Switch Forward Converter using a design example, which can be simulated using PSpice and taken to PCB layout.

Note: You can access Learning PSpice in Capture - PSpice flow only. To access Learning PSpice, choose Help- Learning PSpice in Capture.

Global Parasitic Support

New parameters have been added in .OPTIONS command to support parasitic globally for devices:

■ Junction Gate Field-Effect Transistor Capacitance (JFETCJ)

❑ gate-to-source capacitance (Cgs)

❑ gate-to-drain capacitance (Cgd)

■ Metal–Oxide–Semiconductor Field-Effect Transistor Capacitance (MOSCJ)

❑ gate-to-source overlap capacitance (Cgso)

❑ gate-to-drain overlap capacitance (Cgdo)

❑ zero-bias bulk-to drain junction capacitance (Cbd)

❑ zero-bias bulk-to-source junction capacitance (Cbs)

❑ zero-bias bulk junction bottom capacitance (Cj)

❑ zero-bias bulk junction sidewall capacitance (Cjsw)

Also, Bipolar Junction Transistor Capacitance (BJTCJ) has been enhanced with zero-bias collector substrate capacitance (Cjs).

For more information, see PSpice Reference Guide.



Frequency Response Analysis

In PSpice, you can now perform frequency response analysis to get frequency response of the non-linear switching circuits having varying operating point.

RA is an open-source application and TCL program in FRA is provided to:

■ Develop HTML5 GUI with PSpice

■ Access transient analysis data from DAT file

■ Use TCL interpolate functions to get equidistant points from transient analysis data

■ Perform fourier analysis in TCL

■ Create a PSpice DAT file for frequency response using TCL, to view in Probe

Note: To enable Frequency Response Analysis, choose Tools - FRA in PSpice.



Documentation Enhancements

This release has the following documentation enhancements:

■ New Tutorial: Simulating an SMPS Design using Capture-PSpice Flow

■ Reorganization of Content: Co-Simulation using PSpice SLPS Interface

New Tutorial: Simulating an SMPS Design using Capture-PSpice Flow

A new tutorial walks you through OrCAD® Capture - PSpice flow using an Switched Mode Power Supply (SMPS) design. In this tutorial, you will configure the design for simulation, simulate the design using PSpice, and then use Advanced Analysis to verify stability and yield of the design.

Reorganization of Content: Co-Simulation using PSpice SLPS Interface

Content has been reorganized to create a tutorial that walks you through the various steps to perform co-simulation using the PSpice SLPS Interface using the example of an electronic cruise system.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 4Allegro® Sigrity®

Allegro® Sigrity®

This section describes the new features and enhancements in Allegro Sigrity 16.6 products aligned with Cadence SPB 16.6 QIR 4.

■ New Product: Allegro Sigrity PI (PA5800)

New Product: Allegro Sigrity PI (PA5800)

Allegro Sigrity PI is a new product (PA5800) for PI analysis of Allegro PCB, IC Package, and SiP designs. It features:

■ A layout editor for floorplanning, editing, and routing

■ Integrated Sigrity technology for DC Analysis featuring cross-probing between the analysis results and the floorplanner

■ A new Power Feasibility Editor (PFE) to drive the creation of PI Constraint Sets.

The PFE allows you to select and analyze a set of capacitors to create a de-coupling strategy for a particular device. This strategy is then captured as a PICSet which is then passed back to the design and can be managed in Constraint Manager.

■ A new DeCap Place command to provide placement guidance for placing capacitors based on the PICSet


Cadence® SPB: What’s New in 16.6 QIR 4 (HotFix 16) · Cadence SPB: What's New in 16.6 Quarterly...

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