CA1524, CA3524 Datasheet - Intersil Frequency of Operation Beyond 100kHz • Variable-Output Dead...

FN1239 Rev.4.00 of 16October 2000

FN1239Rev.4.00

October 2000

CA1524, CA2524, CA3524Regulating Pulse Width Modulator

DATASHEET

Features

• Complete PWM Power Control Circuitry

• Separate Outputs for Single-Ended or Push-PullOperation

• Line and Load Regulation . . . . . . . . . . . . . . . 0.2% (Typ)

• Internal Reference Supply with 1% (Max) Oscillator and Reference Voltage Variation Over Full Temperature Range

• Standby Current of Less Than 10mA

• Frequency of Operation Beyond 100kHz

• Variable-Output Dead Time of 0.5s to 5s

• Low VCE(sat) Over the Temperature Range

Applications

• Positive and Negative Regulated Supplies

• Dual-Output Regulators

• Flyback Converters

• DC-DC Transformer-Coupled Regulating Converters

• Single-Ended DC-DC Converters

• Variable Power Supplies

Description

The CA1524 and CA3524 are silicon monolithic integratedcircuits designed to provide all the control circuitry for use ina broad range of switching regulator circuits.

The CA1524 and CA3524 have all the features of the indus-try types SG1524, SG2524, and SG3524, respectively. Ablock diagram of the CA1524 series is shown in Figure 1.The circuit includes a zener voltage reference, transconduc-tance error amplifier, precision R-C oscillator, pulse-widthmodulator, pulse-steering flip-flop, dual alternating outputswitches, and current-limiting and shutdown circuitry. Thisdevice can be used for switching regulators of either polarity,transformer-coupled dc-dc converter, transformerless volt-age doublers, dc-ac power inverters, highly efficient variablepower supplies, and polarity converter, as well as otherpower-control applications.

PinoutCA1524, CA3524 (PDIP, CERDIP)

TOP VIEW

Ordering Information

PART NUMBER

TEMPERATURE RANGE PACKAGE

CA1524E -55oC to +125oC 16 Lead Plastic DIP

CA1524F -55oC to +125oC 16 Lead CerDIP

CA2524E 0oC to +70oC 16 Lead Plastic DIP

CA2524F 0oC to +70oC 16 Lead CerDIP

CA3524E 0oC to +70oC 16 Lead Plastic DIP

CA3524F 0oC to +70oC 16 Lead CerDIP

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

CT

RT

VREF

EMITTER B

COLLECTOR B

COLLECTOR A

EMITTER A

SHUTDOWN

INV. INPUT

OSC OUT

GND

(-) C.L.SENSE

(+) C.L.SENSE

V+

COMPENSATIONAND COMPARATOR

NON-INV. INPUT

CA2524 IS AN OBSOLETE

PRODUCT

CA1524, CA2524, CA3524

Functional Block Diagram

Test Circuit

REFERENCEREGULATOR

5V

FLIP

OSCILLATOR

COMPARATOR

INV. INPUT

NON-INV.INPUT

ERRORAMP

SHUTDOWN

GND

16

15

3

6

7

1

2

10

8

FLOP

+5V

+5V TO ALLINTERNAL CIRCUITS

+5V

-

+

+5V

+5V

C.L.

+5V

+

-

10k

1k9

5

4

COMPENSATION AND COMPARATOR

- SENSE

+ SENSE

12

11

SA

EA

CA

13

14

SB

EB

CB

CT

RT

OSC OUT

VREF

V+

12

13

11

14

5410912768

16

15

3

ls

CA1524

V+

8 - 40V

0.1F RT CT

2k

10k

1k

10k

2k

2k

2k1W

2k1W

OUT A

OUT B


CA1524, CA2524, CA3524

Absolute Maximum Ratings Thermal Information

Input Voltage (Between VIN and GND Terminals) . . . . . . . . . . . .40VOperating Voltage Range (VIN to GND). . . . . . . . . . . . . . . . 8 to 40VOutput Current Each Output:

(Terminal 11, 12 or 13, 14). . . . . . . . . . . . . . . . . . . . . . . . . 100mAOutput Current (Reference Regulator). . . . . . . . . . . . . . . . . . . 50mAOscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Thermal Resistance JAPlastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W

Device DissipationUp to TA = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25WAbove TA = +25oC. . . . . . . . . . . . . . . Derate Linearly at 10mW/oC

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oCStorage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oCLead Temperature (During Soldering)

At distance 1/16 in. (1.59mm 0.79mm)from case for 10s Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and

f = 20kHz, Unless Otherwise Stated.

PARAMETER TEST CONDITIONS

CA1524, CA2524 CA3524

UNITSMIN TYP MAX MIN TYP MAX

REFERENCE SECTION

Output Voltage 4.8 5 5.2 4.6 5 5.4 V

Line Regulation V+ = 8 to 40V - 10 20 - 10 30 mV

Load Regulation IL = 0 to 20mA - 20 50 - 20 50 mV

Ripple Rejection f = 120Hz, TA = 25oC - 66 - - 66 - db

Short Circuit Current Limit VREF = 0, TA = 25oC - 100 - - 100 - mA

Temperature Stability Over Operating Temperature Range

- 0.3 1 - 0.3 1 %

Long Term Stability TA = 25oC - 20 - - 20 - mV/khr

OSCILLATOR SECTION

Maximum Frequency CT = 0.001F, RT = 2K - 300 - - 300 - kHz

Initial Accuracy RT and CT Constant - 5 - - 5 - %

Voltage Stability V+ = 8 to 40V, TA = 25oC - - 1 - - 1 %

Temperature Stability Over Operating Temperature Range

- - 2 - - 2 %

Output Amplitude Terminal 3, TA = 25oC - 3.5 - - 3.5 - V

Output Pulse Width (Pin 3) CT = 0.01F, TA = 25oC - 0.5 - - 0.5 - s

Ramp Voltage Low (Note 1) Pin 7 - 0.6 - - 0.6 - V

Ramp Voltage High (Note 1) Pin 7 - 3.5 - - 3.5 - V

Capacitor Charging Current Range Pin 7 (5-2 VBE)/RT 0.03 - 2 0.03 - 2 mA

Timing Resistance Range Pin 6 1.8 - 120 1.8 - 120 k

Charging Capacitor Range Pin 7 0.001 - 0.1 0.001 - 0.1 F

Dead Time Expansion Capacitor on Pin 3 (when a small osc. cap is used)

Pin 3 100 - 1000 100 - 1000 pF

ERROR AMPLIFIER SECTION

Input Offset Voltage VCM = 2.5V - 0.5 5 - 2 10 mV

Input Bias Current VCM = 2.5V - 1 10 - 1 10 A

Open Loop Voltage Gain 72 80 - 60 80 - dB

Common Mode Voltage TA = 25oC 1.8 - 3.4 1.8 - 3.4 V


CA1524, CA2524, CA3524

Common Mode Rejection Ratio TA = 25oC - 70 - - 70 - dB

Small Signal Bandwidth AV = 0dB, TA = 25oC - 3 - - 3 - MHz

Output Voltage TA = 25oC 0.5 - 3.8 0.5 - 3.8 V

Amplifier Pole - 250 - - 250 - Hz

Pin 9 Shutdown Current External Sink - 200 - - 200 - A

COMPARATOR SECTION

Duty Cycle % Each Output On 0 - 45 0 - 45 %

Input Threshold Zero Duty Cycle - 1 - - 1 - V

Input Threshold Max. Duty Cycle - 3.5 - - 3.5 - V

Input Bias Current - 1 - - 1 - A

CURRENT LIMITING SECTION

Sense Voltage for 25% Output Duty Cycle Terminal 9 = 2V with ErrorAmplifier Set for Max Out,TA = 25oC

190 200 210 180 200 220 mV

Sense Voltage T.C. - 0.2 - - 0.2 - mV/oC

Common Mode Voltage -1 - +1 -1 - +1 V

Rolloff Pole of R51 C3 + Q64 - 300 - - 300 - Hz

OUTPUT SECTION (EACH OUTUT)

Collector-Emitter Voltage 40 - - 40 - - V

Collector Leakage Current VCE = 40V - 0.1 50 - 0.1 50 A

Saturation Voltage V+ = 40V, IC = 50mA - 0.8 2 - 0.8 2 V

Emitter Output Voltage V+ = 20V 17 18 - 17 18 - V

Rise Time RC = 2K, TA = 25oC - 0.2 - - 0.2 - s

Fall Time RC = 2K, TA = 25oC - 0.1 - - 0.1 - s

Total Standby Current: (Note 2) IS V+ = 40V - 4 10 - 4 10 mA

NOTES:

1. Ramp voltage at Pin 7 where t = OSC period in microsecondst RTCT with CT in microfarads and RT in ohms.

Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency wheneach output is connected in parallel.

2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.

Electrical Specifications TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and

f = 20kHz, Unless Otherwise Stated. (Continued)

PARAMETER TEST CONDITIONS

CA1524, CA2524 CA3524

UNITSMIN TYP MAX MIN TYP MAX

High

Lowt


CA1524, CA2524, CA3524

Schematic Diagram

21

3

7

6

8

Q1

R1500

R51K

R71K

Q2 Q7 Q13

Q6

Q3 Q4

R22.7K

RC10K

R36.3K

Q10

Q11

D2D1

Q9 C120pF

R4500

R6500

Q5 Q12

RB4.8K

RA5.3K

QA

OSC SECTION

Q42 Q43

Q44

Q47 Q48

Q49 Q50

Q45

Q46

R391K

R4124K

R40560

R4219.8K

Q51

Q52

R4525K

R441.8K

R437.4K

Q53 Q54

Q55

R463.3K

OSC.OUT

Q59 Q60

Q61

Q56 Q57

INV.IN

ERRORAMP

NON-INV.INPUT

Q58 Q62

R471K

R482K

J

KL

FGHI

C

DE

Q24Q22Q20

R1525K

C220pF

N+ P

10K 1.9K

RD

Q19

R14450

Q14 Q15

R88.4K

R9500

R101K

Q17

Q18

R11500

R1210K

Q16

R136

15 VIN

C4

PULSESTEERINGFLIP-FLOP

B

A

R1616.2K

R1918.7K

R1718.7K

R1818.7

K

R1818.7

K

Q21 Q23

16

VREF

+5V

GND

RT

CT


CA1524, CA2524, CA3524

Schematic Diagram (Continued)

12

11

COLL. A

EMIT A

13 COLL. B

14 EMIT B

10 9

5 4

A

B

OUTPUT A

Q34

Q36

Q35R33200

R321K

R34500

CA1pF

R314.7 RE

500

Q33

OUTPUT B

Q40

Q37 Q38

D3 D4

Q39

RF500

R384.7

Q41

R35500

R371K

R36200

CB1pF

C

DE

R2143.3K

R255K

R245K

Q26

Q27

R238.7K

FG

HI

R265K

Q29

R275K

Q30

Q31

R3043.3K

R288.7K

NORNOR

R521.96K

R541.96K

Q65 Q67

J

COMP

R491K

R5010K

Q63

Q64

Q66

CURRENTLIMIT

SECTION

R5110K

R531.8K

C345pF

(-) C.L.SENSE

Q68 Q71

Q70Q68

Q73Q72

KL

COMPARATOR

(+) C.L.SENSE


CA1524, CA2524, CA3524

Circuit DescriptionVoltage Reference Section

The CAl524 series contains an internal series voltage regulatoremploying a zener reference to provide a nominal 5-volt out-put, which is used to bias all internal timing and control cir-cuitry. The output of this regulator is available at terminal l6and is capable of supplying up to 50mA output current.

Figure 1 shows the temperature variation of the reference volt-age with supply voltages of 8V to 40V and load currents up to20mA. Load regulation and line regulation curves are shown inFigures 2 and 3, respectively.

FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION OF AMBIENT TEMPERATURE

FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION OF REFERENCE OUTPUT CURRENT

FIGURE 3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION OF SUPPLY VOLTAGE

Osclllator Section

Transistors Q42, Q43 and Q44, in conjunction with an externalresistor RT, establishes a constant charging current into anexternal capacitor CT to provide a linear ramp voltage at termi-nal 7. The ramp voltage has a value that ranges from 0.6V to3.5V and is used as the reference for the comparator in thedevice. The charging current is equal to (5-2VBE)/RT or approx-imately 3.6/RT and should be kept within the range of 30pA to2mA by varying RT. The discharge time of CT determines thepulse width of the oscillator output pulse at terminal 3. Thispulse has a practical range of 0.5s to 5s for a capacitorrange of 0.001 to 0.1F. The pulse has two internal uses: as adead-time control of blanking pulse to the output stages toassure that both outputs cannot be on simultaneously and as atrigger pulse to the internal flip-flop which controls the switch-ing of the output between the two output channels. The outputdead-time relationship is shown in Figure 4. Pulse widths lessthan 0.5s may allow false triggering of one output by remov-ing the blanking pulse prior to a stable state in the flip-flop.

FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A FUNCTION OF TIMING CAPACITOR VALUE

If a small value of CT must be used, the pulse width can be fur-ther expanded by the addition of a shunt capacitor in the orderof 100pF but no greater than 1000pF, from terminal 3 toground. When the oscillator output pulse is used as a syncinput to an oscilloscope, the cable and input capacitances mayincrease the pulse width slightly. A 2-K resistor at terminal 3will usually provide sufficient decoupling of the cable. Theupper limit of the pulse width is determined by the maximumduty cycle acceptable.

The oscillator period is determined by RT and CT, with anapproximate value of t = RTCT, where RT is in ohms, CT is inF, and t is in s. Excess lead lengths, which produce straycapacitances, should be avoided in connecting RT and CT totheir respective terminals. Figure 5 provides curves for select-ing these values for a wide range of oscillator periods. Forseries regulator applications, the two outputs can be con-nected in parallel for an effective 0-90% duty cycle with theoutput stage frequency the same as the oscillator frequency.Since the outputs are separate, push-pull and flyback applica-tions are possible. The flip-flop divides the frequency such thatthe duty cycle of each output is 0-45% and the overall fre-quency is half that of the oscillator. Curves of the output duty

5.02

5.00

4.98

4.96

RE

FE

RE

NC

E V

OLT

AG

E (

V)

-60 -40 -20 0 20 40 60 80 100 120 140

AMBIENT TEMPERATURE (oC)

V+ = 40V, IL = 0mA

V+ = 20V, IL = 0mA

V+ = 40V, IL = 20mA

V+ = 8V, IL = 0mA

V+ = 20V, IL = 20mA

V+ = 8V, IL = 20mA

RE

FE

RE

NC

E V

OLT

AG

E (

V)

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.50 8 16 24 32 40 48 56 64 72 80

REFERENCE OUTPUT CURRENT (mA)

TA = +25oC

V+ = 20V

V+ = 40V

V+ = 20V

V+ = 8V

6

5

4

3

2

1

00

7

8

RE

FE

RE

NC

E V

OLT

AG

E (

V)

10 20 30 40

SUPPLY VOLTAGE, V+ (V)

TA = +25oC

OU

TP

UT

DE

AD

TIM

E (s

)

100

10

1.0

0.1

0.0001 0.001 0.01 0.1 1.0

TIMING CAPACITOR, CT (F)

TA = +25oC

V+ = 8V - 40V


CA1524, CA2524, CA3524

cycle as a function of the voltage at terminal 9 are shown inFigure 7. To synchronize two or more CAl524’s, one must bedesignated as master, with RT CT set for the correct period.Each of the remaining units (slaves) must have a CT of 1/2 thevalue used in the master and approximately a 1010 longerRTCT period than the master. Connecting terminal 3 togetheron all units assures that the master output pulse, which occursfirst and has a wider pulse width, will reset the slave units.

FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION OF RT AND CT

Error AmplIfIer Section

The error amplifier consists of a differential pair (Q56,Q57) withan active load (Q61 and Q62) forming a differential transcon-ductance amplifier. Since Q61 is driven by a constant currentsource, Q62, the output impedance ROUT, terminal 9, is veryhigh ( 5M).

The gain is:

AV = gmR = 8 lC R/2KT = 104,

Since ROUT is extremely high, the gain can be easily reducedfrom a nominal 104 (80dB) by the addition of an external shuntresistor from terminal 9 to ground as shown in Figure 6.

FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE CHAR-ACTERISTICS.

The output amplifier terminal is also used to compensate thesystem for ac stability. The frequency response and phaseshift curves are shown in Figure 7. The uncompensated ampli-fier has a single pole at approximately 250Hz and a unity gaincross-over at 3MHz.

Since most output filter designs introduce one or moreadditional poles at a lower frequency, the best network to stabi-lize the system is a series RC combination at terminal9 toground. This network should be designed to introduce a zero tocancel out one of the output filter poles. A good starting point todetermine the external poles is a 1000-pF capacitor and a vari-able series 50-K potentiometer from terminal 9 to ground.The compensation point is also a convenient place to insertany programming signal to override the error amplifier. internalshutdown and current limiting are also connected at terminal 9.Any external circuit that can sink 200A can pull this point toground and shut off both output drivers.

While feedback is normally applied around the entire regulator,the error amplifier can be used with conventional operationalamplifier feedback and will be stable in either the inverting ornon-inverting mode. Input common-mode limits must beobserved; if not, output signal inversion may result. The inter-nal 5V reference can be used for conventional regulator appli-cations if divided as shown in Figure 8. If the error amplifier isconnected as a unity gain amplifier, a fixed duty cycle applica-tion results.

FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF COMPARATOR VOLTAGE (AT TERMINAL 9).

FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A FUNCTION OF AMBIENT TEMPERATURE.

where R =

ROUT RL

, RL =, AV 104ROUT +

RL

TIM

ING

RE

SIS

TAN

CE

, R

T (

) 105

104

103

1 10 102 103 104

OSCILLATOR PERIOD, t (s)

TA = +25oCV+ = 8V - 40V

CT = 0.01F

CT = 0.002F

CT = 0.005F

CT = 0.001F

CT = 0.02F

CT = 0.05F

CT = 0.1F

VO

LTA

GE

GA

IN (

dB

)

80

70

60

50

400o

90o

PH

AS

E A

NG

LE

(DE

GR

EE

S)

RL =

RL = 3M

RL = 1M

RL = 300k

RL =100k

OPEN LOOP PHASE

OPEN LOOP GAIN

10 102 103 104 10550

FREQUENCY (Hz)

OU

TP

UT

DU

TY

CY

CL

E (

%)

48

40

32

24

16

8

0

COMPARATOR VOLTAGE (V)

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4

TA = +25oC

V+ = 20V

CT = 2700pFRT = 6.19kfOSC = 60kHz

CT =1000pFRT = 5kfOSC = 20kHz

1.1

1.0

0.9

0.8

0.7-75 -50 -25 0 25 50 75 100 125 150 175

OU

TP

UT

SA

TU

RA

TIO

N V

OLT

AG

E (

V)

AMBIENT TEMPERATURE (oC)


CA1524, CA2524, CA3524

Output Section

The CA1524 series outputs are two identical n-p-n transistorswith both collectors and emitters uncommitted. Each outputtransistor has antisaturation circuitry that enables a fast tran-sient response for the wide range of oscillator frequencies.Current limiting of the output section is set at 100mA for eachoutput and 100mA total if both outputs are paralleled. Havingboth emitters and collectors available provides the versatility todrive either n-p-n or p-n-p external transistors. Curves of theoutput saturation voltage as a function of temperature and out-put current are shown in Figures 8 and 9, respectively. Thereare a number of output configurations possible in the applica-tion of the CA1524 to voltage regulator circuits which fall intothree basic classifications:

1. Capacitor-diode coupled voltage multipliers 2. Inductor-capacitor single-ended circuits

3. Transformer-coupled circuits

FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A FUNCTION OF OUTPUT CURRENT

Device Application Suggestions

For higher currents, the circuit of Figure 10 may be used withan external p-n-p transistor and bias resistor. The internal reg-ulator may be bypassed for operation from a fixed 5V supplyby connecting both terminals 15 and 16 to the input voltage,which must not exceed 6V.

FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE CURRENT CAPABILITY

The internal 5V reference can be used for conventional regula-tor applications if divided as shown in Figure 11. If the erroramplifier is connected as a unity gain amplifier, a fixed dutycycle application results.

FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS

FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE REFERENCE REGULATION

To provide an expansion of the dead time without loading theoscillator, the circuit of Figure 13 may be used.

FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITHOUT USING A CAPACITOR ON PIN 3 OR WHEN A LOWVALUE OSCILLATOR CAPACITOR IS USED

OU

TP

UT

SA

TU

RA

TIO

N V

OLT

AG

E (

V) 2.0

1.5

1.0

0.5

0

0 20 40 60 80 100

OUTPUT CURRENT, IL (mA)

TA = +25oC

V+ = 8V to 40V

CA1524REFERENCE

SECTION15 16

8

V+

IL TO IADEPENDINGON CHOICEFOR Q1

GND

100

Q1

10F+

-

VREF

VREF

2

1

R2

5K

5K

R1

-

+

-

+2

1

R2

VREF

GND

GND

5K

5K NEGATIVEOUTPUTVOLTAGES

POSITIVEOUTPUTVOLTAGES

VO2.5V (R1 + R2)

R1

R1R2

R1 + R2= 2.5KW

R1

CA1524REFERENCE

SECTION15

16

8V+ CANNOTEXCEED 6V

VT

VREF

NOTE: V+ Should Be in the 5V RangeAnd Must Not Exceed 6V

8

16

95K


CA1524, CA2524, CA3524

FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED TO REDUCE POWER DISSIPATION UNDER SHORTEDOUTPUT CONDITIONS

FIGURE 15. CAPACITOR-DIODE COUPLED VOLTAGE MULTIPLIER OUTPUT STAGES

FIGURE 16. SINGLE-ENDED INDUCTOR CIRCUITS WHERE THE TWO OUTPUTS OF THE 1524 ARE CONNECTED INPARALLEL

FIGURE 17. TRANSFORMER-COUPLED OUTPUTS

5

4

SA//SBR1

R2

RS

SENSE

VO = 5V

IMAX =I

RS

VTH +VOR2

R1 + R2( )ISC =

VTH

RSWHERE

VTH = 200mV+

-

V+

V+

V+

SA

SA

SA

SB

SB

SB

D1

D1

D1

V+ > VO

V+ < VO

| V+ | > | VO |

+VO

+VO

-VO

NOTE: Diode D1 Is Necessary To Prevent ReverseEmitter-Base Breakdown of Transistor Switch SA.

V+

V+

V+

SA/SB

SA/SB

SA/SB

+VO

+VO

-VO

| V+ | < | VO |

V+ < VO

V+ > VO

TABLE 1. INPUT vs. OUTPUT VOLTAGE, AND FEEDBACK RESISTOR VALUES FOR IL = 40mA (FOR CAPACI-TOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)

VO (V) R2 (K) V+ (Min.) (V)

-0.5 6 8

-2.5 10 9

-3 11 10

-4 13 11

-5 15 12

-6 17 13

-7 19 14

-8 21 15

-9 23 16

-10 25 17

-11 27 18

-12 29 19

-13 31 20

-14 33 21

-15 35 22

-16 37 23

-17 39 24

-18 41 25

-19 43 26

-20 45 27

SA-B

V+

VO

V+

SA

SB

PUSH-PULL

FLYBACK

VO

VO

FULL BRIDGE

V+

+

-

VO

+

-

V+

SA

SB

Q1

Q2

CAN BE SA ORSA CAN DRIVEQ1

CAN BE SB ORSB CAN DRIVEQ2


CA1524, CA2524, CA3524

Applications (Note 1)

A capacitor-diode output filter is used in Figure 19 to convert+15VDC to -5VDC at output currents up to 50mA. Since the out-put transistors have built-in current limiting, no additional cur-rent limiting is needed. Table 1 gives the required minimuminput voltage and feedback resistor values, R2, for an outputvoltage.

Capacitor-Diode Output Circuit

A capacitor-diode output filter is used in Figure18 to convert+15VDC to -5VDC at output currents up to 50mA. Since the out-put transistors have built-in current limiting, no additional cur-rent limiting is needed. Table 1 gives the required minimuminput voltage and feedback resistor values, R2, for an outputvoltage range of -0.5V to -20V with an output current of 40mA.

Single-Ended Switching Regulator

The CA1524 in the circuit of Figure 19 has both output stagesconnected in parallel to produce an effective 0% - 90% dutycycle. Transistor Q1 is pulsed on and off by these outputstages. Regulation is achieved from the feedback provided byR1 and R2 to the error amplifier which adjusts the on-time ofthe output transistors according to the load current beingdrawn. Various output voltages can be obtained by adjustingR1 and R2. The use of an output inductor requires an R-Cphase compensation network to stabilize the system. Currentlimiting is set at 1.9 amperes by the sense resistor R3.

NOTE:

1. For additional information on the application of this device and a fur-ther explanation of the circuits below, see Intersil Application NoteAN6915 “Application of the CA1524 series PWM lC”.

FIGURE 18. CAPACITOR-DIODE OUTPUT CIRCUIT

FIGURE 19. SINGLE-ENDED LC SWITCHING REGULATOR CIRCUIT

1

CA3524

1

12

116

16

17

13

110

112

111

113

114

14

15

19

18

16

+15VV+

5K

2K

0.1F5K

R15K

0.01F

0.01F

R215K

IN4001

IN400120F

IN4001

50F

-5V20mA

R1 = 5K

R2 =R1 ( | VO | + 2.5)

(VREF - 2.5)

1

CA3524

1

12

116

16

17

13

110

112

111

113

114

14

15

19

18

115

+28VV+

5K

3K

0.1F5K

0.02F

0.001F

R25K

RURD410

V-

50K

0.1

500F

0.9mH

±Q1

2N6388

2K

+5V IA

R15K


CA1524, CA2524, CA3524

Flyback Converter

Figure 20 shows a flyback converter circuit for generating adual 15V output at 20mA from a 5V regulated line. Referencevoltage is provided by the input and the internal reference gen-erator is unused. Current limiting in this circuit is accomplishedby sensing current in the primary line and resetting the soft-start circuit.

Push-Pull Converter

The output stages of the CA1524 provide the drive fortransistors Q1 and Q2 in the push-pull application of Figure 21.Since the internal flip-flop divides the oscillator frequency bytwo, the oscillator must be set at twice the output frequency.Current limiting for this circuit is done in the primary of trans-former T1 so that the pulse width will be reduced if transformersaturation should occur.

Low-Frequency Pulse Generator

Figure 22 shows the CA1524 being used as a low-frequencypulse generator. Since all components (error amplifier,oscillator, oscillator reference regulator, output transistor driv-ers) are on the lC, a regulated 5-V (or 2.5-V) pulse of 0% - 45%(or 0% - 90%) on time is possible over a frequency range of150 to 500Hz. Switch S1 is used to go from a 5-V output pulse(S1 closed) to a 2.5-V output pulse (S1 open) with a duty cyclerange of 0% to 45%. The output frequency will be roughly halfof the oscillator frequency when the output transistors are notconnected in parallel (75Hz to 250Hz, respectively). Switch S2will allow both output stages to be paralleled for an effectiveduty cycle of 0%-90% with the output frequency range from150 to 500Hz. The frequency is adjusted by R1; R2 controlsduty cycle.

FIGURE 20. FLYBACK CONVERTER CIRCUIT

FIGURE 21. PUSH-PULL TRANSFORMER-COUPLED CONVERTER

1

CA3524

1

12

116

16

17

13

110

112

111

113

114

14

15

19

18

115

+5VV+

25K

2K

100F

0.02F

0.001F

620

300

1

RURD620

5K

4.7F

+

+

1M

510

+15V

-15V50F

50F50T

50T20T

200

0.1F

2N6290

CORE: FEROX CUBE2213P - A250 - 387OR EQUIVALENT

2N2102

IN914

5K

5K

RURD620

11

12

116

16

17

13

110

112

111

113

114

14

15

19

18

115

+28VV+

5K

2K

0.1F

20K

1K

1500F1K

5K

5K

5K

0.01F

1W

0.001F+

100F0.1F

5T

5T

20T

20T

+ 5V5A

1mH

1K

2N6292

2N6292

1K1W RURD620

RURD620


CA1524, CA2524, CA3524

FIGURE 22. LOW-FREQUENCY PULSE GENERATOR

The Variable Switcher

The circuit diagram of the CA1524, used as a variable outputvoltage power supply is shown in Figure 23. By connecting thetwo output transistors in parallel, the duty cycle is doubled, i.e.,0% - 90%. As the reference voltage level is varied, the feed-

back voltage will track that level and cause the output voltageto change according to the change in reference voltage.

FIGURE 23. THE CA1524 USED AS A 0-5A, 7-30 V LABORATORY SUPPLY

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

TO PIN 9

VREFERENCE

+5

R150K

20K

FREQUENCYADJUSTMENT

0.1F

SILVERMICA

2K

2K

R210K

DUTY CYCLEADJUSTMENT

V+ = 9V

1.5K

1.5K

CA35241/2S1

1/2S1

1/2S2

OUTPUT 1A

OUTPUT 2A

1.1K 1.1K

1/2S2TO PIN 12OUTPUT 1

TO PIN 1

TO PIN 13OUTPUT 2

SWITCHOUTPUT PULSES

DUTYCYCLE

S1 0V - 5V 0% - 45%

S2 - 0% - 90%

L120mH

D2 D4

D3D1

ACIN

5100F100V

D1-D4 - A15A

VDC36

R11K1W

Q1

2N6385(PNP DARLINGTON)

R21.510W

0.01F

D5

C310000F

100V

BIFILARWINDING

L250mH

VOUT

C40.1F

7V - 30V0A - 3A

RETURN

C525F

NON-POLAR

C625F

NON-POLAR

R1016K

C110.01F

C101100pF

SILVERMICA

C93300pF1%

R915K1%

C80.1F

R82K

R710K

R62K

R45K

R52K

R310K

C70.1F

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

CA1524

VOLTAGECONTROL fOSC = 20KHz

RURD410


CA1524, CA2524, CA3524

Digital Readout Scale

The CA1524 can be used as the driving source for anelectronic scale application. The circuit shown in Figures 24and 25 uses half (Q2) of the CA1524 output in a low-voltageswitching regulator (2.2V) application to drive the LED’sdisplaying the weight. The remaining output stage (Q1) is usedas a driver for the sampling plates PL1 and PL2. Since theCA1524 contains a 5V internal regulator and a wide operatingrange of 8V to 40V, a single 9V battery can power the total sys-tem. The two plates, PL1 and PL2, are driven with oppositephase signals (frequency held constant but duty cycle maychange) from the pulse-width modulator lC (CA1524). The sen-sor, S, is located between the two plates. Plates PL1, S andPL2 form an effective capacitance bridge-type divider network.

As plate S is moved according to the object’s weight, a changein capacitance is noted between PL1, S and PL2. This changeis reflected as a voltage to the ac amplifier (CA3160). At thenull position the signals from PL1 and PL2 as detected by Sare equal in amplitude, but opposite in phase. As S is driven bythe scale mechanism down toward PL2, the signal at Sbecomes greater. The CA3160 ac amplifier provides a bufferfor the small signal change noted at S. The output of theCA3160 is converted to a dc voltage by a peak-to-peak detec-tor. A peak-to-peak detector is needed, since the duty cycle ofthe sampled waveform is subject to change. The detector out-put is filtered further and displayed via the CA3161E andCA3162E digital readout system, indicating the weight on thescale.

FIGURE 24. BASIC DIGITAL READOUT SCALE

FIGURE 25. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE (CONT’D)

OSCILLATOR 20KHz(PART OF CA1524)

PL1

PL2

SACAMP

CA3130

COUPLED TO MECHANICAL

SCALE MECHANISM

PEAK TO PEAKDETECTOR

LOW PASSFILTER

DISPLAY DRIVE(PART OF CA1524)

DIGITAL METERAND DISPLAY

FULL SCALE

NO WEIGHT

DCVOLTAGE

13

12

11

10

9

15

14

16

15 2

6

1

72

1

13 7

CA3161ECA3162E

8 3

4

3

5

16MSD NSD LSD

+5V

COMMON-ANODE LEDDISPLAYS

11

10

POWER 2N2907OR EQUIVALENT

BCDOUTPUTS

DIGITDRIVERS

8 12 149

0.1F

10K

0.27F

ZEROADJUSTMENT

50K

2.5V

A

B

C

HIGH

LOW

INPUTS:

GAINADJUSTMENT

(NOTE 1)

NOTE:

1. FAIRCHILD FND507 OR EQUIVALENT


CA1524, CA2524, CA3524

FIGURE 26. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE

DIMENSIONS AND PAD LAYOUT FOR CA3524RH CHIP

NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The layout represents a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead

of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

6

42

3

PL1

S

PL2

9V

30K

39K

430K

100M 22M

18

7

CA3160

+

-

200pF

9V10K

100F

68K 6.2K

10K

0.1F 910K 910K

2F 0.47 2FF

300K A

B

C

10F

2.5V

22M

141516 13 12 11 10 9

87654321

4.7K200

2N40379V

TO SCALEMECHANISM

125H

470F

CA1524

24K

0.01F

4.7K

4.7K

6.2K

4700pF

4.7K

5V


CA1524, CA2524, CA3524

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as notedin the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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CA1524, CA3524 Datasheet - Intersil Frequency of Operation Beyond 100kHz • Variable-Output Dead...

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