C-CUBE MICROSYSTEMS C-CUBE JPEG S'TILL IMAO DESIGN GE …

• MICROSYSTEMS C-CUBE

JPEG C-CUBE

GE (SI-1) S' TILL IMAO DESIGN

BOAR MANUAL TECHNICAL

I

90-3503-003

MICROSYSTEMS C-CUBE

JPEG C-CUBE

GE (SI-1) STILL IMAD DESIGN BOAR MANUAL TECHNICAL

ii C-Cube Microsystems

This document is preliminary. The specifications contained herein are derived from functional specifications and performance estimates, and have not been verified against production parts.

C-Cube Microsystems reserves the right to change any products described herein at any time and without notice. C-Cube Microsystems assumes no responsibility or liability arising from the use of the products described herein, except as expressly agreed to in writing by C-Cube Microsystems. The use and purchase of this product does not convey a licence under any patent rights, copyrights, trademark rights, or any other intellectual property rights of C-Cube Microsystems.

Trademark Acknowledgment:

C-Cube Still Image Board, C-Cube SI-l Board, C-Cube Still Image Utility, and C-Cube CL550, are trademarks of C-Cube Microsystems. The corporate logo is a registered trademark of C-Cube Microsystems.

IBM and PC AT are trademarks of International Business Machines.

80386 and 80486 are registered trademarks of Intel Corp.

Windows is a trademark of Microsoft Corporation.

© C-Cube Microsystems 1992 All rights reserved

C-Cube Microsystems 1778 McCarthy Boulevard

Milpitas, CA 95035 Telephone (408) 944-6300

Fax (408) 944-6314

Preface

This application note provides detailed information about the C-Cube JPEG Still Image (SI-l) board design. It includes a complete technical description of the design including bus and chip timing, state machine state diagrams, schematics, PAL Equations, and a sample bill of materials.

This manual is intended for:

o System designers and managers who are evaluating the CL550 for possible use in a system

o Designers and hardware engineers who are designing a system based on the CL550

o Designers and hardware engineers who wish to produce a clone of the SI-l board design

o Programmers and software engineers who are writing application programs that interact with the CL550 and SI-l board

Audience

Preface iii

Organization

iv C-Cube Microsystems

This application note is divided into three chapters, and includes three appendices:

o Chapter 1: Introduction

o Chapter 2: Theory of Operation

o Chapter 3: Hardware Description

o Appendices

o Appendix A: Schematics

o Appendix B: PAL Equations

o Appendix C: Bill of Materials

The JPEG standard is described in detail in JPEG Still Picture Com-pression Algorithm, October 15, 1991. This document is available from Related the C-Cube Microsystems Marketing Department. Publications

Detailed information on the installation and operation of the SI-l board and its associated software is available in the "Still Image (SI-1) Board Users Manual" (C-Cube Publication # 92-1502-(01). This document is available from the C-Cube Microsystems Marketing Department.

Detailed information on the JPEG File Interchange Format (JFIF) is provided in "JPEG File Interchange Format Version 1.01". This docu-ment is available from the C-Cube Microsystems Marketing Depart-ment.

Detailed information on JPEG Device Independent Bitmap file formats can be found in "JPEG DIB File Formats". This document is available from the C-Cube Microsystems Marketing Department.

Detailed information on the CL550 Compression Processor is provided in the C-Cube CL550 JPEG Image Compression Processor Data Book (C-Cube Publication #90-1150-203). This document is available from the C-Cube Microsystems Marketing Department.

Detailed information on Microsoft defined Windows file structures can be found in the Microsoft Windows Software Development Kit Programmers Reference. Volume 3: Messages, Structures and Macros.

Detailed information on Windows graphics function calls can be found in the Microsoft Windows Software Development Kit Programmers Reference. Volume 2: Functions.

Preface y

vi C-Cube Microsystems

Notice:

At the time that this application note was written, the JPEG Still Frame Board had not yet gone through comprehensive compatibility testing. Although it is believed that the design is sound, minor changes to the P.C. bus timing may occur if incompatible computers are found. If problems are encountered, contact C-Cube technical support for the latest information and PAL equations.

Table of Contents

Section I. General Information

Chapter 1 Introduction 1.1 Design Kit Options 1.2 Additionallnformation

Chapter 2 Theory of Operation Theory of Operation

Chapter 3 Configuration and Installation 3.1 Address Decoder 3.2 Clock Generation 3.3 Host Bus Interface 3.4 Pixel Bus Interface

Section II. Appendices

Appendix A Schematics Schematics

Appendix B PAL Equations PAL Equations

Appendix C Bill of Materials Bill Of Materials

1-2 1-2

2-1

3-2 3-4 3-5

3-13

A-1

B-1

C-1

Table of Contents vii

Figures and Tables

Figure 2-1 Detailed Block Diagram 2-3

Figure 3-1 Clock Generator liming Diagram 3-4 Figure 3-2 START- State Diagram 3-5 Figure 3-3 Host Bus Register Write liming 3-7 Figure 3-4 Host Bus Register Read liming 3-10 Figure 3-5 Toggle State Machine State Diagram 3-14 Figure 3-6 STALL- Operation: Compression 3-15 Figure 3-7 STALL- Operation: Decompression 3-15 Figure 3-8 STALL- Handshake Operation For Compression 3-17 Figure 3-9 STALL- Handshake Operation For Decompression 3-20

Table 3-1 Base Address Jumper Positions 3-3

Table C-1 JPEG Still Image Board Bill of Materials C-2

viii C-Cube Microsystems

Chapter 1 Introduction

This application note describes the design of the C-Cube JPEG Still Image (SI-l) board. The SI-l board is designed for use in an IBM PC or PC clone based on the Industry Standard Architecture (lSA) bus. It contains a C-Cube CL550 JPEG compression processor which is mapped into the PC's 110 space.

This purpose of this application note is to provide the hardware designer enough information to either clone this design directly, or use this design as a starting point for a more complex JPEG compression processor board design.

This application note is divided into three chapters and three appendices:

1. Introduction: Introduction and additional information

2. Hardware Theory of Operation: Block level description of the circuitry on the board

3. Hardware Description: Detailed description of th~ hardware blocks, state diagrams and timing diagrams

4. Appendices

Introduction 1-1

Design Kit Options

1.1 Design Kit Options

1.2 Additional Information

To make it easier for you to reproduce boards based on this design, C-Cube offers two design kits:

1. Development Kit: A complete kit of information for either the hardware designer who is going to design a board similar to the SI-I or the software designer who is going to write CL550 drivers. This kit includes:

o A tested, working reference board

o A copy of the SI-l Users Guide

o A copy of the SI-l Product Brief

o The Microsoft Windows based JPEG Still Image Utility

o Source code for the Windows based JPEG Still Image Utility

o Some sample compressed images for testing and demonstration purposes

o A copy of the CL550 MonitorlDebugger (runs under DOS)

o A copy of the SI-l application note (this note)

2. Manufacturing Kit: A complete kit of information for the hardware designer who wishes to produce copies of the SI-l board. This kit includes everything listed in the Development Kit above plus:

o Gerber photoplot files and fabrication drawings for producing the SI-l printed circuit board.

Pricing and delivery information on these design packages is available from your local C-Cube sales representative. There is a list of these sales representatives at the end of this note.

For additional information on the SI-I board and JPEG compression in general, refer to the following documents:

o JPEG Still Image Board Users Manual, C-CubePIN 92-1502-001

o CL550 Databook, C-Cube part number 90-2250-203

o JPEG Still Picture Compression Algorithm, Baseline Process (available from C-Cube marketing, C-cube PIN 90-3503-001)

1-2 C-Cube Microsystems

Chapter 2 Theory of Operation

This chapter describes the theory of operation of the JPEG Still Image Board (SI-l) at the block diagram level. It shows the block diagram of the board, and describes the path the data uses in both compression and decompression modes.

The purpose of this chapter is to give the user a basic overview of the operation of the JPEG Still Image Board. Understanding what each section does will aid in understanding the detailed technical description in the next chapter.

Theory of Operation 2-1

The JPEG Still Image Board, or SI-l board, is a JPEG compression/decompression accelerator card that uses the C-Cube CL550 JPEG compression processor. The CL550 is the heart of the SI-l board, and all compression and decompression operations take place within the processor itself. The other 14 integrated circuits on the board simply connect the CL550 to the ISA (IBM PC AT) bus and provide status and control signals.

The SI-l compression board design has a single 10-MHz CL550 processor, two sets of bus transceivers and latches, control logic and clock circuitry. Figure 2-1 shows a block diagram of the board. This board design uses the CL550 in the still-frame mode. In this mode, the host (PC) processor reads and writes data to and from the CL550 processor, but the CL550 is not connected to a display device. The strip buffer is also not used.

Data can be transferred in any of the following modes:

o From a disk file to a disk file

o From a disk file to memory

o From memory to a disk file

o From memory to memory

The CL550 decompression processor has two buses. The 16-bit Host bus is used for programming the CL550 during the initialization process and for loading and unloading JPEG compressed data during operation. The 24-bit Pixel bus is used to transfer uncompressed pictures to and from the processor. Both buses are connected to the 16-bit ISA Data bus.

When the CL550 is compressing or decompressing 24 bit RGB data, the 24-bit Pixel bus expects data reads and writes to be 24 bits wide, but the ISA bus only supports 16-bit transfers. To overcome this bus width mismatch, latches have been added to store the extra eight bits of data.

When the pixel port is read, the lower 16 bits of the Pixel bus, PD[15:0], are enabled onto the ISA data bus, and the upper eight bits of the Pixel bus, PD[32:16], are stored in latch U7. The host processor accesses the upper eight bits by reading the pixel port a second time. Logic in the PALs automatically enables the latched data onto the ISA Data bus.


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;JISA 652 Data Buffer/ ! .. I Bus Latch(2)1.. ' __ ..- . .

U2,U3 Host DataPort and Cl550 Input Port

Reg.

U11

DIR TGL_EN

B_RESET

Board Control Register IOCHRDY

ISAAddress 22V1O BLI_v .. ,-

Bus PAL CTL_EN

INDEXWR AEN

lOR

lOW

RESET

Host Bus

Interface

Control Logic

22V1O START

PAL TMl BUSCTL)

U8 IOCHRDY

Host Bus Control Logic

t-t=t===;j22Vl0 PAL TOGGLE STALL

~ U9 NDEXWR

Pixel Bus Control Logic

__ HBCLK __ PXCLK

_PXPHASE

CLK3 ...

Pixel I 1 Bus

Interface

U4,U5 Pixel Bus InteriaC'e

PIXRDY

Board Status Register

Clock Generation Unit

OSC1, Ul2, U13 552-101

Figure 2-1 Detailed Block Diagram

When the Pixel port is written, the host processor must make two sequential writes. The first write stores the upper eight bits of pixel data into latch U6. When the second write is made, a reassembled 24-bit word made up of eight bits from the latch and 16 bits from the host data bus is strobed into the CL550 Pixel port.

During compression operations, uncompressed pixel data is written to the Pixel port, and compressed data is read from the host-bus data port as shown in Figure 2-2.

Pixel

Host Interface Huffman Decoder Synchronous Pixel Bus Pipeline

CL550 .........................................................................................................................................................................................

Figure 2-2 Compression Data Flow

During decompression operations, compressed data is written to the host-bus data port, and uncompressed data is read from the Pixel port as shown in Figure 2-3.

Host Interface Huffman Decoder

CL550

Figure 2-3 Decompression Data Flow

Synchronous Pixel Pipeline

The remaining logic on the board is the clock generation circuit and some control logic for decoding the board address and controlling the bus buffers.


Chapter 3 Hardware

Description

This chapter presents a detailed description of the various components of the JPEG Still Image (SI-l) board, using the schematic and PAL equations as references. The schematics are located in Appendix A of this document, and the PAL equations are located in Appendix B.

The purpose of this chapter is to give the designer a thorough understanding of the design of the SI-l board. The purpose of every integrated circuit on the board is discussed, and the timing of the ISA bus interface signals is described in detail. The state machines implemented in the PALs are described and state maps are provided.

The four sections of this chapter are:

o Section 3.1, Address Decoder

o Section 3.2, Clock Generation

o Section 3.3, Host Bus Interface

o Section 3.4, Pixel Bus Interface

Hardware Description 3-1

Address Decoder

3.1 Address Decoder

The SJ-l board is mapped into eight locations in the PC's 110 address space. Four 110 ports are used to configure and communicate with the board. The address of these ports is determined by taking the base address of the board and adding an offset value for the specific port being addressed:

CL550 Host Data Port Base+O

The host processor uses this 16 bit read/write port to pass data to and from the CL550s registers. The data to be passed includes programming and status information, and JPEG compressed data.

CL550 Index Register Base + 2 This 16-bit write-only register stores the address of the CL550 register being addressed. To access a CL550 register, the program must first load the CL550 register index value into this port.

Control! Status Register Base+4

This 110 location functions as the Control register during an 110 write, and the Status register during an 110 read. The Control I Status register is 8-bits wide, but only three bits are used in the control register, and one bit in the status register. They are:

o Control Bit 0: Direction. The host processor writes a 0 to this bit to configure the board for compression, and a 1 to configure the board for decompression.

o Control Bit 1: Toggle Enable. The host processor sets this bit to a 1 to enable the CL550 to transfer 24-bit pixel data.

o Control Bit 7: Reset. The host processor sets this bit to a 1 to force the CL550 into a hardware reset condition, and sets it to a 0 to release the reset. A reset is performed immediately after power-up and each time the operating mode is changed.

o Status Bit 0: Pixel Port Status. The host processor monitors this bit to determine the status of the CL550s Pixel Port. When the Pixel Port Status bit is aI, the CL550 is ready to input or output data.

Unused bit should be set to 0 when writing the register, and will return indeterminate data when reading the register.


Pixel Port Base + 6

The host uses this 16-bit read/write port to transfer pixel data to and from the CL550. When the board is configured for 24-bit pixel mode (Toggle Enable set to 1), two accesses are required to transfer a pixel. The first access will read or write the high byte (bits 23-16) of the pixel bus using the lower 8 bits of the data bus. The second access will read or write the lower word (bits 15 - 0) of the pixel bus.

The base address of the board is set using three jumpers. Table 3-1 lists the allowable base address configurations for the board.

Table 3-1 Base Address Jumper Positions

JP1 JP2 JP3 Base Address (Hex)

2-3 2-3 2-3 Ox03001

1-2 2-3 2-3 Ox0320 2-3 1-2 2-3 Ox0340 1-2 1-2 2-3 Ox0360 2-3 2-3 1 -2 Ox0380 1-2 2-3 1 -2 Ox03AO 2-3 1 -2 1 -2 Ox03CO 1-2 1 -2 1 -2 Ox03EO

1. Default Configuration

The address decoder, shown on Page 4 of the schematic, consists of two parts. NOR gates Ul4A and Ul4B detect that the upper six bits of the address bus are zero. Address decoder PAL UIO decodes nine of the lower ten bits and compares the results to the base address select jumpers. If the addresses match, then the board select signal (BD_SEL-) is generated. Note that to save logic, the least significant bit of the address is not decoded.

The signal CTL_ WR- (also called CTL_EN-) is generated whenever the host processor accesses address Base + 2. It is used to strobe the contents of the host data bus into the Board Control Register UII. IOCSI6-is generated whenever the host processor accesses any port on the SI-I board. This signal indicates to the ISA bus that a 16-bit wide transfer is in process.

Address Decoder


Clock Generation

3.2 Clock Generation

The SJ-l board contains its own clock generation circuitry. This circuit is shown on Page 5 of the schematic. Crystal oscillator aSCI generates a 10MHz symetrical square wave that is buffered by U12A and UI2B. U13A and U13B divide the clock by four giving 5MHz and 2.5MHz outputs.

The buffered oscillator signal PXCLK is used as the CL550 Pixel Clock. The 5MHz output drives the CL550 PXPHSE clock signal and the 2.5MHz output drives the CL550 CLK3 clock signal. HBCLK is the inverse of the Pixel clock signal PXCLK and is used to clock the PALS and to syncronize host bus transfers. Figure 3-1 shows the timing diagram for this circuit and shows the relationships between the four outputs.

PXCLK

HBCLK

PXPHASE

CLK3

Figure 3-1 Clock Generator Timing Diagram


The host bus interface, shown on Page 3 of the schematic, is designed to support CL550 slave mode transfers only. The data bus interface consists of two 74LS652 Octal bus transceiver/registers (U2 and U3) which act as both the index port and the host data port. A PAL controls these buffers during a transfer. When a slave mode transfer is performed, the host processor must first write the address of the register being accessed into the index port. In a separate operation, it must perform a read or write of the data port. At the time of the data port read or write, logic in the HBUSClL PAL US (Schematic Page 4) generates the signals necessary to complete a slave mode transfer.

Control logic for the host bus interface resides in the HBUSCTL PAL, US. Equations for this PAL, in ABEL format, are listed in Appendix B. All of the logic within the PAL is combinatorial except the logic that generates the START- signal. This output is controlled by a two bit state machine. The state diagram for the generation of START- is shown in Figure 3-2.

!DATA_EN DATA_EN START = FALSE START = TRUE

DON'T CARE START = FALSE 552-106

Figure 3-2 START- State Diagram

The control logic for the Host bus adds ISA bus wait states whenever necessary. Accessing the CODEC register incorrectly or at the wrong time can result in generation of a number of wait states that exceeds the ISA bus maximum allowable wait state specification. As a worst-case condition, the CL550 could simply never return an acknowledge (TM2-) which would cause the ISA bus to hang. There is no timeout mechanism in this design. Proper usage of the CODEC register is described in the CL550 databook, and examples of correct procedures

Host Bus Interface

3.3 Host Bus Interface


Host Bus Interface

for accessing the CODEC register are given in the driver code examples.

This information is provided to help you understand the sequence of events taking place:

o The 74S652 "A" bus pins are connected to the ISA data bus signals.

o The 74S652 "B" bus pins are connected to the CL550 host bus port.

o The signal H_ GAB enables the ISA data bus signals onto the CL550 host bus (PC write to CL550).

o The signal H_GBA enables the CL550 host bus signals onto the ISA data bus (PC read from CL550).

o The signal H_SAB enables the 74S652 latched data (previously written by the host processor into the Index register) onto the CL550 host bus.

o The signal H_SBA enables the 74S652 latched data (the stored output of the CL550) onto the ISA data bus.

o The signal H_CAB clocks the contents of the ISA data bus into the 74S652 "A" registers (Index register).

o The signal H_CBA clocks the output of the CL550 into the 74S652 "B" register.


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HBUS[15:0} =====:~j::::::::j:::::I:::I::::::::::::::::i:1Il::::::::::::::::j::::::::::l::I:::::~::m:m::::x,--__ _ I • I I t 552-104

Figure 3-3 Host Bus Register Write Timing

Host Bus Interface


Host Bus Interface

3.3.1 Host Bus Register Write Timing Figure 3-3 shows the sequence of events when the ISA host processor writes to a CL550 register. The circled numbers in the figure refer to the steps in the text below.

1. The processor on the ISA bus initiates the transfer by outputting the address of the CL550 host data port (Base + 0) on the address bus, SA[10:0].

2. The processor on the ISA bus asserts the Address Enable (AEN) signal to qualify the address.

3. The processor on the ISA bus asserts the I/O Write (IOW-) signal to indicate to the SI-l board that an I/O write operation is in progress.

4. The HBUSCTL PAL on the SI-l board responds by immediately asserting the ISA bus signal IOCHRDY - signal. This indicates to the host CPU that at least one wait state will be inserted.

5. All operations before this point have been asynchronous. Operations between the vertical dotted lines are synchronized to the HBCLK signal.

6. The HBUSCTL PAL asserts the START- signal and the TMlsignal to tell the CL550 that a write operation is in progress.

7. The HB USCTL PAL asserts the H_SAB signal. This signal enables the address of the CL550 register being written (the contents of the Index register) onto the host bus. (The Index register contents were written previously by the ISA host processor.)

8. The CL550 samples START-and TM1- and the register address on the host data bus on the falling edge of HBCLK. The CL550 internal write cycle begins at this point.

9. The HBUSCTL PAL releases H_SAB which enables the contents of the ISA data bus onto the host bus.

10. For any CL550 register other than the CODEC, there is always one clock period (wait state) between START and TM2. Accesses to the CODEC can encounter from zero to several (70 Pixel clock time) wait states.

11. When the CL550 is ready to accept the data, it asserts the acknowledge signal, TM2-. This completes the CL550 write cycle.


12. The HBUSC1L PAL releases IOCHRHY to tell the ISA bus that the data has been accepted.

13. The processor on the ISA bus releases lOW -, AEN and the data and address buses to end the ISA Bus write cycle.

Host Bus Interface


Host Bus Interface

AEN .!J! Sf@\,-__

SAI10:01~~,-__

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SD[15:0] -----r--T"'"""""":I~/)_~ ..,...; _~~-l[I=:[:[[[I:~t[lt=::[:::[:[:=:::::j[:[[=[[!I[[[=[:[:[:t~~:I:[:[X,-___ _

HBUS~~m ~ ___ ~~~~ _______ _ I I I I . . . . 552·105

Figure 3-4 Host Bus Register Read Timing


3.3.2 Host Bus Register Read Timing Figure 3-4 shows the sequence of events when the ISA host processor reads from a CL550 register. The circled numbers in the figure refer to the steps in the text below.

1. The processor on the ISA bus initiates the transfer by outputting the address of the CL550 host data port (Base + 0) on the address bus, SA[1 0:0].

2. The processor on the ISA bus asserts the Address Enable (AEN) signal to qualify the address.

3. The processor on the ISA bus asserts the 110 Read (IOR-) signal to indicate that a read operation is in progress.

4. The HBUSCTL PAL in the SI-l responds by immediately asserting the ISA bus signal 10CHRDY - signal. This indicates that at least one wait state will be inserted.

5. All operations before this point have been asynchronous. Operations after this point are synchronized to the HBCLK signal.

6. The HBUSCTL PAL asserts the START- signal and deasserts the TMl- signal to tell the CL550 that a read operation is in progress.

7. The HBUSCTL PAL asserts the H_SAB and H_GAB signals. This enables the address of the CL550 register being addressed (the contents of the Index register) onto the host bus. (The index register was written previously by the ISA host processor)

8. The CL550 samples START- and TMl- and the register address on the host data bus on the falling edge of HBCLK. The CL550 internal read cycle begins at this point.

9. The HBUSCTL PAL releases H_SAB and H_GAB which three-states the host bus.

10. For registers other than the CODEC, there is always one clock period (wait state) between START and TM2. Accesses to the CODEC can encounter from zero to several (70 Pixel clock time) wait states.

11. The CL550 outputs the data on HBUS[15:0] and asserts the acknowledge signal, TM2-. This completes the CL550 read cycle.

12. The HBUSCTL PAL asserts and releases H_CBA. Data from the CL550 is stored in the LS652 registers on the rising edge of

Host Bus Interface


Host Bus Interface


H_ CBA. Because H_ GBA is asserted, it immediately bercomes visable on SD[15:0].

13. The HBUSCTL PAL releases IOCHRHY to tell the ISA bus that the data is available.

14. The ISA bus releases IOR-. This causes H_GBA to be released, and the data on SD[15:0] to become invalid.

15. The ISA bus releases AEN and the data and address buses to end the ISA bus read cycle.

The CL550 Pixel port is a 24-bit wide data port used to transfer pixel data to and from the CL550 processor. During compression operations, it is used as a write-only port to input uncompressed image data. During decompression operations, it is used as a read-only port to output decompressed image data.

Video formats grayscale, YCbCr 4:2:2 and CMYK use only 16 of the 24 pixel port data lines. All the remaining formats use all 24 pixel port data lines. Bit one in the SI-l 's Control register (TGL_EN) sets the 16-bit transfer mode when it is LOW and 24-bit transfer mode when it is HIGH.

The pixel port on the SI-l board, shown on Pages 3 and 4 of the schematic, consists of two transceivers (U4 and U5) and two latches (U6 and U7) that connect the 24-bit Pixel data bus to the 16-bit ISA computer data bus. The latches are used to store the upper 8 bits of the 24-bit bus in the 24-bit mode. U7 is used to store the upper eight bits when reading data from the Pixel port, and U6 is used to store the upper eight bits when writing data to the Pixel port. The PBUSCTL PAL (22VI0 U9) controls these buffers and latches during read and write operations.

Sixteen-bit pixel data can be transferred using a single IJO read or write. 24-bit pixel data reads and writes always require two IJO accesses. To write a 24-bit pixel, the host must first write the upper 8 bits of the pixel. This byte is temporarily stored in latch U6. On the second write the host writes the lower 16 bits of the pixel. As the lower word is being written, logic in the PBUSCTL PAL enables the byte stored in latch U6 onto Pixel bus bits PD[23:16], and enables the word currently on the host data bus onto Pixel bus bits PD[15:0]. The reassembled 24-bit word is then written into the CL550.

Twenty-four-bit pixel port reads also require two accesses. During the first read, the lower 16 bits of the pixel bus, PXDAT[15:0], are output on the ISA data bus, and the upper 8 bits, PXDAT[23: 16], are stored in a latch (U7). The second read enables the latched data onto the 8 least significant bits of the ISA computer data bus.

The Toggle state machine in the Pixel bus control PAL generates the signals necessary to perform 24-bit accesses. The state diagram for this PAL is shown in Figure 3-5. Immediately following a reset, the state machine is always in the WORD state. If a compression is the first op-

Pixel Bus Interface

3.4 Pixel Bus Interface


Pixel Bus Interface

eration to be performed after a reset, the state must be changed to the BYTE state by performing a dummy read of the Pixel port.

Figure 3-5

!LCMO -0-

BYTE

WORD

POLEN -0-

Toggle State Machine State Diagram

State Variables [TOGGLE2:TOGGLE]

552·111

One of the more important components of the pixel bus interface is the hardware handshake mechanism for controlling the CL550 STALL- input. The CL550 can manipulate data much faster than the ISA bus is capable of transferring it. The STALL-line is used to hold the CL550 until the ISA bus can complete the transfer.

Figure 3-6 and Figure 3-7 show the operation of the STALL state machine during a compression operation and a decompression operation respectively. Generation of the STALL- signal is complex because during 24-bit operations the CL550 must be stalled until both the low word and the high byte have been transferred.


Figure 3-&

Figure 3-7

!PXRE -0-

PXRE-PDLEN 1

STALl- Operation: Compression

State Variables [STALl2:STALL]

552-\10

tPXWE o·

PXWEINMRQ

STALL- Operation: Decompression

State Variables [STALL2:STALL]

552-108

Pixel Bus Interface


Pixel Bus Interface

The following background information is given to help you understand the examples.

[J The CL550 clocks on the rising edge of PXCLK, but the PALS clock on the rising edge of HBCLK. This means that signals generated in the PALS will appear to transition in the center of the PXCLK cycle.

[J The CL550 expects the pixel data to be presented on the following pins:

[J PD [23:16] = Blue Pixel Data

[J PD [15:8] = Green Pixel Data

[J PD [7:0] = Red Pixel Data

[J A CL550 Pixel read cycle is a Host bus write cycle and a CL550 Pixel write cycle is a Host bus read cycle.


::t: CD ..., c. :e CD ..., CD

C CD (I) o ..., -C. d'. o :::l

~ ~

PXClK

HBClK

PXRE

lPXRE

DIR

STAll-

STAlU1:0)

PXRDY

lPDLEN-

PDH_RD

PDH_WR

TOGGLE

TGU2:1)

PD[23:16)

PD[15:0)

PIX_EN

SA[15:0)

AEN

I OW

lCMD

IOCHRDY

SD[15:0)

1 __ - ~_~, r---y----y---., -- , " r -----.-----

~ : : :@Y \: \£J\.--n II - '-....... --"'"--_ ......

0[0:O]~[1:0]~~ 2[1:~] : ~~ 2[1:~] X 3[1:0] X,--;--.....:....-O[-O:O..;..~-.....:. ~. lSI ,\ I

Sf m_~:__ t:: ~ I ," , ,

Sf;&'\ in ----t.

LJ ,SI \

'0[0:0] (7~ ; ; ; ; ; ; ; ;

~ 2[1:1] 2[1:1] 3[1:0]

Blue Data Gv , I , , I

: ~ I I , I

X Red/Green Data i i i i i

I , , 0[0:0]

, ,

i X i i

,

I

i

CLK

CL550

CON REG

PBPAl

PBPAl

PBPAl

PBPAl

PBPAl

PBPAl

PBPAl

PBPAl

CL550

CL550

: :,-: \ : : :/ : \: PBPAl ------t{h : , 'f : __ ----,~ 0 ~ PC BUS

5 ' :.~: 1 ®/ PC BUS 6 " ..' , •• l \® l@)/" l \@j,....;l-----r----r PCBUS

Sf '\ i / n i\ ;/ PBPAl

Sf SI l \®@j,.;-l--+---r----i--PCBUS

---~(t=xf.-~ Blue Data X ~1 X Red/Gre~n Data' X PC BUS

I~ ~I 1- Word Write ~ I Byte Write ~ r-I~ 552-107

Figure 3-8 STALL- Handshake Operation For Compression

"'0 x· !!. CD c (I)

:;--CD ~ CD o CD

Pixel Bus Interface

3.4.1 Pixel Bus Compression Timing Figure 3-S shows the timing diagram for a typical pixel write cycle during a compression operation. The numbers in the diagram refer to the steps listed below.

1. The transfer begins when the CL550 requests a 24-bit wide pixel. It asserts PXRE- to begin the request.

2. The pixel bus PAL immediately causes the CL550 ST ALL- signal to be asserted, putting the CL550 into a wait state. During compression operations, the stall signal must remain asserted until the host processor has written both the upper byte and the lower word of data.

3. The pixel bus PAL asserts the PXRDY signal. This signal is connected to Bit 0 in the status register (Pixel Port Status). The host must determine that the CL550 is ready to input data by polling the PXRDY bit and transferring data when it becomes valid. (PXRDY only needs to be checked for the first pixel. For all subsequent pixels, it is guaranteed to be ready again before the next pixel write.)

4. The pixel bus PAL holds the CL550 stalled while waiting for the host processor to supply the first byte of data.

5. When the host processor is ready to provide the requested data, it begins the write operation by outputting the address of the SI-l pixel port and asserting the Address Enable (AEN) signal.

6. The processor indicates to the CL550 that a write operation is going to take place by asserting 110 Write (lOW-).

7. The Toggle State Machine recognizes the valid write condition and changes state.

S. The combination of the assertion of lOW-and state 1 from the Toggle state machine causes the signal PDH_ WR to be asserted by the pixel bus PAL. This signal enables the contents of the lower eight bits of the data bus (SD 7:0) into the High Byte Pixel Latch (PX23:16). This is typically Blue pixel data.

9. On the next HCLK rising edge, the Toggle state machine increments again. This causes the PDH_ WR signal to be deasserted and the TOGGLE signal to be asserted. The pixel data is latched


into the High Byte Pixel Latch (U6) on the falling edge of PDH_WR.

10. The host processor releases IOW-, AEN, and the address and data buses. This completes the write of the High Byte Pixel Latch.

11. The CL550 remains stalled until the host processor is able to provide the lower word of data.

12. When the host processor is ready to provide the lower word, it begins the write operation by outputting the address of the CL550 pixel port and asserting Address Enable (AEN).

13. The host processor asserts IOW- to indicate to the CL550 that it is going to write the second word.

14. The Host Bus Interface PAL pulls IOCHRDY low. This forces the host bus to hold the data on the data bus until the CL550 has accepted it by adding ISA bus wait states.

15. The Pixel Bus PAL releases Statl. This allows the CL550 to complete the "read a 24-bit pixel" operation. To re-assemble the 24-bit word, the upper eight bits (Blue data) are read from the High Byte Pixel Latch, and the lower 16 bits (Red/Green data) are read directly from the Host data bus.

16. The CL550 acknowledges that it has read the data by deasserting the PXRE- signal.

17. Pixel data is sampled on the same clock edge that deasserted the PXRE- signal.

18. The Host Bus Interface PAL releases IOCHRDY as soon as it sees PXRE- deasserted. This allows the host CPU to finish the write cycle.

19. The Host CPU finishes the write cycle by releasing IOW-, AEN, and the address and data buses. This completes the write of a 24-bit pixel.

Pixel Bus Interface


w N c

("') I

("') c: C'" CD

s: 0' ~ o ~ ~ CD 3 en

"v , Cl550 III I !"

DlR/ : -:'

STAll- ---t--\~ irov : \<ill PBPAl

CON REG

: ~f ~ ~:~f~~~~~--~---4---+---+---+---+--

STAlU1:0] O[O:O])Q[O:l]~J 1[0:1] X 2[1:1] X 3[1:0] ~~ 3[1:0] ~ 1[0:1] PBPAl

~r+f ,+if PXROY ~ : ,\ I : @: PBPAl

POLEN- r------rJ \®. / II PBPAl

POH_RO- rf' Sf \® ! PBPAl ,

~~ , « ~~ iff .,

TOGGLE

TGU2:l]

PO[23:16]

PO[15:0]

PIx..EN

SA[15:0]

AEN

IOR-

lCMO

IOCHROY

SO[15:0]

Figure 3-9

~:J~~--~--~:---~~-\~ / ~ I ~ ;

J ; i \..I) i i i , In , , , i ; i i i

2[1:1] X 3[0:1] 0[0:0] 0[0:0] Gs 1[1:0] 2[1:1] , , , , , , , , , , , , , , , ,

PBPAl

PBPAl

X BLUE DATA Cl550

X RED/GREEN DATA , ~ , , , , , , , , , , , , , , ,

Cl550

:: : r---;---;-\ : : I \ PBPAl !-----!.-sf "::. ' fJ ' . .

~~ X' {t-v,..:..-' --:"----'-----:----:---"\x' PC BUS .----.JJ----r-1' , ,I JJ-I' • i i

: : ®I: 19\1 ®I; \: u -, \.V\: u - , ". --...... ------------r----T' l \®! Sf l \® kw! : PC BUS

PC BUS

~f 1\ ! fJ 1\ / PBPAl

~-~, V' fJ V " , " , " , PC BUS

:----)J , X ~O/GREEN X: ' )j , X BLUE:OATA: X , I. Word Read ~ I I.. Byte Read ~ f 552-109

PC BUS

STALL- Handshake Operation For Decompression

~

x' ~ m c: en :;Cit ~ Q) (')

CD

3.4.2 Pixel Bus Decompression Timing Figure 3-9 shows the timing diagram for a typical pixel read cycle during a decompression operation. The numbers in the diagram refer to the steps listed below.

1. A Decompression pixel write cycle begins when the CL550 has a 24 bit pixel ready to be transferred to the host computer. The CL550 asserts PXWE- to start the transfer. The CL550 data bus is already valid at this point.

2. On the next leading edge of HBCLK, the pixel bus PAL asserts the PXRDY signal. This signal is connected to Bit 0 in the status register (pixel Port Status). The host must determine that the CL550 is ready to output data by polling thePXRDY bit and transferring data when it becomes valid. (Note: PXRDY needs to be polled on the first pixel of every group of eight pixels during the first eight lines of the frame. After the first eight lines, PXRDYonly needs to be checked once for the remainder of the frame.)

3. The pixel bus PAL also causes the CL550 ST ALL- signal to be asserted, putting the CL550 into a wait state. The ST ALL- signal will remain asserted only until the host processor has read the lower word of pixel data. During decompression operations there is no need to stall the CL550 until the upper byte is read because the upper byte of pixel data is stored in an external latch.

4. The pixel bus PAL generates CL550 wait states while waiting for the host processor to read the first byte of data. The CL550 can be stalled indefinitely with no loss of data.

5. When the host processor is ready to accept the data, it begins the read operation by outputting the address of the SI-l pixel port and asserting the Address Enable (AEN) signal.

6. The processor indicates to the CL550 that a read operation is taking place by asserting 110 Read (I0R-).

7. The Toggle State Machine recognizes a valid read condition and changes state.

8. The combination of the assertion of IOR- and state 01 from the

Pixel Bus Interface


Pixel Bus Interface


Toggle state machine causes the signal PDL_EN to be asserted by the pixel bus PAL. PDL_EN enables the contents of the pixel data bus, PD[15:0], onto the host bus, SD[15:0]. This is typically Red/Green pixel data.

9. The host processor releases IOR-, AEN, and the address and data buses. This completes the read of the lower 16-bits of the Pixel data bus.

10. The Pixel Bus PAL releases the STALL- signal. This allows the CL550 to continue the decompression operation.

11. When the CL550 sees the ST ALL- signal released, it completes the bus cycle by releasing PXWE-. The rising edge of PXWEis used to strobe the contents of the upper 8 bits of the pixel bus into the high byte pixel latch.

12. The pixel bus PAL recognizes that the transfer is complete and increments the Toggle state machine. This causes the TOGGLE line to change from the word state (HIGH) to the byte state (LOW).

13. One PXCLK cycle after the PXWE- was released, the CL550 has the next 24-bit pixel ready to be stored. The host processor has not yet read the high byte at this point and is not ready to accept the data.

14. The Pixel bus PAL causes the CL550 stall signal to be asserted until the host processor is able to accept the data. The new pixel cannot be read until the high byte of the last pixel has been retrieved from the latch.

15. The host processor begins the read of the pixel high byte by outputting the address of the SI-1 pixel port and asserting the address enable (AEN) signal.

16. The processor indicates to the CL550 that a read operation is taking place by asserting 110 Read (IOR-).

17. The Pixel bus PAL asserts the PDH_RD- signal to enable the output of the Pixel high-byte latch (Blue Data) onto lower eight bits of the host data bus.

18. The Toggle State Machine recognizes a valid read condition and changes state.

19. The host processor releases IOW-, AEN, and the address and data buses. This completes the read of the Pixel high byte latch.

20. The signal PXRDY is valid because the next 24-bit pixel is ready to be read.

Pixel Bus Interface


Pixel Bus Interface


Appendix A Schematics

This appendix contains the schematics for the JPEG Still Image Board. The schematics were drawn using the ORCAD Schematic Capture program. The source files for the schematics are located on the diskette entitled:

JPEG Still Frame Board Schematics and PAL Equations

H a rdwa re Rev. A Part #83-5003-003

This diskette is included with the JPEG Still Image Board manufacturing kit.

Schematics A-l

» N

n I

n C CCD

3: O· .., o ~ ~ 3 en

PC 5 5 0

I LINK

ICL550.SCH I BUSBUFFS.SCH ICONTROL.SCH I CLOCKS. SCH I ISA_BUS.SCH

C-CUBE MICROSYSTEMS

1778 McCarthy B1vd. Mi1pitas, CA 95035 USA Te1: (408) 944-6300 FAX: (408) 944-6314

'l.'it1e PC550 JPEG Compression Card for AT

si:elDocument Number IR~ Date: March 31 1992 ISheet 1 of 6

(I) o ;:r en 3 Q)

C". o en

l> W

<HB.lQ. •• ....!.;U (START

~ ~

[CCCRES lliBCLK ./

<NMRQ=t

lE!ID-PULL-UP

HRro. 1.51

~ HBUS31 ~ HBUS30 ~ HBUS29 ~ HBUS28

3 HBUS27 ~ HBUS26 ~ HBUS25 ~ HBUS24 ~ HBUS23 ~ HBUS22 ~ HBUS21 ~ HBUS20 W, HBUS19 o HBUS18 ~ HBUS17 ~ HBUS16

HB15 44 HBUS15 HB14 45 HBUS14

VHB13 ~ HBUS13 HB12 47 HBUS12

VHBll 48 HBUS11 HB10 50 HBUS10

VHB9 51 HBUS9 V.HBS 52 HBUSS VHB7 53 HBUS7 VHB6 54 HBUS6 VHB5 55 HBUS5 VHB4 56 HBUS4 VHB3 57 HBUS3 VHB2 58 HBUS2

HBl 60 HBUS1 V,HBO 62 HBUSO V

65 I START 19 IDMA~STR

6~ ITM2 68 ITM1 *ff ITMO

IRESET 64 HBCLK

~ IDRQ 70 INMRQ

~ HALF_FULL IFRMEND

~ IHBOUT ~ ITMOUT

IID3 23 IID2 2~ IID1 25 lIDO 18 IHBUS_32 72 TEST

CL550Q

PXADR15 PXADR14 PXADR13 PXADR12 PXADR11 PXADR10

PXADR9 PXADR8 PXADR7 PXADR6 PXADR5 PXADR4 PXADR3 PXADR2 PXADR1 PXADRO

PXDAT23 PXDAT22 PXDAT21 PXDAT20 PXDAT19 PXDAT18 PXDAT17 PXDAT16 PXOAT15 PXDAT1.4 PXOAT1.3 PXDAT1.2 PXDATl.l. PXDAT10

PXDAT9 PXDATS PXDAT7 PXDAT6 PXOAT5 PXDAT4 PXDAT3 PXDAT2 PXDATl. PXDATO

IPXRE IPXWE IPXIN

IPXOUT I STALL

PXCLK PXPHSE

CLK3

IVSYNC I HSYN,S; I BLANK

~i ~ t# i-ft~ t-tt t-tt I-ii r-tO r-ro

IR ~~

99 98 97 96 94 93 92 91 90 89 88 87 86 S5 84 82 81 80 79 78 77 76 75 74

123 122

~ 11 13 120 124 131

~ 12 13

I

Title

PD23 PD22 _, PD21 PD20 _, P019 PD18 P017 p016 POlS PD14 PD13 PD12 POll POl PD9 PDS P07 PD6 PD5 PD4 PI2:! PD2 POl PDO

PnLn .211 PO • • 2A. ,;> PXRE ~ PXWE- ,;>

~ STALL .7 PXCLKJ ~ PXPHSE J

<...£gQJ

C-CUBE MICROSYSTEMS

1778 McCarthy Blvd. Milpitas. CA 95035 USA

PC550 STILL IMAGE COMPRESSION CARD

sizelDocument Number A CL550 JPEG PROCESSOR

Date: April 23. 1992 (Sheet 2 of 6

REV

A

» J:.,

n I n c: C'" CD

3: c;. '"' o (I)

-< ~ CD 3 (I)

< so ••. !>

H GAB H GBA H CAB H 5AB H CBA H SBA

POL EN-OIR

LPOH WR POH RO-PXWE

~

500 4 501 5 502 b 503 7 504 8 505 9 S06 10 507 11

3 2 1 2 23 22

508 4 509 5 5010 6 50117 5012 8 5013 9 5014 10 5015 11

3 2 1 2 23 22

U2 Al Bl 20 HBO

19 HBl A2 B2 18 HB2 A3 B3 17 HB3 HB7 11 A4 B4 16 HB4 HB6 12 AS B5 15 HB5 HB5 13 A6 B6 14 HB6 HB4 14 A7 B7 13 HB7 HB3 15 A8 B8 HB2 16 HBl 17 GAB VHB 18 GBA

CAB SAB CBA SBA 74AL5652

U3 Al Bl 20 HB8 A2 B2 19 HB~ A3 B3 18 HB10 A4 B4 17 HBll HB1511

16 HB12 HB14 12 AS B5 15 HB13 HB13 13 A6 B6 14 HB14 HB12 14 A7 B7 13 HB15 HB11 15 A8 B8 HB1 16 HB9 17 GAB HB8 18 GBA

CAB SAB CBA SBA 74ALS652

----------------

u4 OIR 1

1~ G 9 P07 B8 A8 8 P06 B7 A7 7 P05 B6 A6 6 P04 B5 AS 5 PO:5 B4 A4 4 P02 B3 A3 3 POl B2 A2 2 poO Bl Al

74ALS245

US OIR 1

G .~

B8 A8 9 POlS 8 POll,! B7 A7 7 P013 B6 A6 6 P012 B5 AS 5 POll B4 A4

B3 A3 4 POlO j :5 P09 B2 A2 2 P08 j Bl Al

74AL5245

pnrn ?~, PO •. 23 >

U6 ~ 00 00 2 P016./ ~ !> PO 7 ~

01 01 6 POlS ~

02 02 ~ P019

~ 03 03 12 P02

~ 04 04 15 P021

~ 05 05 .6 P022

~ 06 06 .~ P02:5 07 07

1 11 OC

G 74AL5373

II U7 CLK 11

OC

~ 07 07 18 P023 HB..§.16 17 P022 ~

06 06 14 PO;.! HB412 05 05 3 P02 HB3..::!.. 04 04

~ P01~ 03 03 HB26 02 02 7 P018 HB15 4 P017 HB..Q.£ 01 01 3 P016 00 00

74AL5374

HBro .1<;1 HB ., .5 >

C-CUBE MICROSYSTEMS

1778 McCarthy Blvd. Mil itas CA 95035 USA

'.ritle BUS BUFFERS

Size Oocument Number REV A PC550 Compression Card for AT A

_D;;It;e.: _A.P~U._~1992 Sheet __ 3.. __ ~ _6

en o ::r CD 3 Q)

d'. o en

» U,

LHBCLK ......

IOR-IOW DIR TM2

14C LRESET ....... 9

""\ B RES 1 8

~ 74ALS27

LTGL EN ..... LPXRE ....: lPXWE ..... LNMR.O: .......

14A SA15 1

/SA14 2 12 VSA13 131 V

74ALS27

14B SA12 3 SA11 4 ""\ 6 SA1 5 1

V 74ALS27

SA .. 15 !':'" r, , "1

rAEN:>

PUP PUP3 PUP

JP1 JP2 JP3 - 1 ... 1 " 1 ;.. 2 n.. 2 (l ;;. 3 no. 3

JUMP 3 JUMP 3 JUMP 3

BASE ADDRESS SELECT

l

I\..SA9 I'\,SAB I'\,SA7 I'\,SA6 ~SA5 I'\,SA4 ~SA3 ~SA2

SA1

1

~ HBCLK 1 I1/CLK 1-.23 START-BDSEL- 2 01 A1 3 I2 02 ~~T2-

START- ~

A2 4 I3 03 .... 21 1- --IOR- 5 I4 04 20 H GAB

TM ~

IOW- 6 I5 05 1-..19 H GBA-H GAB :>

DIR 7 I6 06 18 H SAB H GBA- ~

TM2- 8" I7 07 17 H SBA H SAB :>

PDL EN 9 I8 08 16 H CBA H SBA

LPXRE 0 I9 09 15 WAIT- H CBA

~CK-LCMD- 11 I10 010 U15A

CCCRES- 13 I11 I12 1 2 IOCHRDYI

22V10 HBUSCTL 7407

U9 1 HBCLK 1 BDSEL 2 I1/CLK 01 .... 23 PDL EN-

A1 3 I2 02 22 PDH RD- PDL EN-">

A2 4 I3 03 .... 21 PDH WR PDH RD-'">

IOR- 5 I4 04 m~f)GGLE-PDH WR ">

IOW 6 IS 05 19 OGGLE2-I6 18 TALL-

DIR 7 06 TGL EN 8 I7 07 ~;rALL2-

STALL '">

PXRE 9 I8 08 16 CMD

PXWE 10 I9 09 15 LPXRE

NMR - 11 I10 010 14 PIXRDY ~

CCCRES- 13 I11 I12 22V10 PBUSCTL

CCCRES ">

A15 13 U10 22V1 n 1 1

A12 10 "'2 I1/CLK I/010 23 BD SEL-

A9 3 I2 I/09 22 CTL EN

A8 4 I3 I/08 21 INDEXWR- CTL WR '">

I4 20 IOCS16-A7 5 I/07

H CAB "'>

A6 6 I5 I/06 ~ A5 7 I6 U15B

A4 8 I7 I8 A3 9

3 4

A2 10 I9 IOCSTb=l

A1 11 I10 AEN 13 I11 7407

IOR 14 I12 IOW 15 I/01 JP3 16 I/02 JP2 17 I/03 JP1 18 I/04

I/05 ADDR DECODE

ITitle

C-CUBE MICROSYSTEMS

CONTROL LOGIC sizelDocument Number tREV

A PC550-ST STILL-IMAGE COMPRESSOR Date: Aorif 23. 1992 ISheet 4 of 6

l> Q,

C')

n c: em s: n' .., o ~ ~ (1)

3 U)

8

OSCILLATOR l.0.0 MHz

l.

Ul.2A

2

74ALS04

Ul.2B

~ PXCLK

74ALS04 HBCLK

PXPHSE VCCO--~--~------------------r-

CLOCK GENERATOR

HBUS PULL-UPS

VCC

RP2 COM r-..,.... ....... ----1

Rl. r-................ ~-R2 r--":;-~~ R3 r-..,... ........ ~R4 r--_~2-R5 r-""""='=R6 r-.............. ~-R7 r-"""''''';=':=R8 R9

4."7K

HB

RESET

.7K

Ul.2C

5

4 HBl. 5 HBl.l.

HBl: 7 HBl.

HBl. l.6 HBl.5

6

74ALS04

4 Ul.3A Ul.3B

!i D i 01 5

3 CLK ~D l.l.

01 9 rei

4-:7k

SIGNAL PULL-UPS

Ul.l. ",HBO 3 I HBl. 4 Dl.

HB2 7 02 HB3 8 03 HB4 i'3 04 HB5 l.4 05 HB6 l. 7 06 HB7 l.8 g~

I ~ U~~ ~ g~ 5 TGL EN ITGLA 03 6 ..

04 05 06

g~ rrr:s RES ~

iCTL WR- > il.{~t~ 74ALS273

BOARD CONTROL REGISTER C-CUBE MICROSYSTEMS

Title CLOCKS, CONTROL PORT

size Document Number REV A PC550 compression Card for AT A

Date: Aoril 23, l.992 Sheet __ 5 of 6

...!a.. IOCHCHK*

~ S07 S07 S06 3 S06 S05 4 S05 S04 5 S04 S03 6 S03 S02 7 S02 SOl 8 SOl SOO 9 soO

IOCHROY AEN

SA19 SA18 SA17 SA16 SA15 Tf)" SA15 SA14 17 SA14 SA13 18 SA13 SA12 19 SA12 SAll 20 SAll SAI0 21 SAI0

SA9 22 SA9 SA8 23 SA8 SA7 24 SA7 SA6 25 SA6 SA5 26 SA5 SA4 27 SA4 SA3 28 SA3 SA2 29 SA2 SAl 30 SAl SAO

PC SUS A

Jl SSHE*

LA23 LA22 LA21 LA20 LA19 LA18 LA17

MEMR* MEMW* 11 S08 S08

S09 12 S09 SOlO 13 SOl S011 14 SOl S012 15 SOl S013 16 SOl

CI) S014 17 SOl

0 S015 18 SOl

=s-eD

PC BUS C

3 Q) -0' en

:x:-I ......

VCC

J1S GNO

RESET 1~3-t+-t .....J +5V A •

IRQ9 -5V

ORQ2 -12V

SROY* +12V

GNO SMEMW* SMEMR*

ig~: 1-14=~~;~--II_I~-..J OACK3*

ORQ3 OACK1*

ORQl REFRESH*

SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3

OACK2* TC

SA~~~t g~gA

L..",P""C---"S"""U""'S""""B---

JI0 MEMCS16 *

IOCS16* I ~ I I IRQI0 IRQll IRQ12 IRQ15 IRQ14

OACKO* ORQO

OACK5* ORQ5

OACK6* ORQ6

DACK7*

MASTER* ~ ~~~FtEI GNO 18

PC BUS 0

VCC VDO +5V

Title

so

tOCHRI> ~

SA

VSS GND

C-CUBE MICROSYSTEMS

1778 McCarthy Blvd, Miloitas. CA 95035 USA

ISA_SUS, BY-PASS CAPS

Compression Card for AT 1992 ISheet 6 of 6

REV

A

A-a C-Cube Microsystems

Appendix B PAL Equations

This appendix contains the source equations for the PAL devices used in the design of the JPEG Still Image Board. The equations are written to be compiled using DATA liD's ABEL program. The source files for the PALs are located on the diskette entitled:

JPEG Still Frame Board Schematics and PAL Equations

H a rdwa re Rev. A Part 1183-5003-003

This diskette is included with the JPEG Still Image Board manufacturing kit.

PAL Equations 8-1

Address Decoder PAL Equations

B.1 Address Decoder

PAL Equations

module _addrdec;

title 'Address Decoder PAL PC550 still-Image Compression Card for AT

Revision A1, April 1992

C-Cube Microsystems, 1778 McCarthy Blvd, Milpitas CA 95035, U.S.A. Tel: (408) 944-6300 FAX: (408) 944-6314';

declarations

addrdec device 'p22v10';

"inputs A15_13 pin 1; A12_10 pin 2; A9 pin 3; A8 pin 4; A7 pin 5; A6 pin 6; AS pin 7; A4 pin 8; A3 pin 9; A2 pin 10; A1 pin 11; AEN pin 13; !IOR pin 14; !IOW pin 15; JP3 pin 16; JP2 pin 17; JP1 pin 18;

"outputs !BDSEL pin 23; !BDSEL istype 'com, neg' ; !CTL_WR pin 22; !CTL_WR istype 'com, neg' ; !INDEX pin 21; !INDEX istype 'com,.neg' ; !IOCS16 pin 20; !IOCS16 istype 'com, neg' ;


Address Decoder PAL Equations

"logic declarations

CMD = lOR # lOW; HIGH_A = A15_13 & A12_10; BASEl = HIGH_A & A9 & AS & ! A 7 & ! A6 & ! A5 & !A4 & !A3; "Ox300-307 BASE2 = HlGH_A & A9 & AS & !A7 & !A6 & A5 & !A4 & !A3; "Ox320-327 BASE3 = HlGH_A & A9 & A8 & !A7 & A6 & !A5 & !A4 & !A3; "Ox340-347 BASE4 = HlGH_A & A9 & AS & !A7 & A6 & A5 & !A4 & !A3; "Ox360-367 BASE5 = HlGH_A & A9 & AS & A 7 & !A6 & !A5 & !A4 & !A3; "Ox380-3S7 BASE6 = HlGH_A & A9 & AS & A7 & !A6 & A5 & !A4 & !A3; "Ox3AO-3A7 BASE7 = HIGH_A & A9 & AS & A7 & A6 & !A5 & !A4 & !A3; "Ox3CO-3C7 BASES = HIGH_A & A9 & AS & A7 & A6 & A5 & !A4 & !A3; "Ox3EO-3E7

equations

"BDSEL enables read/write transfers to the PC550 board

BDSEL (!JP3 & !JP2 & !JPl & !AEN & BASEl) # (!JP3 & !JP2 & JPl & !AEN & BASE2) # ( !JP3 & JP2 & !JPl & !AEN & BASE3) # ( !JP3 & JP2 & JPl & !AEN & BASE4) # (JP3 & !JP2 & !JPl & !AEN & BASE5) # (JP3 & !JP2 & JPl & !AEN & BASE6) # (JP3 & JP2 & !JPl & !AEN & BASE7) # (JP3 & JP2 & JPl & !AEN & BASES);

"CTL_WR enables a write to the PC550 Control

CTL_WR = BDSEL & A2 & !Al & lOW;

Register

"INDEX enables a write to the PC550 Index Register

INDEX = BDSEL & !A2 & Al & lOW;

"IOCS16 drives the IOCS16 line of the ISA bus during CMD

lOCS16 = BDSEL & CMD;

end _addrdec

PAL Equations B-3

HBUS Controller PAL Equations

B.2 HBUS Controller

PAL Equations

module _hbusctl;

title 'HBUS-to-ISA Bus Control Logic PC550 Still-Image Compression Card for AT and Compatibles

Revision A, September 17, 1992

C-Cube Microsystems, 1778 McCarthy Blvd., Milpitas, CA" 95035, USA. Tel: (408) 944-6300 FAX: (408) 944-6314 ';

declarations hbusctl device 'p22v10'; "inputs HBCLK pin 1; !BDSEL pin 2; A1 pin 3; A2 pin 4; !IOR pin 5; !IOW pin 6; DIR pin 7; !TM2 pin 8; !PDL_EN pin 9; !LPXRE pin 10; !LCMD pin 11; !CCCRES pin 13; "outputs !START pin 23; !START istype !START2 pin 22; !START2 istype !TM1 pin 21; !TM1 istype H_GAB pin 20; H_GAB istype !H_GBA pin 19; !H_GBA istype H_SAB pin 18; H_SAB istype H_SBA pin 17; H_SBA istype !H_CBA pin 16; !H_CBA istype !WAIT pin 15; !WAIT istype !LACK pin 14; !LACK istype

"intermediate expressions CMD = lOW # lOR;

'reg,neg' ; 'reg,neg' ; 'com,neg' ; 'com,pos'; 'com,neg' ; 'com,pos'; 'com,pos'; 'com, neg' ; 'com,neg' ; 'reg,neg';

DATA_EN = BDSEL & !A2 & !A1; INDEX_EN = BDSEL & !A2 & A1 & lOW; CTL_STS = BDSEL & A2 & !Al; PIX_EN = BDSEL & A2 & Al;


HBUS Controller PAL Equations

equations M/START AND /START2 FORM A STATE MACHINE WHICH PULSES START WHEN DATA_EN = 1

START := !START & !START2 & DATA_EN & LCMD & !CCCRES; START2 := (START & !CCCRES) # (START2 & LCMD & !CCCRES);

M/TMl IS EQUAL TO lOW BUT IS Hl-Z WHEN START IS FALSE TMl = lOW; TM1.OE = START;

MH_GAB contoIs the '652-to-HBUS drivers. H_GAB = (DATA_EN & lOW)

# (DATA_EN & lOR & START) # (PIX_EN & lOW) # (CTL_STS & lOW);

M/H_GBA controls the '652-to-ISA bus drivers. H_GBA = (DATA_EN & lOR)

# (PIX_EN & lOR) # (CTL_STS & lOR);

MH_SAB places the latched CL550 index value on HBUS H_SAB = (lOW & START)

# (lOR & START);

MH_SBA is used to pass latched CL550 register read data to lSA bus H_SBA = DATA_EN & lOR;

"H_CBA is used to latch read data from the CL550 during TM2 H_CBA = TM2 & IORi

MWAIT drives the IOCHRDY line. MOn host accesses, WAIT is driven until TM2 is returned from the 550. On pixel WORD writes, WAIT is driven until the rising edge of PXRE. On pixel BYTE read or writes, WAIT is driven until 1 clock past LCMD. On pixel reads, WAIT is driven until LCMD is asserted.On CTL port writes, wait is driven until 1 HCLK past LCMD.On INDEX port writes, wait is driven until 1 HCLK past LCMD.*

WAIT = (DATA_EN & CMD & !LACK) "CL550 Host r/w # (!DIR & PDL_EN & lOW & I LPXRE) "PIXEL WORD WRITE # (IDIR & PIX_EN & IPDL_EN & lOW & lLPXRE) "PIXEL BYTE WRITE # (PIX_EN & lOR & lLPXRE); "PIXEL READ

"LACK is true on TM2 (ACK) active and is latched through CMD active. LACK := TM2 # (LCMD & LACK); end _hbusctl; ?

PAL Equations B-5

Pixel Bus Controller PAL Equations

B.3 Pixel Bus Controller

PAL Equations

module -pbusctl; title 'PXDAT-to-HBUS Interface Control Logic PC550 Still-Image Compression Card for AT

Revision A, September 17, 1992

C-Cube Microsystems, 1778 McCarthy Blvd., Milpitas, CA 95035, USA Tel: (408) 944-6300 FAX: (408) 944-6314 ';

declarations pbusctl device 'p22vl0';

" inputs HBCLK pin 1; IBDSEL pin 2 ; Al pin 3; A2 pin 4; IIOR pin 5; I lOW pin 6; DIR pin 7; TGL_EN pin 8; IPXRE pin 9; IPXWE pin 10; !NMRQ pin 11; !CCCRES pin 13;

"outputs !PDL_EN pin 23; IPDL_EN istype IPDH_RD pin 22; IPDH_RD istype PDH_WR pin 21; PDH_WR istype !TGL1 pin 20; !TGL1 istype ITGL2 pin 19; !TGL2 istype !STALL pin 18; ISTALL istype ISTALL2 pin 17; ISTALL2 istype ILCMD pin 16; ILCMD istype ILPXRE pin 15; ILPXRE istype PIXRDY pin 14; PIXRDY istype

"logic declarations

CMD = lOR # lOW;

'reg,neg' ; 'com, neg' ; 'com,pos'; 'reg,neg' ; 'reg,neg' ; 'reg,neg' ; 'reg, neg' ; 'reg,neg' ; 'reg,neg' ; 'com,pos';

DATA_EN = BDSEL & IA1 & !A2; INDEX_EN = BDSEL & A1 & IA2 & lOW; STS_EN BDSEL & IA1 & A2 & lOR; CTL_EN = BDSEL & IA1 & A2 & lOW; PIX EN = BDSEL & A1 & A2; LPIX_EN = PIX_EN & CMD & LCMD; LPDL EN = POL EN & LCMD; PDH EN PIX_EN & !TGL1 & CMD; IRESET = CCCRES;

B-6 C-Cube Microsystems


equations

MPDL_EN opens the 16-bit transceivers connected to PXDAT[O .. 15] MThe x-cvrs open only for writes in compress and reads in decompress

PDL_EN = ( PIX_EN & TGLl & lOW & lDIR ) # ( PIX_EN & TGLl & lOR & DIR )i

MPDH_RD enables the a-bit read latch from PXDAT[16 .. 23] PDH_RD = PDH_EN & lOR & DIRi -decompress only

MPDH_WR enables the a-bit write latch to PXDAT[16 .. 23] PDH_WR = PDH_EN & LCMD & lLPXRE & lDIRi ·compress only

·These state equations control the pixel port toggle for 24/32-bit modes. MWhen toggle mode is entered, the initial state will point to the WORD ·port (TGL1=l, TGL2=1) . In compression, BYTE-WORD input of data is Mrequired, so a dummy read to the pixel port will toggle to the BYTE latch. ·For decompression, WORD-BYTE access of data is required (reading the word Mlatches the byte).

TGLl : = (l TGL_EN # (TGL_EN & TGL2 & lLCMD) # (TGL_EN & TGLl & LCMD) ) & lCCCRESi

TGL2 := lTGL_EN # (TGL_EN & TGL2 & lLPIX_EN) # (TGL_EN & lTGLl & LPIX_EN) # CCCRESi

PAL Equations B-7


·State equations for STALL in compression (l DIR) and decompression (DIR) .

STALL . - (lDIR & lIRESET & lSTALL2 & STALL) # ( lDIR & lIRESET & lSTALL2 & PXRE) # ( lDIR & lIRESET & STALL & PXRE & lLPDL_EN) # ( lDIR & lIRESET & lSTALL2 & lSTALL & NMRQ) # ( lDIR & lIRESET & STALL & lPXRE & NMRQ) # (DIR & lIRESET & STALL & STALL2 & LPDL_EN) # (DIR & lIRESET & lSTALL2 & PXWE) # (DIR & lIRESET & lSTALL2 & 1 PXWE & NMRQ);

STALL2 . - (lDIR & lIRESET & lSTALL2 & NMRQ) # ( lDIR & lIRESET & STALL2 & STALL & NMRQ) # (lDIR & lIRESET & STALL2 & PXRE) # ( lDIR & lIRESET & PXRE & lLPDL_EN) # ( lDIR & lIRESET & lSTALL2 & STALL & lPXRE & LPDL_EN) # (DIR & lIRESET & STALL & STALL2) # (DIR & lIRESET & STALL & PXWE & LPDL_EN) # (DIR & lIRESET & STALL2 & PXWE);

-LCMD is a synchronized CMD line for use in all state machines.

LCMD := (DATA_EN # PIX_EN) & CMD;

_ /LPXRE is used in compression WORD writes to hold WAIT until PXRE goes high. /LPXRE is used in compression BYTE writes hold wait for 1 clock past LCMD. /LPXRE is used in all pixel READs to hold WAIT for 1 HCLK past LCMD-

LPXRE := (lDIR & LPDL_EN & IPXRE) -PIXEL WORD WRITE # (lDIR & LPDL_EN & LPXRE) -PIXEL WORD WRITE # (lDIR & PDH_EN & lOW & LCMD) -Pixel BYTE write # (PIX_EN & lOR & LCMD); -pixel READ (byte or word)

-PIXRDY is a status bit which is read at IObase+4 (Pixel Port Ready)

PIXRDY (lDIR & PXRE & STALL) # (DIR & PXWE & STALL);

PIXRDY.OE = STS_EN & lOR;

end _pbusctl;

?

B-8 C-Cube Microsystems

Appendix C Bill of Materials

This appendix contains the Bill of Materials for the JPEG Still Image Board. All of the Integrated Circuits except the CL550-10 are expected to be in low-cost standard DIP packages.

The PAL devices need to be programmed to the equations listed in Appendix B before being loaded onto the board. To facilitate this, sockets are listed for these three devices only.

This Bill of Materials is for the board assembly only. It does not include items which are normally on the top level Bill of Material such as manuals, software diskettes, and packing materials.

Bill of Materials C-l

n N

n Table C-1 JPEG Still Frame Board Bill of Materials I

n c:

Item Dty Reference Part Number Description c-CD

s: 1 1 Ul Cl5500 Cl550-10 MOUAD JPEG Compression Processor C;"

2 2 U2,U3 74AlS652 Octal Transceivers/latches, Through Hole .., 0 (I) 3 2 U4,U5 74AlS245 Octal Transcievers, Through Hole -< (I) r+ 4 U6 74AlS373 Octal D-Type Transparent latches, Through Hole CD 3

5 U7 74AlS374 Octal D-Type Edge-Triggered Flip-Flops, Through Hole (I)

6 U8 HBUS Control PA122Vl 0-15 Programmable logic Device, Socketed

7 U9 PBUS Control PA122Vl 0-15 Programmable logic Device, Socketed

8 Ul0 ADDR Decode PA122Vl 0-15 Programmable logic Device, Socketed

9 Ull 74AlS273 Octal D-Type Flip-Flops with Clear, Through Hole

10 U12 74AlS04 Hex Inverters, Through Hole

11 U13 74AlS74 Dual D-Type Flip-Flops with Preset, Clear, Through Hole

12 U14 74AlS27 Triple 3-lnput NOR Gates, Through Hole

13 U15 7407 Hex Open-Collector Drivers, Through Hole

14 1 OSCl Oscillator TTL Oscillator, 10.0 MHz

15 3 JP1,JP2,JP3 JUMP 3 3-post Pin Jumpers

16 2 C2,Cl 35 uF Capacitor, Through Hole, Tantalum, 20V

17 18 C3,C4,C5,C6,C7 ,C8,C9,C1 0, .1 UF Capacitor, Through Hole, Ceramic, 20V Cl1,C12,C13,C14,C15,C16,

C17,C18,C19,C20

18 3 U8,U9,Ul0 DIP-24 24-pin DIP low Insertion Force socket

19 3 JP1 , JP2, JP3 SHUNT-2 Jumper Shunts

20 3 RP1,RP2,RP3 4.7K SIP res pack, 10 pin, 9 res, 5%

21 1 B1 PCB mounting bracket, GLOBE G35

22 2 Sl,S2 Philips Head Screw 4-40X3/16

23 Printed Circuit Board

C-Cube Microsystems

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California

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North American Representatives

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Connecticut

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District of Columbia

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Southern Semtronic Associates 3471 NW 55th Street Ft. Lauderdale, FL 33309 phone: 305-731-2484 fax: 305-731-1019

Georgia

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Hawaii

Bager Electronics 17220 Newhope Street, Suite 209 Fountain Valley, CA 92708 phone: 714-957-3367 fax: 714-546-2654

Idaho

Eastern Anderson Associates 270 South Main # 1 08 Bountiful, UT 84010 phone: 801-292-8991 fax: 801-298-1503

Western Thorson Company Northwest 12340 N.E. 8th Street Bellevue, W A 98005 phone: 206-455-9180 fax: 206-455-9185

DUnois

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Southern C-Cube Microsystems


Indiana Mississippi Southern

C-Cube Microsystems Montgomery Marketing Omega

1910 Sparkman Avenue 2655 Interplex Drive Suite 104

Iowa Huntsville, AL 35816 Trevose, PA 19053

phone: 205-830-0498 phone:215-244~

Cahill, Schmitz & Howe fax: 205-837-7049 fax: 215-244-4104 4905 Lakeside Dr. N.E.,Suite 100 Cedar Rapids, IA 52402 Missouri New Mexico phone: 319-377-8219

C-Cube Microsystems fax: 319-377-0958 C-Cube Microsystems

Kansas Montana New York

C-Cube Microsystems Promotech Sales, Inc. Metro 2901 S. Colorado Blvd. Parallax

Kentucky Denver, CO 80222 734 Walt Whitman Road phone: 303-692-8484 Melville, NY 11747

C-Cube Microsystems fax: 303-692-8416 phone: 516-351-1000 fax: 516-351-1606

Louisiana Nebraska Upstate n.. Marketing C-Cube Microsystems Empire Technical Associates 14850 Quorum Dr., Suite 100 29 Fennell Street, Suite A Dallas, TX 75240 Nevada Skaneateles, NY 13152 phone: 214-490-9300 phone: 315-685-5703 fax: 214-960-6075 Excluding Clark County fax: 315-685-5979

Norcomp Eastern Maine 2140 Professional Drive, #200 Roseville, CA 95661 Empire Technical Associates

Procomp Associates phone: 916-782-8070 349 W. Commercial Street 1049 East Street fax: 916-782-8073 Suite 2920 Tewksbury, MA 01876 East Rochester, NY 14445 phone: 508-858-0100 Clark County phone: 716-381-8500 fax: 508-858-0110 Bager Electronics fax: 716-381-0911

6324 Varlel, Suite 314 Maryland Woodland Hills, CA 91367 North Carolina

C-Cube Microsystems phone: 81S-712-0011

Montgomery Marketing fax: 818-712-0160 1200 Trinity Road

Massachusetts New Hampshire Raleigh, NC 27607 phone: 919-851-0010

Procomp Associates Procomp Associates fax: 919-S51-6620 1049 East Street 1049 East Street Tewksbury, MA 01876 Tewksbury, MA 01876 North Dakota phone: 508-858-0100 phone:50S-85S-0100 fax: 508-858-0110 fax: 50S-858-0110 Cahill, Schmitz & Cahill, Inc.

315 N. Pierce Street Michigan New Jersey St. Paul, MN 55104

phone: 612-646-7217 C-Cube Microsystems Northern fax: 612-646-4484

Minnesota Parallax 734 Walt Whitman Road Ohio

Cahill, Schmitz & Cahill, Inc. Melville, NY 11747 C-Cube Microsystems

315 N. Pierce Street phone: 516-351-1000 St. Paul, MN 55104 fax: 516-351-1606 phone: 612-646-7217 fax: 612-646-4484

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Oklahoma South Dakota Vermont

TL Marketing Cahill. Schmitz & Cahill. Inc. Procomp Associates 14850 Quorum Dr .• Suite 100 315 N. Pierce Street 1049 East Street Dallas. TX 75240 St. Paul. MN 55104 Tewksbury. MA 01876 phone: 214-490-9300 phone:612~-7217 phone: 508-858-0100 fax: 214-960-6075 fax: 612-646-4484 fax: 508-858-0110

Oregon Tennessee Virginia

Thorson Company Northwest Montgomery Marketing C-Cube Microsystems 9600 S.W. Oak Street #320 3000 Northwoods Parkway #110 Portland. OR 97223 Norcross. GA 30071 Washington phone: 503-293-9001 phone: 404-447-6124

Thorson Company Northwest fax: 503-293-9007 fax: 404-447-0422 12340 N.E. 8th Street

Pennsylvania Texas Bellevue. W A 98005 phone: 206-455-9180

Omega Northem fax: 206-455-9185 2655 Interplex Drive Suite 104 TL Marketing Trevose. PA 19053 14850 Quorum Dr .• Suite 100 West Virginia phone: 215-244-4000 Dallas. TX 75240

C-Cube Microsystems fax: 215-244-4104 phone: 214-490-9300 fax: 214-960-6075

Wisconsin Rhode Island Central

Procomp Associates TL Marketing Westem 1049 East Street 12015 Park 35 Circle. Suite 224 Cahill. Schmitz & Cahill. Inc. Tewksbury. MA 01876 Austin. TX 78753 315 N. Pierce Street phone: 508-858-0100 phone: 512-837-7272 St. Paul. MN 55104 fax: 508-858-0110 fax: 512-837-6886 phone: 612-646-7217

fax: 612-646-4484 South Carolina Eastem

Eastem TL Marketing Montgomery Marketing 14343 Tory Chase Blvd. Suite I Beta Technology Sales. Inc. 1200 Trinity Road Houston. TX 77014 9401 W. Beloit Road. Suite 409 Raleigh. NC 27607 phone: 713-587-8100 Milwaukee. WI 53227 phone: 919-851-0010 fax: 713-580-7517 phone: 414-543-6609 fax: 919-851-6620 fax: 414-543-9288

Utah Wyoming

Anderson Associates C-Cube Microsystems 270 South Main #108 Bountiful. UT 84010 phone: 801-292-8991 fax: 801-298-1503


Canada

British Columbia

Thorson Company Northwest 12340 N.B. 8th Street Bellewe. W A 98005 phone:2~55-9180 fax: 2~55-9185

Alberta

Thorson Company Northwest 12340 N.B. 8th Street Bellewe. W A 98005 phone: 206-455-9180 fax: 206-455-9185

Saskatchewan

Electrosource 230 Galaxy Blvd. Rexdale. ONT Canada M9W 5R8 phone: 416-675-4490 fax: 416-675-6871

C-Cube Microsystems

Ontario

Electrosource 230 Galaxy Blvd. Rexdale. ONT Canada M9W 5R8 phone: 416-675-4490 fax: 416-675-6871

Electrosource 340 March Road. Suite 503 Kanata,ONT Canada K2K2E4 phone: 613-592-3214 fax: 613-592-4256

Quebec

Electrosource 6600 Trans Canada Highway. Suite 420 Pointe Claire. Quebec H9R4S2 phone: 514-630-7486 fax: 514-630-7421

Pacific

Kubota C-Cube Inc. Yokohama Business Park East Tower, 12th Floor 134 Goudo-cho, Hodogaya-ku Yokohama-city Japan, 240 phone: (81) 45-336-6550 fax: (81) 45-336-6551

MEMEC Asia Pacific (Rep/Dist.) 4th Floor Myungdang Bldg. 152-62 Sarnsung-Dong Kangnarn-Ku Seoul Korea phone: (82) 2 563-5277 fax: (82) 2 563-5279

MEMEC Asia Pacific(Rep) 14F-l, 171 Section 58 Min Sheng East Road Hai Hwa Building Taipei Taiwan phone: (886) 2 760 2028 fax: (886) 2 765-1488

Europe

NEWTEK (ReplDist.) 8, rue de l'Esterel SILIC 583 94663 Rungis Cedex France phone: (33) 1-46.87.22.00 fax: (33) 1-46.87.80.49

International Representatives and

Distributors

Jung Tai Electronic Co. Ltd. (Dist.) 47 Park Ave. II, Suite 104 Science-Based Industrial Park Hsinchu Taiwan 30077, R.O.C. phone: (886) 2 762 8102 fax: (886) 2 762-3259

ALLY, Inc. (Dist.) 7F, 18, Alley 1 Lane 768, Sec. 4 Pa Teh Rd., Taipei, Taiwan, R.O.C. phone: (886) 2 788-6270 fax: (886) 2 786-3550

MEMEC Asia Pacific (Rep) 10 Anson Rd., #14 -02, Int'l Plaza Singapore 0207, Singapore phone: (65) 222-4962 fax: (65) 222-4939

Serial System Marketing (Rep/Dist.) 11 Jalan Mesin Standard Industrial Bldg, #06-00 Singapore 1336 phone: (65) 280-0200 fax: (65) 286-6723

Kudos Thame Ltd. (ReplDist.) 55 Suttons Park, London Rd. Reading, BERKS RG6 lAZ United Kingdom phone: (44) 734-351010 fax: (44) 734-351030

MEMEC Asia Pacific (Rep/Dist.) Unit No 2520-2525 Tower 1 Metroplaza Ring Fong Road Kwai Fong, N.T., Hong Kong phone: (852) 410-2780 fax: (852) 418-1600

ZA TEK Components Pty Ltd. (ReplDist.) Suite 8, 1059 Victoria Rd. West Ryde 2114 Sydney, Australia phone: (61) 2-874-0122 fax: (61) 2-874-6171

Metronik GmbH (ReplDist.) Leonhardsweg 2 8025 Unterhaching Germany phone: (49) 89-61108-0 fax: (49) 89-6116858

International Representatives and Distributors

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