Bus Serialization for Reducing Power Consumption
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1 Bus Serialization for Reducing Power Consumption Naoya Hatta † , Niko Demus Barli †† ,Chi taka Iwama † , Luong Dinh Hung † ,Daisuk e Tashiro † , Shuichi Sakai † , Hidehiko Tanaka ††† † University of Tokyo †† Texas Instruments Japan ††† Institute of Information Security
description
Bus Serialization for Reducing Power Consumption. Naoya Hatta † , Niko Demus Barli †† ,Chitaka Iwama † , Luong Dinh Hung † ,Daisuke Tashiro † , Shuichi Sakai † , Hidehiko Tanaka ††† † University of Tokyo †† Texas Instruments Japan ††† Institute of Information Security. Introduction. - PowerPoint PPT Presentation
Transcript of Bus Serialization for Reducing Power Consumption
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Bus Serialization for Reducing Power Consumption
Naoya Hatta†, Niko Demus Barli††,Chitaka Iwama†, Luong Dinh Hung†,Daisuke Tashiro†,Shuichi Sakai†, Hidehiko Tanaka†††
† University of Tokyo†† Texas Instruments Japan
††† Institute of Information Security
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Introduction
• Wiring power consumption is an important issue on VLSI design
• SoC and Chip Multiprocessor require buses with long wires
• Bus serialization for reducing bus power consumption
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Outline
• Proposition– Objective– Bus Serialization– Layout Optimization
• Evaluations
• Conclusion
• Future Works
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Proposition
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Objective
T = M fT: ThroughputM: The number of wiresf: Bus frequency
P: Powera: ActivityC: Bus capacitanceV: Voltage swing
Throughput must not decrease
We want to reduce Power
P = a T C V2
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Bus Serialization
Low power and
high frequency
Reduce bus capacitance - by decreasing the number of wires
Latch LatchWire
Conventional Bus
Serializer Deserializer
Wire
Serialized Bus
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Layout Changes
• The number of wires (M) decreases
• Wire resistance (R) decreases
• Wire capacitance (C) decreases
PitchPitch
Without increasing area
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Parameters Change
T = M f
• M decreases Require higher f - for remaining T
• R, C decrease
f 1 / R C∝f increases
P = a T C V2
• C decreasesPower decreases
Objective
Meet the requirement ?
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0
20
40
60
80
100
120
140
Wire Width
Rat
io to
Con
vent
iona
l Bus
[%]
CRT
Layout Optimization
T > 100 %
Minimum C(=Minimum P)
Best width
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Why power decreases?
C C / 2
f 2 f
P = f C V2
Power doesn’t decrease?
C C / 2
f 2 f
P = M f C V2
Power decreases!
M M / 2
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Evaluation
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Condition
• Bus Specification– Bus width: 64bit– The number of wires (conventional): 64– The number of wires (serialized): 32
• Wire Configurations (width, height, etc…)– From International Technology Roadmap for
Semiconductor 2002• Bit pattern
– Address bus and data bus between L1 cache and L2 cache• L1 cache (data/inst) :16KB, 2way, 64byte block
– SPECint95 benchmark• Compare to conventional (fully parallel) bus
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Bus Capacitance
0
20
40
60
80
100
120
45 65 70 80 90 100 115 130
Technology [nm]
Bus
Cap
acit
ance
Rat
io t
oC
onve
ntio
nal B
us [
%]
The effect of serialization increasesas gate length shrinks
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Bus Power Consumption
0
50
100
150
200
250
300
45 65 70 80 90 100 115 130
Technology [nm]
Bus P
ower
Rat
io to
Con
vent
iona
l Bus
[%]
AddressData
Power decreases by 34%
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Why Power Increases?
• The number of transitions increases by serialization
• When the same bit pattern is transferred every cycle, extra transition occurs.
• In address bus, this situation frequently appears.
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0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
Conventional Bus
Serialized BusPower is consumedExtra Transition
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Differential Data Transfer (DDT)
• Transfer the difference between present data and previous data
0010011010
0010011011
0010011100
0010011010
0000000001
0000000111
Normal DDT
0010011010
0010011011
0010011100
Bit Pattern
Extra Transition doesn’t occurExtra Transition occurs
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Bus Power Consumption (DDT)
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60
80
100
120
140
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45 65 70 80 90 100 115 130
Technology [nm]
Bus
Pow
er R
atio
to
Con
vent
iona
l Bus
[%
]
AddressData
Power decreases by 27%
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Comparison
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50
100
150
200
250
45 65 70 80
Technology [nm]
Bus
Pow
er R
atio
[%
]
Address Address (DDT)Data Data (DDT)
• DDT is useful in Address.
• In Data, not useful
• In 45 nm technology, power decreases by about 30%
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Power of Peripheral Circuits
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0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Wire Conventional Bus(Peripherals)
Serialized Bus(Peripherals)
Cur
rent
Per
One
Tra
nsit
ion
[pA
]
180nm processWire length: 5mm
The additional power of peripheral circuits is
2% of the power consumed by wire
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Conclusion
• Normal serialized bus is proper to data bus
• Serialized bus with DDT is proper to address bus
• Bus serialization technique decreases power consumption by 30% of conventional in 45nm process
• As gate length shrinks, Bus serialization becomes more effective
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Future Works
• Apply to Chip Multiprocessor– Between L1 cache and L2 cache
• Additional costs of DDT– Additional circuits and delay
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Capacitance Model
CLdown
CC CC
T
W
S
H
CLup
Layer 3
Layer 1
Layer 2 Metal line
Dielectric layer
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Power increasing by DDT
10001000
10101010
10101010
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Bus Power Model
DriverCL (Load Capacitance)
DriverCL (Load Capacitance)
CC (Coupling Capacitance)
Wire 1
Wire 2
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Additional Delay
• Conventional bus: 0.17ns
• Serialized bus: 0.15ns
