Bus Interfaces and Standards - McGill University
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Bus Interfaces and Standards Bus Interfaces and Standards Zeljko Zilic Zeljko Zilic
Transcript of Bus Interfaces and Standards - McGill University
Bus Interfaces and Standards Bus Interfaces and Standards
Zeljko ZilicZeljko Zilic
OverviewOverview
q Principles of Digital System Interconnect
q Modern bus Standards: l PCI, AMBA, USB
q Scalable Interconnect: Infiniband
q Intellectual Property (IP) Reuse
q Reusable Design
q Principles of Digital System Interconnect
q Modern bus Standards: l PCI, AMBA, USB
q Scalable Interconnect: Infiniband
q Intellectual Property (IP) Reuse
q Reusable Design
System Buses/BackplanesSystem Buses/Backplanes
q Systematic way to create extendible and open hardware systemsl Also: to reduce prices, reuse designs, reach market
q Standardization: the keyl Industry associations (USB, PCI)l Standardization bodies (IEEE488, Firewire)
q Standard content:l Physical, Mechanical, Electrical and Logical
q Example: PC Platform l PCI, ISA, USB, RS232, SCSI, IDE, Ethernet, V.52,
VGA, Rambus, Infiniband, AGP
q Systematic way to create extendible and open hardware systemsl Also: to reduce prices, reuse designs, reach market
q Standardization: the keyl Industry associations (USB, PCI)l Standardization bodies (IEEE488, Firewire)
q Standard content:l Physical, Mechanical, Electrical and Logical
q Example: PC Platform l PCI, ISA, USB, RS232, SCSI, IDE, Ethernet, V.52,
VGA, Rambus, Infiniband, AGP
Bus PrinciplesBus Principles
q Quick and fair access to shared resourcesl Bus (Interconnect), Memory, IO, Processors
q Example:
PC Platform
q Quick and fair access to shared resourcesl Bus (Interconnect), Memory, IO, Processors
q Example:
PC Platform
Bus RealizationsBus Realizations
q Shared interconnect l Bus, Crossbar, Ring
q Signalling lines used for exchanging info, control of the accessl Arbitration: fair bus accessl Handshake: managing transfersl Address, data linesl Error, reset, watchdog
q Shared interconnect l Bus, Crossbar, Ring
q Signalling lines used for exchanging info, control of the accessl Arbitration: fair bus accessl Handshake: managing transfersl Address, data linesl Error, reset, watchdog
Synchronous vs. AsynchronousSynchronous vs. Asynchronous
q Original buses: asynchronous handshakel VME, IEEE 488, SCSI 1 (but not SCSI 3)
q Example of async. handshake
q Original buses: asynchronous handshakel VME, IEEE 488, SCSI 1 (but not SCSI 3)
q Example of async. handshake
Synchronous busSynchronous bus
q Virtually all modern buses
q Transactions relative to positive clock edge
q Virtually all modern buses
q Transactions relative to positive clock edge
ArbitrationArbitration
q Arbitration for accessing bus
l Centralized
l Decentralized
q Arbitration for accessing bus
l Centralized
l Decentralized
PCI BusPCI Bus
q Dominant standardl Not only PCs, but also communication
systems, embedded systems
q Organization:
q Dominant standardl Not only PCs, but also communication
systems, embedded systems
q Organization:
PCI Signalling LinesPCI Signalling Lines
q 32-bit multiplexed Address/Data bus
q 4-bit command field – transaction type/byte enable
q Handshaking
q Error, reset, clock
q Extension: 64 bits
q Testing interface (JTAG)
q 32-bit multiplexed Address/Data bus
q 4-bit command field – transaction type/byte enable
q Handshaking
q Error, reset, clock
q Extension: 64 bits
q Testing interface (JTAG)
PCI TransactionsPCI Transactions
q Read:l Send addressl Turn around the
busl Get data
q Write: l Send addressl Send data
q Notice use of RDY and SEL signals
q Single-cycle turnaround
q Read:l Send addressl Turn around the
busl Get data
q Write: l Send addressl Send data
q Notice use of RDY and SEL signals
q Single-cycle turnaround
AMBA OverviewAMBA Overview
q AMBA Bus Basics
q AMBA Signals
q AMBA High Performance (AHB) Specification
q Timing Diagrams
q Testing Interface
q AMBA Bus Basics
q AMBA Signals
q AMBA High Performance (AHB) Specification
q Timing Diagrams
q Testing Interface
Introduction to AMBA BusIntroduction to AMBA Bus
q Acorn RISC Machine – ARMl Processor for Acorn home computerl Acorn filed for bankruptcy – ARM reinvented
q ARM – leading embedded microprocessorl Licensed to all ASIC houses for SoCl Produced by Intel (formerly by DEC) - StrongARM
q Advanced Microcontroller Bus Architecture l Specification by ARM, open to othersl Several bus standards
q Acorn RISC Machine – ARMl Processor for Acorn home computerl Acorn filed for bankruptcy – ARM reinvented
q ARM – leading embedded microprocessorl Licensed to all ASIC houses for SoCl Produced by Intel (formerly by DEC) - StrongARM
q Advanced Microcontroller Bus Architecture l Specification by ARM, open to othersl Several bus standards
AMBA ConceptsAMBA Concepts
q 3 Ways of creating buses:l Tri-state (internal tri not available in some ASICs)
l Multiplexer-bus
l OR-bus (with “AND” gate enablers)
q 3 Standardsl Advanced High Performace Bus (AHB)
l Advanced System Bus (ASB)
l Advanced Peripheral Bus (APB)
q Recommendations: use AHB
q 3 Ways of creating buses:l Tri-state (internal tri not available in some ASICs)
l Multiplexer-bus
l OR-bus (with “AND” gate enablers)
q 3 Standardsl Advanced High Performace Bus (AHB)
l Advanced System Bus (ASB)
l Advanced Peripheral Bus (APB)
q Recommendations: use AHB
AHB AMBA BusAHB AMBA Bus
q No physical level standard (any voltage/technology)l Suited for SoC – synthesized designs from HDL
q High clock rateq Pipelined accessq Multiple bus mastersq Burst transfersq Split transactionsq Separate read and write buses
q No physical level standard (any voltage/technology)l Suited for SoC – synthesized designs from HDL
q High clock rateq Pipelined accessq Multiple bus mastersq Burst transfersq Split transactionsq Separate read and write buses
AMBA ImplementationAMBA Implementation
q Arbiter and global decoders: standalone
q Add-on components: master or slave
q Interface: added to add-on components
q Arbiter and global decoders: standalone
q Add-on components: master or slave
q Interface: added to add-on components
MAIN BUS CONTROLLER:ARBITER AND DECODER
MAIN BUS CLOCK DOMAIN
MASTER INTERFACE
SLAVE INTERFACE
SLAVE DEVICE #1
MASTER DEVICE #1
M_IN M_OUT
S_IN S_OUT
MASTER DEVICE #1 CLOCK DOMAIN
SLAVE DEVICE #1 CLOCK DOMAIN
AMBA SignalsAMBA Signals
Input: Comment: HGRANT A master gets control of bus when HGRANT is high and HREADY is high. HREADY Receives HREADYOUT signal from active slave indicating wait states or
completion. HRESP[1:0] Response from slave indicating status of transfer. HRDATA[15:0] Read data to master.
Output: Comment: HBUSREQ Must be maintained high during a burst of undefined length. HTRANS[1:0] Transfer state, must give IDLE if nothing to transfer: a master may be selected if no
masters want the bus. HADDR[15:0] Target address for transfer. HWRITE Write transaction when high and read when low. HSIZE[1:0] Size of transfer: 01 is 16 bits. Only 16 bits supported. HBURST[2:0] Burst type: 000 is single, 001 is unspecified length burst, others are 4, 8 and 16 beat
bursts (wrapping or non-wrapping). HWDATA[15:0] Write data from master.
Bus Signals - MasterBus Signals - Master
type AHB_Mst_In_Type is record
HGRANT
HREADY
HRESP[1:0]
HRDATA[15:0]
end record;
type AHB_Mst_Out_Type is record
HBUSREQ
HTRANS[1:0]
HADDR[15:0]
HWRITE
HSIZE[1:0]
HBURST[2:0]
HWDATA[15:0]
end record;
Bus Signals - SlaveBus Signals - Slave
type AHB_Slv_In_Type is record
HSEL
HADDR[15:0]
HWRITE
HTRANS[1:0]
HSIZE[1:0]
HBURST[2:0]
HWDATA[15:0]
HREADY
end record;
type AHB_Slv_Out_Type is record
HREADYOUT
HRESP[1:0]
HRDATA[15:0]
end record;
Bus Transactions- SingleBus Transactions- Single
HCLK
HBUSREQ
HGRANT
HTRANS
CONTROL*
HRDATA
HWDATA
HREADY
SINGLE TRANSACTION (MASTER SIGNALS)1 2 3 4 5 6
HADDR
7
A
NONSEQ
* CONTROL: HBURST, HWRITE, HSIZE
Control for A
A
A
HRESP OKAY
Single TransactionSingle Transaction
Clock 1: Master has a transfer to accomplish so the HBUSREQ is asserted. Also note that the address and control info has to be driven as well.
Clock 2: Bus controller sees the request and is able to grant the bus.
Clock 3: Master sees the grant and knows that the next cycle will clock address to slave. The HBUSREQ is deasserted because grant was seen. Also note that the bus controller uses this sampling point to determine the transaction type and control.
Clock 4: This is the edge on which the slave samples the address and prepares for the data phase. The bus controller deasserts the HGRANT because it is given to another master. On the bus controller side, the 2nd masters address phase would go out to the slaves between clock 6 and 7.
Clock 5: The slave is not ready to give read data or accept write data so itdeasserts the HREADY signal (wait state). It is not a problematic situation so the HRESP is OKAY.
Clock 6: HREADY is asserted so the data is sampled.
Clock 1: Master has a transfer to accomplish so the HBUSREQ is asserted. Also note that the address and control info has to be driven as well.
Clock 2: Bus controller sees the request and is able to grant the bus.
Clock 3: Master sees the grant and knows that the next cycle will clock address to slave. The HBUSREQ is deasserted because grant was seen. Also note that the bus controller uses this sampling point to determine the transaction type and control.
Clock 4: This is the edge on which the slave samples the address and prepares for the data phase. The bus controller deasserts the HGRANT because it is given to another master. On the bus controller side, the 2nd masters address phase would go out to the slaves between clock 6 and 7.
Clock 5: The slave is not ready to give read data or accept write data so itdeasserts the HREADY signal (wait state). It is not a problematic situation so the HRESP is OKAY.
Clock 6: HREADY is asserted so the data is sampled.
Back-to-Back TransactionBack-to-Back Transaction
HCLK
HBUSREQ
HGRANT
HTRANS
CONTROL*
HRDATA
HWDATA
HREADY
SINGLE TRANSACTIONS BACK-TO-BACK (MASTER SIGNALS)1 2 3 4 5 6
HADDR
7
* CONTROL: HBURST, HWRITE, HSIZE
A
B
HRESP
CONTROL FOR A
NONSEQ
A
A
OKAY
NONSEQ
CONTROL FOR B
B
B
OKAY
Burst TransactionBurst Transaction
HCLK
HBUSREQ
HGRANT
HTRANS
CONTROL*
HRDATA
HWDATA
HREADY
FIXED LENGTH BURST TRANSACTION (MASTER SIGNALS)1 2 3 4 5 6
HADDR
7
* CONTROL: HBURST, HWRITE, HSIZE
A
HRESP
A
OKAY
A+2
A+2
A+2
SEQ
A+4
A+4
A+6
A+6
OKAY OKAY OKAY
A+4
SEQ
A+6
SEQ
A
NONSEQ
CONTROL FOR BURST
Undefined Length BurstUndefined Length Burst
HCLK
HBUSREQ
HGRANT
HTRANS
CONTROL*
HRDATA
HWDATA
HREADY
UNDEFINED LENGTH BURST TRANSACTION (MASTER SIGNALS)1 2 3 4 5 6
HADDR
7
* CONTROL: HBURST, HWRITE, HSIZE
A
HRESP
A
OKAY
A+...
SEQ
OKAY OKAY OKAY
A+n-1
SEQ
A+n
SEQ
A
NONSEQ
CONTROL FOR BURST
A+...
A+...
A+n-1 A+n
A+n-1 A+n
Single Transaction - SlaveSingle Transaction - Slave
HCLK
HSEL
HTRANS
CONTROL*
HRDATA
HWDATA
HREADYOUT
SINGLE TRANSACTION (SLAVE SIGNALS)1 2 3 4 5 6
HADDR
7
* CONTROL: HBURST, HWRITE, HSIZE
A
HRESP OKAY
HREADY
A
NONSEQ
CONTROL FOR A
A
AMBA Test InterfaceAMBA Test Interface
q Standardized test interfacel Allows testing of modules in isolation
l Test using only bus transfers
l Requires no interaction with other system elements
l IO pins are not directly connected to bus
q Standardized test interfacel Allows testing of modules in isolation
l Test using only bus transfers
l Requires no interaction with other system elements
l IO pins are not directly connected to bus
Test Interface Controller (TIC)Test Interface Controller (TIC)
q 3 Control signalsl Test request
A/B
l Test Acknowledgement
q 16 bit test bus
q 3 Control signalsl Test request
A/B
l Test Acknowledgement
q 16 bit test bus
Test Control SignalsTest Control Signalsq During test modeq During test mode
Enter Test mode request001
Test mode entered1--
Exit test mode100
Read vector110
Write vector101
Address vector or turnaround vector
111
Current access incomplete0--
DescriptionTACKTREQBTREQA
TIC OperationTIC Operation
q TREQA used to initialize the test
q TACK should remain High throughout the test
q Read vectors are followed by two turnaround vectors to ensure the completion of the transfer
q TREQA used to initialize the test
q TACK should remain High throughout the test
q Read vectors are followed by two turnaround vectors to ensure the completion of the transfer
Writing Test VectorsWriting Test Vectors
Reading Test ResultsReading Test Results
Infiniband OverviewInfiniband Overview
q New switched fabric proposal: trade association (PC)
q Goal: provide extensive IO bandwidth for servers
q Scalability
q Performance
q Reliability, Availability, Serviceability
q New switched fabric proposal: trade association (PC)
q Goal: provide extensive IO bandwidth for servers
q Scalability
q Performance
q Reliability, Availability, Serviceability
Infiniband - ConceptsInfiniband - Concepts
q A System Area Network(SAN)
q Unified Fabric for use between elements of computer systems
q Independent of the Host Operating System (OS)
q A System Area Network(SAN)
q Unified Fabric for use between elements of computer systems
q Independent of the Host Operating System (OS)
The Switched FabricThe Switched Fabric
q Links
q Switches
l Routes packets based on destination Local ID and service level within a subnet
q Routers
l Routes packets based on Global ID to different subnets
q Links
q Switches
l Routes packets based on destination Local ID and service level within a subnet
q Routers
l Routes packets based on Global ID to different subnets
Infiniband Architecture ModelInfiniband Architecture Model
Infiniband Host ArchitectureInfiniband Host Architecture
q Connects memory controller to fabric through one or more links
q Provides work queues for posting work requests
q Manages transport functions
q Supports memory translation and protection
q Connects memory controller to fabric through one or more links
q Provides work queues for posting work requests
q Manages transport functions
q Supports memory translation and protection
CommunicationCommunication
q Queuing:- Foundation of IBA
operations- Ability of a consumer to
queue up a set of instructions that the hardware executes.
q Queuing:- Foundation of IBA
operations- Ability of a consumer to
queue up a set of instructions that the hardware executes.
Communications StackCommunications Stack
q Overviewq Overview
2. Request translated into WQE by the CA and it is put into “send stack” of QP
1. Host sends a request to the remote consumer
3. Request packet passes through transport, network, link & physical layers
4. Request reaches the “receive stack” of the remote consumer where packets are reassembled & checked for validation
5. Depending on QoS, the remote can either send or not send an ACK signal back to the host
IBA Layered ArchitectureIBA Layered Architecture
ConclusionsConclusions
q System buses: means to realize open and extendible systems
q Bus basics
q Modern standards: PCI, AMBA, Infiniband
q Design and test issues
q System buses: means to realize open and extendible systems
q Bus basics
q Modern standards: PCI, AMBA, Infiniband
q Design and test issues
