Bus Interface

Bus interfaces

AMBA based system architecture

Avalon bus based system

Core Connect bus based system

IBM CoreConnect

5© 2008 Sudeep Pasricha & Nikil Dutt

•PLB• Pipelined• Burst modes• Split transactions• Multiple masters

•OPB• Low bandwidth• Burst mode• Multiple Masters

•DCR• Low throughput• 1 r/w = 2 cycles• Ring type data bus

ST Bus interconnect

Possible wishbone interconnections

Sonics Smart Interconnect

• Consists of 3 synchronous bus-based interconnect specifications– SonicsMX

• high performance interconnect fabric– SonicsLX

• high performance interconnect fabric, but with less advanced features

– Synapse 3220• peripheral interconnect designed to connect slower

peripheral components


SonicsMX

• High performance synchronous bus fabric– Pipelined, non-blocking, multi-threaded communication support– Split/outstanding transactions for high performance– Configurable data bus width: 32, 64, or 128 bits– Socket-based connection support, using native OCP 2.0 interface– Bandwidth and latency-based arbitration schemes to obtain desired

quality of service (QoS) for threads– Register points (RPs) for pipelining long interconnects and providing

timing isolation– Protection mode support– Advanced error handling support– Fine-grained power management support


SonicsMX Topology• SonicsMX supports full crossbar, partial crossbar,

and shared bus topology


SonicsMX Arbitration• Weighted QoS

– available bandwidth distributed among masters based on ratio of bandwidth weights configured for each master

• Priority QoS – extends bandwidth-based scheme above

• 1-2 threads are assigned a static priority (guaranteed service)• Other threads assigned bandwidth weights (best effort)

• Controlled QoS– dynamically switches between three arbitration schemes based on

traffic characteristics• Static priority (guaranteed service)• Bandwidth weighted scheme (best-effort)• Guaranteed Bandwidth allocation (guaranteed service)


STBus

• Consists of 3 synchronous bus-based interconnect specifications– Type 1

• Simplest protocol meant for peripheral access– Type 2

• More complex protocol• Pipelined, SPLIT transactions

– Type 3• Most advanced protocol• OO transactions, transaction labeling/hints


Type 1• Simple handshake mechanism• 32-bit address bus• Data bus sizes of 8, 16, 32, 64 bits• Similar to IBM CoreConnect DCR bus


Type 2• Supports all Type 1 functionality• Pipelined transfers• SPLIT transactions• Data bus sizes up to 256 bits• Compound operations

– READMODWRITE• Returns read data and locks slave till same master writes to location

– SWAP• Exchanges data value between master and slave

– FLUSH/PURGE• Ensure coherence between local and main memory

– USER• Reserved for user defined operations


Type 3• Supports all Type 2 functionality• OO transaction completion• Requires only single response/ACK for multiple data

transfers (burst mode)


STBus• All types have

– MUX-based implementation

– Shared, partial or full crossbar implementation


STBus Arbitration• Static priority

– Non-preemptive

• Programmable priority• Latency based

– Each master has register with max. allowed latency (in clock cycles)• If value is 0, master must be granted bus access as soon as it requests it

– Each master also has counter loaded with max. latency value when master makes request

– Master counters are decremented at every subsequent cycle– Arbiter grants access to master with lowest counter value– In case of a tie, static priority is used


STBus Arbitration• Bandwidth based

– Similar to TDMA/RR scheme

• STB– Hybrid of latency based and programmable priority schemes– In normal mode, programmable priority scheme is used– Masters have max. latency registers, counters (latency based scheme)– Each master also has an additional latency-counter-enable bit– If this bit is set, and counter value is 0, master is in “panic state”– If one or more masters in panic state, programmable priority scheme

is overridden, and panic state masters granted access

• Message based– Pre-emptive static priority scheme


I2C Bus

• Used to link micro controller systems• Used as command interface in MPEG2 video

chip• Low cost, easy to implement and moderate

speed.

Structure of I2C Bus system

Electrical inter face of I2C bus

Bus transaction on the I2C bus

Bus Interface

• ISA (Industry Standard Architecture)• VESA local bus

– (Video Electronics Standards Association)• PCI (peripheral component interconnect)• USB (Universal Serial Bus)• AGP (Advanced Graphics Port)

Industry Standard Architecture

ISA• Oldest version• ISA slots are present in main board• 8 bits and 16 bit standards• Extended version of 32 bit• Operates at 8MHz• 8 bit data bus, 20 bit de-multiplexed address bus• I/O and memory control signal• Interrupt lines• DMA channels• Power, reset and misc signals

VESA local bus

VESA

• 33 MHz extension of ISAbus• High speed data transfer applications• 32 bit address and data bus• Used for video and disk interfaces• Require third connector to be added behind

the standard 16 bit connector

PCI Bus

PCI

• 64 bit data bus• Contain series of registers, located in a small

memory device that contain information about the board.

• The information in this registers allow the computer to automatically configure the PC card

• Microprocessor connects to the PCI bus through an IC called PCI bridge

• 32 or 64 bit address and data bus.

Bus system structure

PCI Bus commands• INTA Sequence: Get the interrupt vector from the interrupt controller. The

interrupt vector byte is returned during a read operation.• Special Cycle: Used to transfer data to all PCI components, e.g. processor

shutdown.• I/O Read Cycle: Data are read from an I/O device at address AD0-AD15.• I/O Write Cycle: Data are written to an I/O device.• Memory Read Cycle: Data are read from memory device.• Memory Write Cycle: Data are written to memory device.• Configuration Read: Configuration information is read from PCI device• Configuration Write: Configuration information is written to PCI device.• Memory Multiple Access: Multiple data are read from memory device.• Dual Addressing Cycle: Used for transferring data to a 64-bit PCI device

which only contains a 32-bit data path.• Line Memory Access: Used to read more than two 32-bit numbers.• Memory Write with Invalidation: Same as line memory access, but used

with write and bypasses write-back function of the cache.

PCI interface block diagram

USB Plug and USB card for mother board

USB

• Allows access of upto 127 different connections via a 4 wire serial connection.

• Ideal for keyboard, sound card, modem etc.,• Cable lengths are limited to 5 meters• Packet identification byte contains 8 bits right

most 4 bits contains the type of packet that follows.

• Left most 4 bits are the compliment(used for error detection

Accelerated Graphics ports

Bus Interface

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