Building Gates with Diodes

and BJTs

Dr. Bassam Jamil

Introduction

Acknowledgement: Most of the following slides were

adopted from Dr. Anas Al-Trabsheh lecture notes.

Topics

– Basics of logic gates

– Diodes and Diode-Resistor Logic

– BJT

– Resistor-Transistor Logic (RTL)

– Transistor-Transistor Logic (TTL)

– Emitter-Coupled Logic (ECL)

2

Logic Gates

3

Vin1 Vin2 Vout

L L L

L H H

H L H

H H H

Vin1 Vin2 Vout

L L L

L H L

H L L

H H H

Vin Vout

L H

H L

The objective of digital electronics is to “build/implement

logic gates” using basic circuit components.

Recall from digital logic class, the basic logic gates are:

inverter, AND, OR, NAND, NOR.

Inverter OR AND

The Basics of Digital Gate Implementation

4

5

Diodes

onDDD VVI for 0

0for DonDD IVV

V.V onD 70

DV

DI

onDV

DV+ - DI

Allows current to pass in one direction

Piecewise linear model:

Cutoff:

Conducting:

Diode-Resistor Logic

6

Consists only of diodes and resistors

Performs AND and OR logic functions

1. DRL AND gate

VOut

VIn2

VIn1

+VVDC

D2

D1

R1

For OFF"" is 2121 ,ONDDC,in DVVV

"1" :"1" :2&1

HighVVHighV DCOutin

RI

ON

RVVV

OFF

I

InDDC

R

ON

is Dor D eitherwhen

;/

are D and D bothwhen

;0

21

1

21V1 V

2

V

o

L L L

L H L

H L L

H H H

Diode-Resistor Logic

7

2. DRL OR gate

For ON"" is 2121 ,OND,in DVV

"0" :0"0" :2&1

LowVLowV Outin

RI

ON

RVV

OFF

I

ONDIn

R

is Dor D eitherwhen

;/

are D and D bothwhen

;0

21

1

21

V1 V2 Vo

L L L

L H H

H L H

H H H

VOut

VIn2

VIn1

0V

D2

D1

R1

Bipolar Junction Transistor

8

CEV

CI

Saturation

Forward-active

Cut-off

Inverse-active

MODES of operation

1. Cut-off mode:

a) VBE < 0.7 V

b) transistor is off

c) IB=IC=IE=0

2. Forward-active mode:

a) VBE = 0.7 V

b) IE= IB+IC

c) IC = × IB

3. Inverse-active mode

a) VBE = 0.7 V

b) (see next slide)

4. Saturation mode

a) VBE = 0.8 V

b) VCE = 0.2 V

c) IE= IB+IC

d) IC = × × IB

BTJ currents and voltages

9

B

E

C

0BI 0CI

0EI

V

offVBE

7.0

Cut-off Mode

B

E

C

0BI

BF

C

I

I

0

B

E

I

I

1

0

V

FAVBE

7.0

Forward-Active Mode

B

E

C

0BIBFC II 0

CBE III 0

V

SatVBE

8.0

Saturation Mode

B

E

C

0BIBRE II

BRC II 1

V

RAVBC

7.0

Inverse-Active Mode

VSatVCE 2.0

Resistor Transistor Logic (RTL) Inverter

10

Voltage-Transfer Characteristics

OHV

FAVV BEIL

CCOH VV

IHV

)(satVV CEOL

OV

IV

Q(off)

Q(sat)

Edge of saturation

OFFVGNDV BEI For IB=0,IC=0,VO=VCC=VOH

Edge of conduction

FAVGNDV BEI For IB=(VI-VBE(FA))/RB,IC=βFIB,VO=VCC-ICRC

IHI VGNDV For IB=(VI-VBE(sat))/RB

IC=(VCC-VCE(sat))/RC VO=VCE(sat)=VOL

CEV

CCV

BR

CR

OV

IV1Q

RTL : NAND and NOR Gates

11

CCV

1BR

CR

OV

1INV 1Q

2BR

2INV 2Q

BNR

INNV NQ

CCI

CCV

CR

OV1BR

1INV 1Q

2INV

2BR

2Q

CCI

NAND NOR

Diode-Transistor Logic (DTL)

12 FAVV BEIL

CCOH VV

satVV BEIH

IV

Q1(off)

Q1(sat)

FAVONVONVV BEDLDII For

DI is ON,

DL & Q1 are OFF

FAVV BEI ONVFAVV DIBEX

CCOH VV FAVV BEIL

For FAVV BEI

ONVFAVV DLBEX

DI & DL & Q1 are ON (FA)

satVV BEIH

For satVONVONVV BEDLDII

IHI VV

DI is OFF,

DL is ON

Q1 is sat satVV CEOL

satVV CEOL

CEV

CCV

BRCR

OV

IV

1QXV

ID LD

OV

DTL NAND Gate

13

CEV

CCV

BRCR

OV

1INV

1QID LD

2INV

AND Inverter

CCOH VV

If at least one input less than VBE(FA), then Q1 is off. i.e. ICC=0

Transistor-Transistor Logic (TTL) Inverter

14

IV

For ILI VV QI is sat& Q1 is FA

VVIH 6.0

Q1(sat) For satVsatVVV ICEBEIHI ,1,

Q1 is sat satVV CEOL satVV CEOL

OVOV

CCV

BRCR

OV

IV1Q

IQ

BI

VVIL 5.0

CCOH VV Q1(off)

satVFAVVV ICEBEILI ,1, For For typical values of RB, IB is in mA, QI is sat. B

IIBECC

BR

VVVI

,

CCOH VV ILICEBE VsatVV ,1,

BE of QI is forward-biased

Q1 is cut-off

IHI VV For BE of QI is reverse-biased

Inverse-active mode (RB)

DTL vs. TTL

15

OV

CCV

BRCR

OV

IV1Q

IQ

BI

CEV

CCV

BRCR

OV

IV

1Q

The input and level-shifting diodes are replaced by QI

The QI BJT requires less area than the two diodes

TTL NAND Gate

16

CCOH VV

satVV CEO

If at least one input is less than VIL, then the Q1 is off.

Multiple-emitter BJT requires much less chip area than using individual transistors for each

input

OV

CCV

BRCR

OV

1INV1Q

IQ

BI

2INV

INKV

If all inputs are greater than VIH, then the Q1 is sat.

Emitter-Coupled Logic (ECL)

17

Emitter-Coupled Logic (ECL)

The BJTs in ECL circuits do not operate in saturation mode, but either in cut-off or forward-active modes

The ECL circuits are the fastest switching time of commercially digital circuits.

Typical propagation delay times are on the order of 1ns, allowing for clock frequencies up to 1GHz.

However, ECL circuits have the highest power dissipation of all logic families, typically 25mW per gate.

Basic ECL Current Switch

18

BBV

CIR

IVIQ RQ

CRR

INVV

Inverting

NINVV

Non-Inverting

EEI

EEV

CCV

This figure shows an ideal BJT current switch

The input is at the base of QI , and VBB is a constant reference voltage

The coupled emitters are ideally connected to a constant current source IEE.

BBI VV OFF is IQ High is INVV

FA is RQ Low is NINVV

BBI VV FA is IQ Low is INVV

OFF is RQ High is NINVV

Resistor EC Current Switch

19

BBV

CIR

IVIQ RQ

CRR

INVV

Inverting

NINVV

Non-Inverting

REI

EEV

CCV

This figure shows an early ECL implementation

EV

ER

E

EEERE

R

VVI

Outputs are taken at the collectors of QI and QR.

CIICCCICINVO RIVVVV ,,1,

CRRCCCRCNINVO RIVVVV ,,2,

and

BBI VV OFF is IQ CCINV VV

CRRCCCNINV RIVV ,

BBI VV FA is IQ CIICCCINV RIVV ,

CCNINV VV

ECL NOR/OR Gate

20

BBV

CIR

1IV

1IQ RQ

CRR

NORVORV

REI

EEV

CCV

EV

ER

Adding additional input transistors with coupled collectors and coupled emitters to the ECL current switch: VINV becomes NOR output and VNINV becomes OR output. For any high-state input, the corresponding transistor is forward-active and then the corresponding collector current flows through RCI and

2IV

2IQ

LowRIVVV CIICCCINVNOR ,

If all inputs are low, then all the corresponding transistors are cut-off and then

HighVVV CCINVNOR

HighVVV CCNINVOR

LowRIVVV CRRCCCNINVOR ,