Buffers
description
Transcript of Buffers
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Buffers
• Buffer: Doesn’t change the input. Only amplifies.
in out
EN
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Three-State Buffers
Buffer output has 3 states: 0, 1, ZZ stands for High-Impedance Open circuit
EN = 0 out = Z (open circuit)
EN = 1 out = in (regular buffer)
in out
EN EN in out
0 X Z
1 0 0
1 1 1
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Three-state buffer(BUF)/inverter(INV) symbols
in out
EN
in out
EN
in out
EN
in out
EN
3-state BUF, EN high
3-state BUF, EN low 3-state INV, EN low
3-state INV, EN high
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Open Collector/Drain Gates
Outputs of two (or more) gates must not be wired together:
A
B
out
wired
If A = B out = A = B
If A B a large enough current
can be created, that causes excessive heating and could damage the circuit.
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Multiplexed output lines using three-state buffers
A
B
out
ENA
ENB
S
S A B ENA ENB out
0 0 0 1 0 0
0 0 1 1 0 0
0 1 0 1 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 1 0 1 1
1 1 0 0 1 0
1 1 1 0 1 1
A
B
A
B
S
out0
1
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Open Collector/Drain Gates
Outputs of some gates can be wired: The result: O1 AND O2
Open Collector Gates in TTL Technology Open Drain Gates in CMOS Technology
A
B
Out =
O1
O2
O1 . O2
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Open Collector/Drain Gates
Open Collector (Open Drain) NAND Truth Table:
A B F=(A•B)’
0 0 Z
0 1 Z
1 0 Z
1 1 0
• Z (Hi-Z) (Hi-Impedance): As if it is unconnected.
+5 V
F
A B
0 V
Open-collector NAND gate
Pull-up resistor
The gate cannot pull up the output needs a resistor to
pull it up if an input is ‘0’
OD
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Open Collector/Drain Gates
• Wired AND:+5 V
F
A B
0 V
Open-collector NAND gate
Pull-up resistor
If A and B are "1", output is actively pulled lowif C and D are "1", output is actively pulled lowif one gate is low, the other high, then low winsif both gates are "1", the output floats, pulled high by resistorHence, the two NAND functions are AND'd (wired) together!
F
C D
0 V
Open-collector NAND gate
Pull-up resistor
OD
OD
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NAND-Only Implementation Find Sum-of-Product form.
Inventers can be added
Equivalent NAND-only
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NAND-Only Implementation
NAND = AND + NOT
Use Open Collector/Drain NAND Gates:
OD
OD
OD
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Another Method
Instead of finding the circuit for F, find the circuit for F’ in the first stageThen there will be no Inverter at the output
• Wired OR:Open drain/collector gate with active low inputs.
OD
OD
OD