B.Supmonchai Goals of This Chapter · B.Supmonchai July 5, 2005 2102-545 Digital ICs 5 2102-545...

B.Supmonchai July 5, 2005

2102-545 Digital ICs 1

Chapter 11

Timing Issues in Digital Systems

Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory

August 20, 2004; Revised - July 5, 2005

2102-545 Digital ICs Timing Issues in Digital Systems 2

B.Supmonchai

Goals of This Chapter

q Introduction to timing issues in digital design

q Classification of Digital systems

q Impact on performance and functionality

ß Clock Skew

ß Clock Jitter

q Clock-Distribution Techniques


B.Supmonchai

Timing Classifications

q Synchronous systems

ß All memory elements in the system aresimultaneously updated using a globally distributedperiodic synchronization signal (i.e., a global clocksignal)

ß Functionality is ensure by strict constraints on theclock signal generation and distribution to minimizeÿ Clock skew (spatial variations in clock edges)

ÿ Clock jitter (temporal variations in clock edges)


B.Supmonchai

Timing Classifications II

q Asynchronous systemsß Self-timed (controlled) systems

ß No need for a globally distributed clock, but haveasynchronous circuit overheads (handshaking logic,etc.)

q Hybrid systemsß Mesochronous and Plesiochronous Systems

ß Synchronization between different clock domains

ß Interfacing between asynchronous and synchronousdomains




B.Supmonchai

Synchronous System Timing Basics

q Under ideal conditions (i.e., when tclk1 = tclk2)

T ≥ tc-q + tplogic + tsu

thold ≤ tcdlogic + tcdreg

tc-q, tsu,thold, tcdreg

clktclk1 tclk2

D Q

R1Combinational

Logic D Q

R2

In

tc-q, tsu,thold, tcdreg

Maximum Clock Period, T

tplogic, tcdlogic


B.Supmonchai

Clock Uncertainties

PLL

1clockgeneration

2 clock drivers

4 power supply

3 interconnect6 capacitive load

7 capacitivecoupling

5 temperature

q Under real conditions, clock signal can have both spatialand temporal variationsß Systematic (Deterministic) - easy to model and correct for at

design time

ß Random - difficult to model and eliminate


B.Supmonchai

Clock Nonidealitiesq Clock skew, tSK (Pink + Orange)

ß Spatial variation in temporally equivalent clock edges

ß Can be either deterministic or random or both

q Clock jitter (Blue + Orange)

ß Temporal variations in consecutive edges of the clock signal

ß Modulation and random additive noise

ß Short term (cycle-to-cycle) tJS and long term tJL

q Variation of the pulse width

ß Important for level sensitive clocking


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Clk

Clk

tSK

tJS

Clock Skew and Jitter

q Both clock skew and jitter affect the effectivecycle time

q Only clock skew affects the race margin




B.Supmonchai

Distribution of Clock Skew

Earliest occurrenceof Clk edgeNominal – d/2

# of registers

Clk delayInsertion delay

Latest occurrenceof Clk edge

Nominal + d /2

Max Clk skew

d

Negative Positive


B.Supmonchai

Positive Clock Skew

clktclk1 tclk2

delayT

d > 0

d + thold

T + d ≥ tc-q + tplogic + tsu so T ≥ tc-q + tplogic + tsu - dthold + d ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg - d

q Clock anddata flowin the samedirection

D Q

R1Combinational

Logic D Q

R2

In

T + d1

2

3

4


B.Supmonchai

Negative Clock Skew

D Q

R1Combinational

Logic D Q

R2

In

clktclk1 tclk2

delay

T

d < 0

T + d ≥ tc-q + tplogic + tsu so T ≥ tc-q + tplogic + tsu - dthold + d ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg - d

2

1 3

4

T + d

q Clock anddata flowin oppositedirection


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T - 2tjitter ≥ tc-q + tplogic + tsu so T ≥ tc-q + tplogic + tsu + 2tjitter

Jitter directly reduces the performance of a sequential circuit

Clock Jitter

q Jitter causes Tto vary on acycle-by-cyclebasis

clktclk

D Q

R1Combinational

LogicIn

T

-tjitter +tjitter




B.Supmonchai

tclk1 tclk2

d > 0

-tjitter

T ≥ tc-q + tplogic + tsu - d + 2tjitter thold ≤ tcdlogic + tcdreg – d – 2tjitter

Combined Impact of Skew and Jitter

q Constraints on the minimum clock period (d > 0)

D Q

R1Combinational

Logic D Q

R2

In

1

6 12

TT + d


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Note on Clock Skewq For Positive Clock skew: d > 0 improves

performance, but makes thold harder to meet. Ifthold is not met (race conditions), the circuitmalfunctions independent of the clock period!

q For Negative Clock skew: d < 0 degradesperformance, but thold is easier to meet(eliminating race conditions)

q For Skew with Jitter: d > 0 with jitter degradesperformance, and makes thold even harder tomeet. (The acceptable skew is reduced by jitter.)


B.Supmonchai

Clock Distribution Networks

q Clock skew and jitter can ultimately limit theperformance of a digital system, so designing aclock network that minimizes both is important

q In many high-speed processors, a majority of thedynamic power is dissipated in the clocknetwork.

q To reduce dynamic power, the clock networkmust support clock gating (shutting down(disabling the clock) units)


B.Supmonchai

Clock Distribution Factors

q Things to consider

ß Interconnect material used for routing clock

ß Shape of network

ß Clock drivers and buffers used

ß Load on clock lines

ß Rise and fall time of clock (may have to considertransmission line effects as well!!)

ß Skew specifications




B.Supmonchai

Clock Distribution Techniques

q Balanced paths (H-tree network, matched RCtrees)

ß In the ideal case, can eliminate skew

ß Could take multiple cycles for the clock signal topropagate to the leaves of the tree

q Clock grids

ß Typically used in the final stage of the clockdistribution network

ß Minimizes absolute delay (not relative delay)


B.Supmonchai

Clock

Clock

Idlecondition

Gatedclock

Insert clock gating atmultiple levels in clocktree

Shut off entire subtreeif all gating conditionsare satisfied

q If the paths are perfectly balanced, clock skew is zero

H-Tree Clock Network


B.Supmonchai

DEC Alpha 21164 (EV5)q 300 MHz clock (9.3 million transistors on a 16.5x18.1

mm die in 0.5 micron CMOS technology)ß single phase clock

q 3.75 nF total clock loadß Extensive use of dynamic logic

q 20 W (out of 50W) or 40% in clock distribution network

q Two level clock distributionß Single 6 stage driver at the center of the chip

ß Secondary buffers drive the left and right sides of the clockgrid in m3 and m4

q Total equivalent driver size of 58 cm !!2102-545 Digital ICs Timing Issues in Digital Systems 20

B.Supmonchai

Clock Drivers

DEC Alpha 21164




B.Supmonchai

Clock Skew in Alpha Processorq Absolute

skewsmallerthan 90 ps

The critical instruction and execution units all see the clock within 65 ps


B.Supmonchai

Dealing with Clock Skew and Jitterq To minimize skew, balance clock paths using H-tree or

matched-tree clock distribution structures.

q If possible, route data and clock in opposite directions

ß Eliminates races at the cost of performance.

q The use of gated clocks to help with dynamic powerconsumption make jitter worse.

q Shield clock wires (route power lines – VDD or GND –next to clock lines) to minimize/eliminate coupling withneighboring signal nets.


B.Supmonchai

Dealing with Clock Skew and Jitter IIq Use dummy fills to reduce skew by reducing variations

in interconnect capacitances due to interlayer dielectricthickness variations.

q Beware of temperature and supply rail variations andtheir effects on skew and jitter. Power supply noisefundamentally limits the performance of clocknetworks.

B.Supmonchai Goals of This Chapter · B.Supmonchai July 5, 2005 2102-545 Digital ICs 5 2102-545...

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