SOFTWARE DEFECT ORIGINS AND REMOVAL METHODS Capers Jones, Vice
BS Poly Removal Defect Reduction - Linx Consulting · BS Poly Removal Defect Reduction Removal of...
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BS Poly Removal Defect Reduction Removal of edge cluster defects by improving recipe and hardware for backside polysilicon wet etch process
BS Poly Removal Defect Reduction Removal of edge cluster defects by improving recipe and hardware for backside polysilicon wet etch process
Malta, NY
Hong Zhai, Colin Weidner, Dhiman Bhattacharyya, Norberto DeOliveria, and Vincent Sih
TOC
1) Mission: repurposing an existing tool 2) Challenge: gap and performance 3) Approach and methodology 4) Current Result & status 5) Concluding remarks
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Table of contents:
GOTO PC Qual Weekend Abnormality (A good way) Highlights 1. Failed to meet the target > half year. New base line proposed
2. We found 2 quals passed spec 3. Possible root cause needed to be correlated & discovered.
• Assumption base line shift needed to be explained.
Date-wafer
PC
1.0 .75 .5 .25 0
New Proposed Base Line
POR
Weekend
Carefully review this chart
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Date-wafer
PC
1.0 .75 .5 .25 0
Stage of starting manufacture Qualification
Re-Categorize the previous busy chart: (1) All wafer check one by one for history: 88 past runs wfrs.
(2) Red boxed: all new Bare Si wfr.
(3) Black box from one tool family.
(4) Non-boxed from any other tools in chart.
A few runs with controlled parameters
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Controlled Run Controlled ReRun
Date-wafer
PC
1.0 .75 .5 .25 0
(1)Addition Pre Step. (2)Pre Defect measurement. (3)Process Step. (4)POST Defect measurement. (5)Additional Steps, like SEM etc
New Step
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SUMMARY REVIEW
What have done •Goto POR •DOI reduction
What to learn •FAB is BIG & sophisticated. •Improvement are all-facet. •Urgency of BIG DATA sorting.
What to proceed •GAPS remain. •Technologies distributions.
Current ER Performance .
Current PC Performance (GOTO only) .
POR
GO
TO
Current PC Performance (POR) .
ER
1.0 .5 0 .5 -1
Date-wafer-unit
Date-wafer-unit
PC 1.0 .75 .5 .25 0
1.0 .75 .5 .25 0
Edge cluster as Pin signature observed!
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Check out this slide again! Two weeks watch after new plan implementation
Date-wafer-unit
PC
1.0 .75 .5 .25 0
Actions taken and still continue…
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Process • Spin speed. • Optimizing opening/closing the A and B chunk pins.
1) Exploring possible water droplets 2) Pins rubbing the wafer?
• A few different things: • - Tool family sequence compare. • - Adjust open/close sequences. • - Perform rinse segmentation. Hardware • Handling and pocket size.
To try: - Adjusting pocket size. - Perform Chuck A/B sequence
Recipe • Current (Rev 12) vs Rev 14 (150% increase spin speed) vs Rev 15 (A-B Dry) options. Pocket size:
• Water is pooling? • 150% increased spin speed test. Chuck Pin Open/Close • Chuck Pin Open/Close vs A/B switching times. • Two chambers showed promising data (reduced pin signature) with the pocket size at optimizing counts. • Change another set of MPCs to different pocket size. • Data that we gathered from these two pocket size.
Path forward:
(1)Pin Signature. GAP to close. (2)Correlation Pin signature with Prod. (3)Yield gain?
Concluding Remarks:
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Summary: • Perform: POR Goto
Process step improve • Pin Signature: Pocket Size
adjustment need address