Bringing Robustness and Power Efficiency to...

Bringing Robustnessand Power Efficiencyto Autonomous Energy-Harvesting MicrosystemsJean-Frederic Christmann, Edith Beigne,

Cyril Condemine, Pascal Vivet, and

Jerome Willemin

CEA-Leti, MINATEC

Nicolas Leblond

Tiempo SAS

Christian Piguet

Swiss Center for Electronics and Microtechnology

� EXTENDING BATTERY LIFE or eliminating the battery

altogether is a key issue in today’s autonomous wireless

microsystems.1 A proposed solution is to harvest en-

ergy from the environment and thereby maximize the

lifespan of autonomous communicating sensors to

avoid any human maintenance. By extracting their en-

ergy from the environment, autonomous devices can

be self-powered over their full lifetimes, an essential

property for applications such as ambient intelligence,

active security, and monitoring.2 In such devices and

applications, energy availability and power dissipation

are not constant over time, so energy management is

crucial in determining the potential for information

processing. A limited amount of extractable energy is

indeed fixed by solar radiation, thermal gradients, or

even device movements. Moreover, the harvester tech-

nologies, such as photovoltaic, Seebeck-effect�based

thermo generators (or even piezoelectrical generators)

provide low efficiencies and remain

under development. For those reasons,

the average harvested energy of these

devices is extremely low.3,4

Asynchronous circuits are well-

suited for the implementation of

energy-harvesting microsystems for sev-

eral reasons. For implementing digital

logic, the intrinsic standby-state and

process-voltage-temperature (PVT)

robustness provided by asynchronous data-driven de-

sign techniques is promising.5 Asynchronous circuits

can be easily supplied at very low voltage levels, and

their smooth current profile due to automatic speed

regulation perfectly meets energy harvester and bat-

tery requirements. Detecting and processing events

is the fundamental behavior of asynchronous cir-

cuits, and energy monitoring is among the main

functions in applications based on energy harvesting.

An energy-harvesting microsystem must indeed be

aware of both available energy and system activity.

By detecting environmental energy changes, the

microsystem can configure the optimal power path

within the architecture to reach the best trade-off be-

tween power and efficiency. (The sidebar ‘‘Related

Work’’ presents other approaches.)

In this article, we propose an autonomous, recon-

figurable, robust energy-harvesting microsystem.

Asynchronous Design

Editors’ note:

Asynchronous circuits are well-suited to ultra-low-power design. This article

presents a microsystem that is powered only by energy extracted from the en-

vironment to implement an autonomous sensing application. Key to this appli-

cation is the use of asynchronous logic, which not only provides greater energy

efficiency due to its event-driven nature but, more importantly, allows graceful

adaptation to highly variable power availability.

��Montek Singh (UNC Chapel Hill) and

Luciano Lavagno (Politecnico di Torino)

0740-7475/11/$26.00 �c 2011 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers84

mdt2011050084.3d 8/9/011 15:17 Page 84

The microsystem, called Managy (for management of

energy), includes an asynchronous dedicated control-

ler with analog-to-asynchronous and asynchronous-to-

analog handshaking interfaces. It features two main

innovations: a fully energy- and data-driven architec-

ture implemented in asynchronous logic and power

path reconfiguration from harvesters to loads.

Managy’s dedicated digital power management allows

either constrained power supply schemes or fully

energy-driven power path configuration. For monitor-

ing applications requiring an ultra-low-power, highly

autonomous node, Managy’s fully asynchronous,

data-driven dedicated controller allows power effi-

ciency optimization by means of power path reconfi-

guration. Moreover, the asynchronous scheme offers

high robustness to voltage variations and a low-energy

wake-up capability. We have fully validated the pro-

posed architecture in a cosimulation flow integrating

analog models and asynchronous logic, and it has

shown up to a 40% gain over traditional architectures.

Energy-harvesting microsystemManagy is an autonomous, wireless multisource

and multisensor node. Its purpose is to extract energy

from the environment to handle monitoring and com-

munication functions. Here we describe the princi-

ples underlying Managy, the system’s asynchronous

control, and the system architecture.

Microsystem principles

The energy-driven architecture detects environ-

mental energy events and translates them into data

events to be sent to the asynchronous controller.

Managy integrates an energy-harvesting platform, a

long-lasting storage device such as a microbattery,

an internal sensor unit based on analog-to-digital

(A/D) converters, and a dedicated digital controller.

The microsystem provides power supply fea-

tures for low-voltage (LV ¼ 1 V) modules, such as

the integrated A/D converters, and higher-voltage

(HV ¼ 1.8 V to 3 V) components, such as commercial

Related Work

The past decade has produced advanced research

and industrial achievements in the field of wireless sen-

sor nodes and networks. This work has mainly focused

on lowering a microsystem’s energy consumption by de-

signing ultra-low-power building blocks, including ana-

log sensor interfaces, RF communication blocks, and

digital control modules. Researchers have used a syn-

chronous commercial off-the-shelf (COTS) microcontrol-

ler (Texas Instruments’ MSP430) to control the duty

cycle between active and sleep mode according to

available energy.1 In another solution, researchers

designed a dedicated state machine without reconfigur-

ability features.2 However, both of these synchronous

implementations require costly phase-locked loops

(PLLs) or clock generation schemes with complex soft-

ware or hardware management of active and idle modes.

Several asynchronous approaches focusing on en-

ergy harvesting have been proposed.3,4 Limited to RF

energy harvesting, these schemes involve a contactless

smart-card chip that integrates a coil connected to a

radio frequency identification (RFID) power reception

system with an asynchronous microcontroller. Thanks

to on-chip asynchronous digital control, these circuits

demonstrate high robustness to voltage variations, very

low power consumption, and reduced area due to their

smaller smoothing capacitance, compared with RFID

synchronous microsystems. Other researchers have

studied new sensor interfaces, with the idea of dynami-

cally adapting sampling frequency to signal variations,

thus decreasing interface circuit activity.5

References1. Y.H. Chee et al., ‘‘PicoCube: A 1cm3 Sensor Node Powered

by Harvested Energy,’’ Proc. ACM/IEEE 45th Design Automa-

tion Conf. (DAC 08), IEEE Press, 2008, pp. 114-119.

2. E. Torres et al., ‘‘SiP Integration of Intelligent, Adaptive, Self-

Sustaining Power Management Solutions for Portable Appli-

cations,’’ Proc. IEEE Int’l Symp. Circuits and Systems

(ISCAS 06), IEEE Press, 2006, pp. 5311-5314.

3. J. Kessels and P. Marston, ‘‘Designing Asynchronous

Standby Circuits for a Low-Power Pager,’’ Proc. IEEE, vol. 87,

no. 2, 1999, pp. 257-267.

4. A. Abrial et al., ‘‘A New Contactless Smart Card IC Using an

On-chip Antenna and an Asynchronous Microcontroller,’’

IEEE J. Solid-State Circuits, vol. 36, no. 7, 2001, pp. 1101-

1107.

5. F. Akopyan, R. Manohar, and A.B. Apsel, ‘‘A Level-Crossing

Flash Asynchronous Analog-to-Digital Converter,’’ Proc. 12th

IEEE Int’l Symp. Asynchronous Circuits and Systems (Async

06), IEEE Press, 2006, pp. 11-22.

85September/October 2011

mdt2011050084.3d 8/9/011 15:17 Page 85

off-the-shelf (COTS) sensors. To avoid extra voltage

conversions, energy storage is performed above

the highest voltage level. Two power paths

supply LV loads. On one hand, sources can directly

supply loads using a direct power path. On the

other hand, an indirect power path goes from sour-

ces to battery and from battery to loads. Further-

more, the direct path scheme can be extended

to HV loads, with a lower gain due to voltage

conversions.

The direct power path is created whenever loads

request power and energy is available through sour-

ces. Available energy on the direct path is for imme-

diate use at high power efficiency. In contrast, the

indirect path stores energy in the battery. This energy

can be used for later needs but at the cost of reduced

efficiency.

Constrained applications would not leverage most

benefits of direct paths. As an example, a device run-

ning during the night and harvesting energy from

solar cells will, most of the time, use stored energy

through the indirect path. Nevertheless, switching to

direct paths presenting good power efficiency is pref-

erable. Total power consumption is thus reduced, and

the system remains functional at low harvested en-

ergy levels. High-level power management is required

to optimize the system’s total power efficiency and

reconfigure the power paths according to environ-

mental changes. Passive components cannot perform

this management easily, so we included a digital con-

troller in the system. The controller provides the con-

trol algorithm for turning on and off the power paths

according to the device energy state and to the appli-

cation task demands.

The Managy architecture targets three main appli-

cation types:

� Always sleeping: The system periodically measures

physical parameters at a frequency defined by the

application. The system is in a sleeping mode

most of the time, so the main issue is leakage cur-

rent. Moreover, energy variations don’t impact the

application schedule.

� Full monitoring: The system keeps aware of its in-

ternal state by measuring at high frequency one

or more physical parameters and can make a de-

cision at any moment. Power consumption is con-

stant even if harvester outputs vary over time.

� Wake-up: The system is in a sleeping mode and

keeps tracking specific external physical events.

The whole system wakes up on a physical event

to achieve a specific task and then goes back to

sleeping mode.

Since the use of the direct power path involves a

correlation of energy variations and availability, this

path is appropriate in full-monitoring applications

and even more so in wake-up applications.

Asynchronous control

By nature, Managy is asynchronously energy- and

data-driven; that is, the system is highly sensitive

to physical events and reacts to those events to

reach an optimum energy point. To efficiently imple-

ment such a system, it was obvious we must use asyn-

chronous logic design techniques. Moreover, a

synchronous design would require the use of an

area-consuming on-chip PLL and limit the controller’s

supply voltage to nominal levels with high current

peaks. Considering both the extra area cost of asyn-

chronous logic implementation versus the low digital

control complexity of the control algorithm, we de-

cided to use a dedicated controller. At a low supply

voltage level, even slower than at a nominal supply

voltage level, asynchronous logic remains functional

and provides a very low leakage current.

Asynchronous circuits use local synchronization,

which replaces global clock signaling. The asynchro-

nous dedicated controller is designed in quasi-delay-

insensitive (QDI) asynchronous logic and imple-

mented in a double-rail coding scheme and a four-

phase handshake protocol.5

With the benefits of QDI asynchronous logic, the

controller gives the system robustness and autonomy.

Because they are data driven, asynchronous circuits

are active only when and where needed. This pro-

vides an automatic sleep mode to the controller

and also reduces global power consumption. The

power consumption in autonomous wireless sensor

nodes (AWSNs) is directly related to the number of

tracked events and to task frequency. The local syn-

chronization scheme distributes activity over time

and over the AWSN sources because batteries are

more robust to a smooth current profile than to high

current peaks. Consequently, we also see less noise

on sensitive power supply lines and fewer electromag-

netic emissions. This scheme thus also reduces para-

sitic effects on external node communications.

Finally, because they are delay insensitive, these

asynchronous circuits are highly robust to supply

Asynchronous Design

86 IEEE Design & Test of Computers

mdt2011050084.3d 8/9/011 15:17 Page 86

voltage variations and more generally to PVT varia-

tions. Asynchronous circuits provide automatic

speed regulation, giving the best compromise be-

tween speed and energy available on the node.

Even if the controller is working slowly, it can still

work at a very low supply voltage, regardless of volt-

age variation due to the amount of available energy

in the microsystem.

By using asynchronous logic, we deliver energy-

driven and data-driven control and solve many issues:

no PLL, low noise, fast wake-up time, low-power idle

mode, and robustness to low voltage supply level.

Thus, we alleviate design constraints and improve

the microsystem’s robustness, autonomy, and power

efficiency, compared with a synchronous solution.

Architecture

Figure 1 shows an overview of the Managy harvest-

ing microsystem architecture. The microsystem

extracts its energy from the environment using vari-

ous energy harvesters. It uses photovoltaic (PV)

cells to extract solar energy6 and thermoelectric gen-

erators (TEGs) to extract energy from thermal gra-

dients.4 It can also use vibratory energy sources

such as electromagnetic generators or piezoelectric

generators,3 as well as RF energy and RFID systems.7

Most COTS components accept a input voltage

range (e.g., 1.8 V to 3 V) and regulate their nominal

supply value within themselves. In contrast, integrated

components supplied at LV level may need a smooth

and constant power supply. Therefore, we use a lith-

ium-metal microbattery (3 V to 3.6 V) as the long-last-

ing storage device. It provides high cyclability

(thousands of cycles without capacity loss), electro-

chemical stability (no self-discharge), and voltage

compliance with the microsystem’s voltage range.

The microsystem implements both direct and indi-

rect power paths for LV and HV loads’ power supply.

Monitoring

Internal loads

LV indirectpath

î Low voltage (< 1V)î Regulated power supply needs

(e.g., A/D converters)

External loads

î High voltage (1.8V–3V)î Internal voltage regulator

(e.g., COTS components)

Digitalcontroller

Application, communication,power, and sensor

management

Energyharvesters

TEG

PV cell

Man

agy++

LV

dire

ct

pat

h

Vib

RF

Controllerpower supply

Analog blocksî Current mergerî Voltage regulator

(e.g., diodes, LDO reg.)

+

Analog blocksî Voltage reducer(e.g., DC/DC buck)

Storagedevice

(e.g., coin cell,microbattery)

++

Batterycharger

++

++Analog blocks

î Voltage boosterî Current merger

(e.g., diodes, DC/DC boost)

+

++

HV direct

Indirect path

path

+

HV

ind

irect

pat

h

–

Figure 1. The Managy harvesting microsystem architecture integrates an energy-harvesting platform,

a long-lasting storage device such as a microbattery, an internal sensor unit based on analog-to-digital

(A/D) converters, and a dedicated digital controller. (TEG: thermoelectric generator; PV: photovoltaic;

Vib: vibratory source.)


mdt2011050084.3d 8/9/011 15:17 Page 87

Figure 1 illustrates these paths with unidirectional

arrows.8 Due to their specific technologies, the sour-

ces deliver very low output voltage levels (a few hun-

dred mV); it is thus mandatory to convert and boost

this voltage to supply any blocks in the microsystem.

First, since the microsystem must be independent

from the number of sources, we used triggered diodes

to merge the current into a unique power path. We

implemented direct power paths using a low-drop-

out (LDO) regulator for LV loads and a voltage

booster for HV loads. The power path from sources

to battery uses this same voltage booster and a battery

charger. The indirect path for HV loads is thus directly

completed, whereas the indirect path for LV loads

needs step-down converters to reduce the voltage.

Energy storage in the battery and extra voltage conver-

sions reduce the indirect power path’s efficiency.

Energy-driven power managementIn response to power path energy variations, the

digital controller reconfigures the power paths: setting

the indirect path by default to provide energy con-

stancy and switching to the direct path whenever en-

ergy is harvested by sources. Managy detects energy

variations by analog comparison of voltage thresh-

olds. To avoid detecting many energy events, the volt-

age comparisons are performed only on high-value

capacitors or on the battery.

Capacitors inserted downstream

from each analog current merger

block (Figure 1) serve as short-

term energy storage. Managy

compares their voltage with

thresholds to generate energy

events. The controller is thus

advised on energy levels for

both LV and HV power paths.

In addition, battery voltage varia-

tions are translated into energy

events and give battery state-of-

charge information.

Based on two data wires and

one acknowledgment wire for

one digital bit signal, the control-

ler’s dual-rail, four-phase, asynchro-

nous QDI logic uses a four-phase

synchronization protocol to estab-

lish a communicating channel be-

tween two digital modules.

Digital power management architecture

The Managy microsystem’s event-driven behavior

relies on asynchronous detection of energy events.

The digital power management architecture mainly

consists of data-driven finite-state machines dedicated

to surveying each voltage path’s energy state. Figure 2

illustrates this architecture and its interface with the

analog part of the microsystem.9 The digital power

management system includes the high- and low-

voltage path handlers, the battery-monitoring mod-

ule, and the timer.

Voltage path handlers. The two voltage path han-

dlers react to energy events that are received on

Int_Low, Int_Med, and Int_High signals for the LV

power path and Ext_High, Ext_Med, and Ext_High sig-

nals for the HV power path. The path handlers are

thus able to follow the current energy level on each

path.

The digital application manager sends power sup-

ply information to these modules using Int_ED,

Int_now, and No_Int signals for the LV power path

and Ext_ED, Ext_now, and No_Ext signals for the

HV power path. Now signals are used to request an

immediate power supply on the concerned power

path. They are useful in applications that are highly

reactive to physical events. ED signals, used for fully

Asynchronous Design

Analog-to-async and async-to-analog interfaces

Low-voltage pathhandler

High-voltage pathhandler

Batterymonitoring

Timer

Application management Core

Analog system

Asynchronous digital controller

Ext

_Hig

h

Ext

_Med

Ext

_Low

Bat

t_he

lp

Cha

rge

SoC

_Eva

l

Bat

t_S

oC

DC

DC

_SR

LDO

_On

Int_

Hig

h

Int_

Med

Int_

Low

Int_

OK

Int_

ED

Int_

now

Ext

_ED

Ext

_now

No_

Ext

Ext

_OK

SoC

Get

_SoC

Dat

e

Ala

rm

Din

g

Tac

Tic

Batt_ok

Batt_askBatt_ask

Batt_ok

No_

Int

Powermanagement

Channel types1-rail

2-rails

4-rails

N-rails (N > 4)

Figure 2. The digital controller’s power management architecture and its interface

with the analog system. The power management architecture consists of four

modules: high- and low-voltage path handlers, battery monitor, and timer.


mdt2011050084.3d 8/9/011 15:17 Page 88

energy-driven behavior, allow a task (e.g., wake-up

sensor, measurement, data recovery, and sensor shut-

down) to be treated entirely with a direct path power

supply. No signals cancel a power supply order.

Int_OK and Ext_OK signals inform the digital applica-

tion manager of the voltage path’s capability to pro-

vide the correct power supply. The path handlers

can ask for the battery state using a Batt_ask signal

and get a yes/no answer in a Batt_ok signal.

The HV path handler outputs two signals to the an-

alog system: Charge allows the battery to charge if no

job is active (i.e., neither requested nor in process)

and if the voltage on the HV power path is high

enough. Batt_help turns the HV indirect power path

on and off. The LV path handler also outputs two sig-

nals to the analog system: DCDC_SR turns the step-

down converters (i.e., the LV indirect power path)

on and off. LDO_On turns the LDO regulator on and

off and thus completes the power path to the LV

loads. Additionally, since there is a start-up delay be-

fore the LDO outputs a smoothed and regulated sup-

ply voltage, the LV path handler can generate an

event and retrieve it after this delay using the tic

and tac signals.

Battery monitoring. When an event is received on

the Get_SoC signal, the battery-monitoring module

initiates an analog procedure that provides the bat-

tery state of charge using the SoC_Eval signal. The

state of the FSM changes according to the Batt_SoC

signal and sends the state of charge back to the appli-

cation manager on the SoC signal. This module

can be questioned by the voltage path handlers on

Batt_ask signals and sends back a yes/no state on

the concerned Batt_ok signal.

Timer. Because there is a start-up timing constraint

on the LDO regulator, the aim of the timer module

is to get an event on the tic signal when the LDO is

switched on and to send back an event on the tac sig-

nal after the LDO start-up delay. To implement this

delay, the module sends a value on Alarm to the

microsystem real-time clock (RTC) according to the

current time value on Date. As an event is emitted

on Ding when the current time value reaches the

Alarm value, the module is asynchronously informed

that the LDO start-up time has elapsed and sends an

event on tac. The module thus maintains asynchro-

nous behavior by avoiding a switching reaction on

each change of the RTC counter.

Analog-asynchronous handshake

interface design

The Managy microsystem is energy-driven; it

receives analog signals and is controlled by a data-

driven implementation.

From analog events to asynchronous hand-

shake. An analog comparator output switch is con-

sidered an event. Since the digital controller

architecture is data-driven, interfacing to perform

polling on analog signals is unnecessary, and thus

sampling of those signals is unnecessary. Only syn-

chronization is needed on these events. An analog-

to-asynchronous interface is needed to perform the

correct signaling. Figure 3a illustrates this interface.

Figure 3a shows the processing of an analog rising

edge into an asynchronous event. Assuming that the

ack signal is at 1 (channel ready) and that the free sig-

nal is at 0 (interface cleared), the second Muller gate

(C) generates a 1 on the data signal. The fast return to

zero (FRTZ) part of the interface prevents action of a

blocking scheme when the IN signal spends too much

time at 1. In that case, once the data signal is at 1, the

free signal goes to 0, which is propagated to the data

signal when ack goes to 0. This ensures that the inter-

face follows the handshake protocol. Once the IN sig-

nal goes back to 0, the free signal goes to 0, allowing

the interface to obtain a new analog event.

From asynchronous handshake to analog signal.

Consider an analog block whose supply voltage is

controlled through a PMOS transistor controlled by

an asynchronous dual-rail channel.5 Figure 3b repre-

sents the asynchronous dual-rail, four-phase interface.

Acknowledgment is generated with classical asynchro-

nous buffers. The interface uses a set-reset (RS) latch

(NR1 and NR2 gates), which detects E0 and E1 pulses

and sets the output to the corresponding bit value.

A pulse on E1 propagates through three gates before

the output is set, thus delaying the acknowledgment

to ensure stability of the RS latch outputs.

Because they require no arbitration, these interfa-

ces are simple and very efficient in implementing

the transformation between the microsystem’s analog

signals and the dedicated asynchronous controller.

Design, modeling, and verificationIn this section, we present an overview of the

design flow, using application scenarios, from micro-

system modeling to digital verification.


mdt2011050084.3d 8/9/011 15:17 Page 89

Asynchronous handshake modeling

Although dedicated languages have been pro-

posed for modeling asynchronous circuits, asynchro-

nous systems can easily be modeled with the

SystemVerilog language (IEEE Std. 1800-2009). In-

deed, asynchronous behavior can be modeled with

concurrent always modules communicating through

channels implemented with specific SystemVerilog

interfaces. With the help of specific libraries, design-

ers can instantiate channels carrying any data type,

from predefined SystemVerilog bit type to user-

defined type. A predefined type called event_type

can also be used in event-based communication.

Channel communications are modeled as Read

and Write operations using methods from the library;

the Read method enables a process to read data from

a channel. The process is paused until the handshake

is performed. The channel is released after this in-

struction; using the read value implies that it has

been saved. This method thus implies data memoriza-

tion, which can be avoided by using both the Begin-

Read and the EndRead methods and by inserting the

instructions which need the read value between

those two instructions. The first method blocks the

channel until the read value is processed, and

the second releases the channel, thus allowing the

designer to control channel availability and avoid

memorization. The Write method allows a process

to write data on a channel and blocks it until the

handshake is completed. Channel models implement

a Ready property, which is constantly updated and

represents the channel’s availability. This property

can be tested in processing code.

The following code illustrates a simple data buffer

on a byte channel, which reads input data and writes

it on the output channel. The code presents instantia-

tion of the two channels and the always block mod-

eling the buffering process.

Mixed-signal cosimulation flow

We verified the proposed mixed-signal asynchro-

nous microsystem using a mixed analog-digital flow

supporting the asynchronous models. First, we

Asynchronous Design

Bit channel

FRTZ

Event type channel+_

Vref

C

data

ack

Analog

Analog-to-asyncinterface

C

Reset_nReset_n

In

Asynchronousdigital

controller

free

Ack

Reset_n

VDD

Analogbloc

AnalogAsync-to-analog

interface

Out

E0

E1ackBit channel

NR1

NR2Asynchronousdigital

controller

(a)

(b)

Figure 3. Analog and asynchronous (a) and asynchronous and analog (b) interfaces.

channel_byte Cnl_out(), Cnl_in(); // I/O channels

byte A: // Variable for read

always

begin

cnl_in.Read(A); // Read

cnl_out.Write(A); // Write

end


mdt2011050084.3d 8/9/011 15:17 Page 90

performed high-level modeling

with SystemVerilog for digital

components and Simulink

(http://www.mathworks.com/

products/simulink/) for analog

components. This purely behav-

ioral model accounts for the

physical equations of harvesters

and allows a fast simulation

and a first functional verification.

We linked Matlab and ModelSim

(http://www.mathworks.com/

products/) to cosimulate the

whole platform. Using System-

Verilog, we then refined the

model at the channel transfer

level. With the help of specific

SystemVerilog libraries, we mod-

eled the asynchronous controller

handshake protocol and dual-rail

encoding. Then we verified the

system’s asynchronous behavior.

Finally, we refined the model

at the hardware level by synthe-

sizing the asynchronous control-

ler at the gate level using a

specific asynchronous cell li-

brary and designing the analog

blocks at the transistor level. We

verified the functional behavior

again using the Advanced

Analog/Mixed Signal Simulator

(ADMS) tool for mixed-signal

cosimulation between a Spice

model and a Verilog gate model.

We have not yet performed

the back-end verification phase.

It will consist of full placement and routing of the

microsystem, including analog macro blocks and

physical gate views. We will then verify the physical

layout extraction at the end of the design flow.

By loading the digital component in the Simulink

environment we performed a cosimulation between

Matlab and ModelSim. We launched the simulation

using Matlab and exchanged data with ModelSim to

perform the cosimulation.

As an example, Figure 4a illustrates a simple

analog-to-asynchronous interface verification. The en-

ergy source (i.e., an external power level, Pext) deliv-

ers charges to a DC/DC converter (DC/DC) and fills a

25-mF capacitor. The converter regulates its output

voltage at 2.5 V with 80% power efficiency. This

voltage is compared to a 2-V threshold by a compara-

tor whose output is sent as digital data to the

interface. A FRTZ analog-to-asynchronous interface

(Figure 3a) receives this signal and uses a simple

inverter to generate an automatic acknowledgment.

Figure 4 also shows relevant signal simulation

through Matlab (b) and ModelSim (c) during ca-

pacitance charging. Both graphs represent the

data signal. In Figure 4b, the 2-V voltage threshold

on Vout generates a rising edge on the data signal.

In Figure 4c, this rising edge is detected to generate

+_

Analog-to-async interface

Reset_n

CC

Reset_n out

data

Simulinkmodel

Classicalview

Pext

DigitalAnalog

C = 25 μF

τ = 400 ps

out_ack

Vref = 2 V

I_out

DC/DCη = 80%

10e-3 0.8I_out = 0 A

I_leak

I_leak = 100nA

[1e – 6; inf]

data

HDL cosimulationVref

I_out

x

×

Pext Converter’sefficiency ÷ 1

s+ -K-

1/C

––

Volta

ge

(V)

3

2

1

00 0.002 0.004 0.006 0.008

Time (s)(b)

(c)

(a)

0.01 0.012 0.014 0.016

VoutData

data

Asynchronousprotocol phases

8340000000 ps

I II III IV

8340001000 ps

out

out_ack

Time

ModelSim

simulatorn42:4449

Figure 4. Cosimulation: analog-to-asynchronous interface verification (a); signal

simulation with MathWorks’ Matlab (b) and ModelSim (c) during capacitance

charging.


mdt2011050084.3d 8/9/011 15:17 Page 91

an asynchronous event on the out signal, and

the interface performs the four-phase handshake

protocol.

The Managy design flow is based on a full mixed-

signal cosimulation and allows various architecture

refinement steps. Indeed, analog and digital parts

can be independently designed (from model to tran-

sistors) and verified together at any moment, from be-

havioral level to gate and transistor levels.

System-level verification methodology

We verified the Managy platform using four main

application scenarios:

� Initialization: Assuming the system is empty of any

energy, this scenario tests energy-harvesting start-

up to enable the controller supply. A component,

called Power-on-Reset, located in the controller

power supply (Figure 1), generates a reset signal

(e.g., 1, after 1 microsecond when the digital sup-

ply voltage reaches 0.8 V, the minimum supply

voltage value).

� Battery charging: Assuming there is no sensor

measurement request, this scenario verifies the

battery-charging path.

� Supplying and working with internal loads: This

scenario evaluates internal direct and indirect

power paths. When the load’s power supply is

valid, the system launches the sensor measure-

ments and reads the results.

� Supplying and working with external loads: This

scenario evaluates external direct and indirect

power paths. Various behaviors are emulated.

For example, a high-voltage buffer capacitor is

sized for the most consuming load; the system

waits for the capacitor to be full and treats a com-

plete job with the energy stored in it before turn-

ing off the path.

Most actual applications are a particular combina-

tion of these scenarios. For example, we considered a

microsystem for ambient-air monitoring, including a

temperature sensor, a humidity sensor, and a wireless

communication device. A typical scenario for this ap-

plication is to measure temperature and humidity

every minute and communicate the results every

10 minutes. Path reconfiguration either reduces total

power consumption or improves system autonomy.

The aforementioned four scenarios (basic behav-

iors) are basic functionalities that have been tested.

More generally, we tested the system on realistic appli-

cation environment, which regroups initialization and

use of internal/external loads while recharging the

battery. The tests are thus not a simple combination

of these four scenarios, but a ‘‘global’’ scenario that

will test each of them, one time (e.g., initialization)

or more (recharging, supplying power to the loads).

Simulation results

At fixed power efficiencies, it is possible to deter-

mine the efficiency gain function of the environ-

mental conditions (such as energy availability and

load service schedule) provided by the Managy ar-

chitecture, compared with a classical single-power-

path architecture.9 For the ambient-air monitor ap-

plication, Managy stores 40% more energy in the

battery by using the direct path to supply the

loads than a classical architecture does. If the avail-

ability of harvested energy decreases or if some

power loads require too much time, the indirect

path is activated, reducing overall power efficiency.

Nevertheless, in this case, a 25% gain is obtained

in a realistic environment (i.e., an environment in

which energy is available 60% of the time) in which

loads cannot always be supplied directly. The Man-

agy configuration leads to a shorter battery charge

time, as well as improved battery autonomy. Finally,

even though system specifications strongly drive the

maximum obtainable energy gain, environmental

conditions also have a major impact.

Asynchronous controller implementation results

We have implemented Managy in the UMC 180-nm

technology (http://www.umc.com) to ensure low

leakage current. We synthesized the complete asyn-

chronous controller using a specific asynchronous

standard-cell library (including Muller gates) created

from the digital UMC 180-nm standard library and

based on standard cells. The power management

controller’s total complexity is less than 5,000 gates.

The microsystem allows thermoelectrical, vibra-

tory, RF, and photovoltaic energy harvesting. Any in-

terface sensor can be connected to the microsystem

and sampled using a sigma-delta converter or a

successive approximation register (SAR) A/D con-

verter. We have verified the entire system at the tran-

sistor level for various application scenarios. This

verification, considering the energy state and sensor

event measurements, shows the full power path

reconfiguration. We fully validated the microsystem’s

Asynchronous Design


mdt2011050084.3d 8/9/011 15:17 2

robustness to low voltage and voltage variations,

which enables system wake-up at around 0.6 Vof sup-

ply voltage.

AS IN OUR SIMULATIONS, Managy will be fabricated in

a 180-nm technology, and the silicon will be tested in

an applicative environment. Power path reconfigura-

tion is based on available energy and requested

measurements. To propose a complex path reconfigu-

ration algorithm based on both available energy and

consumed power, we must consider each block’s

power consumption. Furthermore, Managy will be

tested under various environmental conditions with

a precise study of how the use of the fully energy-

driven power path configuration can reduce the con-

sumption at application level. Finally, implementing a

fully asynchronous data-processing chain may require

a precise A/D converter; asynchronous A/D conver-

sion would be a natural option. �

AcknowledgmentsThis work was partially funded by the French

National Research Agency (ANR) through the project

ANR-SESAM ANR-08-SEGI-019.

�References1. Y.H. Chee et al., ‘‘PicoCube: A 1cm3 Sensor Node

Powered by Harvested Energy,’’ Proc. ACM/IEEE 45th

Design Automation Conf. (DAC 08), IEEE Press, 2008,

pp. 114-119.

2. J. Penders et al., ‘‘Human++: From Technology to

Emerging Health Monitoring Concepts,’’ Proc. 5th Int’l

Summer School and Symp. Medical Devices and

Biosensors (ISSS-MDBS 08), IEEE Press, 2008,

pp. 94-98.

3. C. Williams et al., ‘‘Development of an Electromagnetic

Micro-Generator,’’ IEE Proc. Circuits, Devices & Systems,

vol. 148, no. 6, 2001, pp. 337-342.

4. V. Leonov et al., ‘‘Thermoelectric Converters of Human

Warmth for Self-Powered Wireless Sensor Nodes,’’

IEEE Sensors J., vol. 7, no. 5, 2007, pp. 650-657.

5. A.J. Martin, ‘‘Programming in VLSI: From Communicating

Processes to Delay-Insensitive Circuits,’’ Developments

in Concurrency and Communication, C.A.R. Hoare, ed.:

Addison-Wesley, 1990, pp. 1-64.

6. J.F. Randall and J. Jacot, ‘‘Is AM1.5 Applicable in Prac-

tice? Modelling Eight Photovoltaic Materials with Respect

to Light Intensity and Two Spectra,’’ Renewable Energy,

vol. 28, no. 12, 2003, pp. 1851-1864.

7. A. Abrial et al., ‘‘A New Contactless Smart Card IC

Using an On-chip Antenna and an Asynchronous Micro-

controller,’’ IEEE J. Solid-State Circuits, vol. 36, no. 7,

2001, pp. 1101-1107.

8. J.F. Christmann et al., ‘‘An Innovative and Efficient

Energy Harvesting Platform Architecture for Autonomous

Microsystems,’’ Proc. 8th IEEE Int’l NEWCAS Conf.,

IEEE Press, 2010, pp. 173-176.

9. J.F. Christmann et al., ‘‘Bringing Robustness and Power

Efficiency to Autonomous Energy Harvesting Micro-

systems,’’ Proc. IEEE Int’l Symp. Asynchronous Circuits

and Systems (Async 10), IEEE Press, pp. 62-71.

Jean-Frederic Christmann is pursuing a PhD in

microelectronics at the Grenoble Institute of Technol-

ogy, France. He is also a researcher at CEA-Leti

MINATEC Campus. His research interests include

asynchronous design and power management in

energy-harvesting systems. He has an MS in micro-

electronics from the Grenoble Institute of Technology.

Edith Beigne is an IC design engineer at the Digital

Design Laboratory of CEA-Leti MINATEC Campus,

where she directs low-power and variability activities.

Her research interests include asynchronous design,

variability issues and power-performance-yield im-

provement in advanced CMOS circuits. She has

an engineering degree in microelectronics from the

Grenoble Institute of Technology.

Cyril Condemine is the Microsystems IC Design

Team manager at CEA-Leti in Grenoble. His research

interests include the design of sensor interfaces and

of DC/DC converters. He has a PhD in microelec-

tronics from the National Institute of Applied Science.

Pascal Vivet is a researcher at the Digital Design

Laboratory of CEA-Leti MINATEC Campus. His re-

search interests include networks on chip, GALS

(globally asynchronous, locally synchronous) and

asynchronous design, low-power design, and MPSoC

architecture. He has a PhD in microelectronics from

the Grenoble Institute of Technology.

Jerome Willemin is an IC design engineer in the

Microsystems IC Design Team of CEA-Leti MINATEC

Campus. His research interests include sensors, en-

ergy harvesting, and power management. He has

an engineering degree in microelectronics from the

Grenoble Institute of Technology.


mdt2011050084.3d 8/9/011 15:17 Page 93

Nicolas Leblond is an application engineer at

Tiempo S.A.S., France. His research interests include

asynchronous design automation. He has an engineer-

ing degree in microelectronics from the Grenoble Insti-

tute of Technology.

Christian Piguet is head of the SoC program at

CSEM (Swiss Center for Electronics and Microtechnol-

ogy). He is also a professor at Ecole Polytechnique

Federale de Lausanne (EPFL), Switzerland, and

Lugano University, Switzerland. His research interests

include low-power SoC design. He has a PhD in com-

puter science from EPFL.

�Direct questions and comments about this article to

Jean-Frederic Christmann, MINATEC�CEA/LETI,

17 rue des Martyrs, 38054 Grenoble Cedex 9 � France;

[email protected].

Asynchronous Design


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