Brief History of the 80x86 familiesise.svcengg.com/images/userfiles/files/17CS44 - MPMC.pdf ·...

NAYANA.B.P

Module-1 The 80x86 Microprocessor Chapter-1

Microprocessor (µp): is a programmable electronic device that controls the interpretation and execution of the

instructions.

Micro refers to small size and the processor refers to the device that performs computational and control

operation.

The world 1stµp is the Intel 4004, introduced in 1971.Major µp manufacturers are Intel, Zilog (Z8000) and

Motorola (MC 6800).

[Note:CPU [ALU]: basic unit of computer invented in 1944 by Eckert and John William.Purpose of CPU:

improve or replace the calculator and simulate the human brain.Principle: Von Neumann stored program

concept.]

Brief History of the 80x86 families:

Evolution from 8080/8085 to 8086:

• In 1978 Intel Corporation introduced a 16 bit µp called the 8086. This processor was major

improvement over previous generation 8080/8085 series Intel microprocessor in several ways.

► 8086 having a memory capacity of 1MB whereas 8080/8085 having maximum of 64KB of

memory

► 8080/8085 was an 8-bitsystem meaning that the microprocessor could work on only 8-bits of

data at a time.Data larger than 8-bits had to be broken into 8-bit pieces to be processed by

CPU.The 8086 is a 16-bit microprocessor.

► The 8086 was a pipelined processor, whereas 8080/8085 non-pipelined. Pipelined architecture

increases the processing speed of the microprocessor.

Evolution from 8086 to 8088:

• When 8086 was introduced, at that all peripherals were designed are 8-bit.In addition, aprinted circuit

board with a 16 bit data bus much more expensive.

• Therefore Intel came-out with 8088 version.

• It is identical to the 8086 as programming is concerned, it has an 8 bit data bus instead of 16 bit bus, and

it has a same memory capacity of 1MB.

Success of the 8088

• In 1981 Intel has chance to change forever, when IBM picked up the 8088 as their microprocessor in

designing the IBM PC

• The 8088-based IBM PC was a great success,because IBM & Microsoft made it an open system.

• open system means Documentation and specifications of the hardwareand software of the PC were made

public

• Making it possible for many vendors to clone(copy of something) the hardwareand software

successfully.

Other microprocessor 80286, 80386 and 80486

• Major victory and need from PC users for more powerful microprocessor,Intel introduced the 80286 in

1982.

• The evolution of microprocessors is increasingly influenced by the evolution of the Internet.

• It consists of 16-bit internal & external data buses. 24 address lines, 16MB of memory. (224=16MB)

• 80286 can operate in one of two modes:real mode and protected mode - which allows for 16M of

memory.

NAYANA.B.P

[NOTE: ➢ Real mode operation allows the microprocessor to address only the first 1M byte of memory

space.Only the 8086 and 8088 operate in the real mode.

➢ The DOS requires that the microprocessor should operate in the real mode.

➢ Protected mode memory addressing allows access to the data and programs located above the

first 1M byte of memory, as well as within the first 1M byte of memory.

➢ The 80286 and above operate in either the real or protected mode.Protected mode is where

Windows operates. ]

♦ In 1985 Intel introduced 80386

♦ It consists of 32-bit bit internal & external data buses, with a 32-bit address bus.

♦ Capable of handling memory of up to 4 gigabytes. (232)

♦ All the microprocessor discussed so far were general-purpose processors could not handlemathematical

calculations rapidly

▪ Intel introducednumeric data processing chips called Math coprocessors, such as 8087, 80287, 80387.

▪ In 1989 Intel introduced 80486

▪ In 80486, Intel put a greatly enhanced80386 & math coprocessor on a single chip, plus additional

features such as cache memory.

o [Note: Cache memory is static RAM with a very fast access time.] ▪ All programs written for the 8088/86 will run on286, 386, and 486 computers.

Pentium and Pentium pro:

• In 1993, Intel released the Pentium. It was given the name Pentium instead of 80586 because names can

be copyrighted, but numbers cannot.

• Ithad speeds of 60 & 66 MHz, consists of 3 million transistors on thePentium chip.

• Pentium hasspeed twice that of 80486and 300 times faster than that of the original 8088.

• Pentium is fully compatible with previous x86processors but includes several new features like separate

8KB of cache memory for code and data.

• The Pentium is a 273-pin PGA (pin grid array) chip

• It consists of 64-bit data bus, & 32-bit address bus.

• Capable of addressing 4GB of memory.

• In 1995 Intel Pentium Pro was released—the sixthgeneration x86.

• It consists of 5.5 million transistors.

• Designed primarily for 32-bit servers & workstations.

Pentium II:

• In 1997 Intel introduced the Pentium II processor with 7.5-million-transistor,havingMMX(Multi-Media

Extension) technology for fast graphics and audio processing.

• In 1998 the Pentium II Xeon was released.

• Primary market is for servers and workstations.

• In 1999, Pentium Celeron was released.

• Its Lower cost & good performance make it ideal for PC’sused to meet educational and home business

needs.

Pentium III:

• In 1999 Intel released Pentium III.

• 9.5-million-transistor processor.

• 70 new instructions called SIMD.

• Mainly used for 3-D imaging, andstreaming audio.

NAYANA.B.P

Pentium 4:

• In 2000 Intel released Pentium 4.

• Speeds of 1.4 to 1.5 GHz.

• Completely new 32-bit architecture, called Net-Burst.

• Designed for heavy multimedia processing, Video, music, and graphic file manipulation on the Internet.

• New cache & pipelining technology & expansion ofthe multimedia instruction set make the Pentium-4

a high-endmedia processing microprocessor.

Pentium Itanium:

• Intel has selected Itanium as the new brand namefor the first product in its 64-bit family of processors.

• Formerly called Merced.

• Pentium Itaniumarchitecture is designed to meet needs ofpowerful servers & high-performance

workstations.

• Itanium will have the ability to execute many instructionssimultaneously, plus extremely large memory

capabilities.

Differences between 8008, 8085, 8086, 8088, 80286, 80386, 80486

S.N Product 8008 8080 8085 8086 8088 80286 80386 80486

1 Introduced year 1972 1974 1976 1978 1979 1982 1985 1989

2 Technology PMOS NMOS NMOS NMOS NMOS NMOS CMOS CMOS

3 NO’S of Transistors 3000 4500 6500 29000 29000 134000 275000 1.2million

4 Number of pins 18 40 40 40 40 68 132 168

5 Physical memory 16KB 64KB 64KB 1MB 1MB 16MB 4GB 4GB

6 Data bus 8 8 8 16 8 16 32 32

7 Address bus 8 16 16 20 20 24 32 32

Differences between Pentium, Pentium pro, Pentium-II, Pentium-III, Pentium-IV, Pentium Itanium

S.N Product Pentium Pentium pro Pentium-II Pentium-III Pentium-IV Pentium Itanium

1 Introduced year

1993 1995 1997 1999 2000 2002

2 Technology BICMOS BICMOS BICMOS BICMOS BICMOS BICMOS

3 Numbers

ofTransistors

3.1million 5.5million 7.5million 9.5million 42million 220 million

4 Physical memory

4GB 64GB 64GB 64GB 64GB 64GB

5 Data bus 64 64 64 64 64 64

6 Address bus 32 36 36 36 36 64

Note: • Bus is a group wires or lines which carry data, address and control signals.

• Address Bus: used to specify the physical address of the memory or I/O device, it is unidirectional.

[The 16-bit address bus means it can address or 65535 different memory locations].

• Data Bus: used to transfer the data within the microprocessor and memory or I/O device, it is

bidirectional-because microprocessor requires sending and receiving data.

• Control Bus: used to process the data that is what to do with selected memory location.

• In the most computer system there are four control bus connections. (Memory write control),

(memory read control), (I/O write control), (I/O read control).

NAYANA.B.P

Inside the 8086/88:

There are two ways to make the CPU process information faster:

• Increase the working frequency by using technology available, with cost considerations.

• Change the internal architecture of the CPU

The architecture of 8086 is functionally divided into two units they are Bus Interface Unit (BIU) and Execution

Unit (EU).

The BIU accesses memory and peripherals, while the EU executes instructions previously fetched.

The functional parts of the BIU are

1. Instruction queue (IQ)

2. Instruction pointer (IP)

3. Segment registers

▪ Instruction queue (IQ): is used to speed up the execution of programs, by pre-fetching six

instructionbytes in advance from the memory. The queue is 4 bytes long in 8088 and 6 bytes in 8086.

▪ Instruction pointer (IP): It always holds the address of memory location (offset) of the next instruction

to be executed. As the instruction is executed, the IP is advanced to point to the next instruction in the

memory.

▪ Segment Register: BIU contains four 16-bit segment register they are :

Code Segment register [points to the codememory]

Data Segment register [points to the data memory]

Stack Segment register [points to the Stack memory]

Extra Segment register [points to the data memory]

Execution Unit (EU):

♦ The phases of execution of the instruction are fetching, decode, and execute.

♦ The functional parts of the EU are

General purpose Registers

Arithmetic and Logic Unit (ALU)

Flag Registers

Pointers and Index Registers

NAYANA.B.P

♦ ALU:It performs 8bit or 16 bit mathematical operations such as Addition, Subtraction, Multiplication,

Division,data conversion and logical operations like AND,OR and NOT.It also performs register

increment,decrement and shift operation.

Multi/General purpose registers: • AX 16-bit register (accumulator) as either of two 8-bit registers (AH and AL).The AX register is used in

data movement,arithmetic and logical operations. AX is divided into two parts (AH-higher 8 bits of AX

and AL-lower 8 bits of AX).

• The bits of a register are numbered in descending order, as shown:

• BX (base register).It is used as a pointer to memory location. [Holds offset address of the memory

location using which we can access the data segment memory]

• CX (Count). The loop and repeat instruction of 8086 uses the CX register to hold repeat count value.The value stored in this register is used to control the number of times a loop has to be executed.

• DX (data), DH, or DL.DX is used to hold the I/O address during some I/O operation.

• BP(base pointer)points to a memory location for memory data transfers.

• DI(destination index) and SI (source index):.DI and SI is also used in string handling operations.

Special-Purpose Registers: SP(stack pointer) addresses an area of memory called the stack.

Pipelining:

Intel implemented pipelining in 8088/86 by splitting the internal structure into two sections:

• The execution unit (EU) and the bus interface unit (BIU).

• These two sections work simultaneously.

• The BIU fetches the instruction bytes while the EU is executing an instruction. Fetching the next

instruction while the current instruction executes, is called pipelining.

• 8088/86 pipelining has two stages, fetch &execute.

• In more powerful computers, it can have many stages.

• 8085 could fetch or execute at any given time.

• The idea of pipelining in its simplest form is to allow the CPU to fetch and execute at the same time.

NAYANA.B.P

INTRODUCTION TO ASSEMBLY PROGRAMMING

• The CPU can work only in binary, at very high speeds.

• It is tedious & slow for humans to deal with 0s & 1s inorder to program the computer.

• A program that consists of 0s & 1s is called machine language.

• Early programmers actually coded the programsin machine language.

• Assembly languages were developed,which provided mnemonics for machine code.

• Mnemonic refer to codes & abbreviationsthat are relatively easy to remember.

• Assembly language is referred to as a low-levellanguage because it deals directly with the

internalstructure of the CPU.

• Assembly language programs must be translated intomachine code by a program called an assembler.

• To program in Assembly language, programmersmust know the number of registers and their size as

well as other details of the CPU.

• There are numerous assemblers available fortranslating x86 Assembly language programsinto machine

code.

• One of the most commonly used assembler’s isMASM by Microsoft, TASM by Turbo.

• Today there are many different programminglanguages, such as C/C++, C#, etc.called high-level

languages

• Programmerdoes not have to be concerned with internal CPU details.

• High-level languages are translated into machinecode by a program called a compiler.

Assembly language programming:

• An Assembly language program consists of a series of lines of Assembly language instructions.

• An Assembly language instruction consists of a mnemonic (opcode), optionally followed by one or two

operands.

• Operands are the data items being manipulated and Mnemonics are commands to the CPU, telling it

what to do with those items.

• Two widely used instructions are move &add.

MOV instruction:

❖ The MOV instruction copies data from one location to another, using below format:

The MOV instruction showing the source, destination, and direction of data flow.

NAYANA.B.P

❖ This instruction tells the CPU to move (in reality, copy) the source operand to the destination operand.

❖ The source is at the right and the destination is at the left, next to the opcode MOV.

❖ An Opcode, or operation code, tells the microprocessor which operation to perform, the source and

destination are often called operands.

❖ Comma always separates the destination from the source in an instruction.

❖ MOV AX, BX instruction transfers the contents of the source register (BX) into the destination register

(AX).

❖ After this instruction is executed, register AX will have the same value as register BX.

❖ The source never changes, but the destination always changes.

Example:

MOV AH, AL ; move or copies the contents of AL to AH.

MOV AX, 45H ; move or copies immediate value 45H to AX

MOV BL, AX ; not allowed (mixed size: cannot move 16-bit register into an 8-bit register)

MOV DS, CS ; not allowed (segment to segment)

MOV DS, 35H ; not allowed (values cannot be loaded into any segment register)

➢ To move information to the segment registers, the data must first be moved to a general-purpose

register, then to the segment register.

Note: 8bit data ranges from 00H to FFH (255 Decimal) and 16-bit data ranges from 0000H to FFFFH

ADD instruction:

• The ADD instruction has the following format:

ADD destination, source

• ADD tells the CPU to add the source & destinationoperands and put the result in the destination.

• To add two numbers such as 25H and 34H, each canbe moved to a register, then added together:

• Executing the program above results in:AL = 59H (25H + 34H = 59H) and BL = 34H.

• The contents of BL do not change.

• Is it necessary to move both data items intoregisters before adding them together?No, it is not necessary.

• The general-purpose registers are typically used inarithmetic operations

INTRODUCTION TO PROGRAM SEGMENTS

• A typical Assembly language program consists ofat least three segments:

• Data segment - used to store information (data) to be processed by the instructions in the code segment.

• Code segment - which contains the Assembly language instructions that perform the tasks that

theprogram was designed to accomplish.

• Stack segment - used by the CPU to store information temporarily.

• A segment is an area of memory that includes upto 64K bytes

• 8085 having a maximum of 64KB of physical memory, since it had only 16 pins for address lines. (216 = 64K)

• In 8085 there was 64KB of memory for all code, data, and stack information.

• This Limitation was carried into 8088/86 design for compatibility.

• In 8088/86 there can be up to 64K bytes in each category.

• 8088/86 can only handle maximum of 64KB of code, 64KB of data and 64KB of stack at any given time

although it has 1MB of memory.

NAYANA.B.P

Code segment:

• In Intel 8086there are three types of addresses:

The physical address – is a 20-bit address.

An actual physical location in RAM or ROM within the 1MB

This address can have a range of 00000H to FFFFFH.

The offset address - a location in a 64KB segment range,

This can range from 0000H to FFFFH

The logical address - which consists of a segment value and an offset address.

• To execute a program, 8086 fetches the instructions from the code segment.

• The logical address of an instruction always consists of aCS (code segment) and an IP (instruction

pointer), shown in CS:IP format.

• IP contains the offset address.

• The physical address for the location of the instructionis generated by shifting the CS left one hex digit,

thenadding it to the IP.

• Assume CS=2500H& IP = 95F3H

• The offset address contained in IP, is 95F3H.

• The logical address is CS:IP, or 2500:95F3H.

• The physical address will be 25000 + 95F3 = 2E5F3H

• How to Calculate the physical address is shown below:

• The microprocessor will retrieve the instruction from memory locations starting at 2E5F3.

• Since IP can have a minimum value of 0000H and amaximum of FFFFH, the logical address range in

thisexample is 2500:0000 to 2500:FFFF.

• This means that the lowest memory location of the codesegment above will be 25000H (25000 + 0000)

and thehighest memory location will be 34FFFH (25000 + FFFF).

NAYANA.B.P

DATA SEGMENT:

• Assume a program to add 5 bytes of data, such as 25H, 12H, 15H, 1FH, and 2BH, one way to add them

is as follows:

• In the program above, the data & code are mixed together in the instructions.

• If the data changes, the code must be searched for every place it is included and the data retyped.

• To overcome this in x86 microprocessors, the area of memory setaside for data is called the data

segment.

• The data segment uses register DS and an offset value.

• 8088/86 allows only the use of registers BX, SI,and DI as offset registers for the data segment

• The next program demonstrates how data canbe stored in the data segment and the programrewritten so

that it can be used for any set of data.

• Assume data segment offset begins at 200H. The data is placed in memory locations:

• The program can be rewritten as follows:

• The offset address is enclosed in brackets, whichindicate that the operand represents the addressof the data and not the data itself.

• If the brackets were not included, as in "MOV AL,0200", the CPU would attempt to move 200 into AL

instead of the contents of offset address 200.

• This program will run with any set of data.

• Changing the data has no effect on the code.

• If the data had to be stored at a different offsetaddress the program would have to be rewritten

• A way to solve this problem is to use a register to holdthe offset address, and before each ADD,

increment theregister to access the next byte.

NAYANA.B.P

• The INC(increments) instruction adds 1 to its operand.

• "INC BX" achieves the same result as "ADD BX,1

• The physical address for data is calculated usingthe same rules as for the code segment.

• The physical address of data is calculated by shifting DSleft one hex digit and adding the offset value, as

shown

LITTLE ENDIAN V/S BIG ENDIAN:

• Previous examples used 8-bit or 1-byte data.What happens when 16-bit data is used?

• From a Gulliver’s travels story about how an egg shouldbe opened—from the little end, or the big end.

• In the big endian method, the high byte goes to thelow addressand the low byte to the high address.

• In the little endian method, the high byte goes to thehigh address and the low byte to the low address.

Memory location DS:1500 contains F3H.

Memory location DS:1501 contains 35H.

• All Intel microprocessors and many microcontrollersuse the little endian convention.

• Motorola microprocessors, alongwith some other microcontrollers, use big endian.

NAYANA.B.P

EXTRA SEGMENT:

• ES is a segment register used as an extra datasegment.

• In many normal programs this segment is not used.

• Used in essential string operations.

MEMORY MAP OF THE IBM PC:

• The 20-bit address of 8088/86 allows 1MB (1024K bytes) ofmemory space with the addressrange 00000–FFFFF.

• During the design phase of the firstIBM PC, engineers had to decideon the allocation of the 1-

megabytememory space to various sectionsof the PC.

• This memory allocation iscalled a memory map.

• Figure above shows Memory Allocation in the PC

• Of this 1 megabyte, 640K bytesfrom addresses 00000–9FFFFHwere set aside for RAM

• 128K bytes A0000H– BFFFFHwere allocated for video display

• The remaining 256K bytes fromC0000H–FFFFFH were set asidefor ROM

• The 640K bytes from 00000 to 9FFFFH is referredto as conventional memory.

• The 384K bytes from A0000H to FFFFFH are calledthe UMB (upper memory block).

RAM:

• In the early 80s, most PCs came with 64KB to 256KB of RAM,it is more at that time.

• Users had to buy memory expansion board to expand up to 640K if they needed additional memory.

• The need for expansion depends on the windows version being used and the type of application software

to run.

Video RAM:

• From A0000H to BFFFFH is set aside for video RAM

• The amount of memory used and the memory location vary dependingon the video board installed on

the PC

NAYANA.B.P

ROM:

• C0000H to FFFFFH is set aside for ROM.

• Not all the memory in this range is used by the PC's ROM.

• 64K bytes from location F0000H–FFFFFH areused by BIOS (basic input/output system) ROM.

• Some of the remaining space is used by various adaptercards (such as the network card), and the rest is

free.

• There must be some permanent (nonvolatile) memory to hold the programs telling the CPU what to do

when the power is turned on

• This collection of programs is referred to as BIOS.

• The BIOS tests devices connected to the PC whenthe computer is turned on and to report any errors.

FLAG REGISTER:

• The flag register is a 16-bit register sometimesreferred to as the status register.

• Although it is 16 bits wide, only some of the bits are used and rest are either undefined or reserved by

Intel.

• Many Assembly language instructions alter flagregister bits & some instructions function

differentlybased on the information in the flag register.

• Six flags, called conditional flags, indicate somecondition resulting after an instruction executes.

These six are CF, PF, AF, ZF, SF, and OF.

• The remaining three, often called control flags, controlthe operation of instructions before they are

executed.

CF (Carry Flag) - Set when there is a carry out, from d7 after an 8-bit operation, or d15 after a 16-bit

operation.

PF (Parity Flag) - After certain arithmetic and logical operations, if the result has an even number of 1s, the

parity flag is set to 1; otherwise, it is cleared.(The parity bit only counts the lower 8 bits of the result and is

set accordingly)

AF (Auxiliary Carry Flag) - If there is a carry from d3 to d4 of an operation, this bit is set; otherwise, it is

cleared.

ZF (Zero Flag) - Set to 1 if the result of arithmetic or logical operation is zero; otherwise, it is cleared.

SF (Sign Flag) - Binary representation of signed numbers uses the most significant bit as the sign bit. After

arithmetic or logic operations, the status of this sign bit is copied into the SF, indicating the sign of the result.

TF (Trap Flag) - When this flag is set it allows the program to single-step, meaning to execute one instruction

at a time. Single-stepping is used for debugging purposes.

IF (Interrupt Enable Flag) - This bit is set or cleared to enable/disable only external maskable interrupt

requests.

DF (Direction Flag) - Used to control the direction of string operations.

OF (Overflow Flag) - Set when the result of a signednumber operation is too large.

NAYANA.B.P

NAYANA.B.P

• Flag bits affected by the ADD instruction: CF (carry flag); PF (parity flag); AF (auxiliary carry flag). ZF

(zero flag); SF (sign flag); OF (overflow flag).

• Instructions such as data transfers (MOV) affect no flags.

• A widely used application of the flag register is the use of the zero flag to implement program loops.

• A loop is a set of instructions repeated a number of times.

• As an example, to add 5 bytes of data, a counter can be used to keep track of how many times theloop

needs to be repeated.

• Each time the addition is performed the counter is decremented and the zero flag is checked.

• When the counter becomes zero, the zero flag is set (ZF = 1) and the loop is stopped.

The x86 ADDRESSING MODES:

• How the CPU can access data in variousways, called addressing modes.

• The number of addressing modes is determined whenthe microprocessor is designed & cannot be

changed

• The x86 provides seven distinct addressing modes:

[1] Register addressing mode:

• Register addressing mode involves use of registersto hold the data to be manipulated.Memory is not

accessed, so it is relatively fast.

• Examples of register addressing mode:

• The source & destination registers must match in size.

• Coding "MOV CL,AX" will give an error, since the source isa 16-bit register and the destination is an 8-bit register.

[2] Immediate addressing mode

• The source operand is a constant.

• This mode can be used to load information into anyof register except the segment and flag registers.

NAYANA.B.P

[3] Direct addressing mode:

• The data is in somememory location(s).

• The address of the data in memory comes immediatelyafter the instruction.

• The address of the operand is provided with theinstruction, as an offset address.

• Calculate the physical address by shifting left the DSregister and adding it to the offset

• Note the bracketaround the address.If the bracket is absent, executing the command will givean error,

as it is interpreted to move the value 2400 (16-bit data) into register DL an 8-bit register.

[4] Register indirect addressing mode:

• The address ofthe memory location isheld by a register.

• The registers used for this purpose are SI, DI, and BX.

• The physical address is calculated by shifting DSleft one hex position and adding BX to it.

• The same rules apply when using register SI or DI.

[5] Based relative addressing mode:

• Base registersBX or BP, and a displacement value, is used tocalculate the physical address.

• Default segments used for the calculation of thephysical address (PA) are DS for BX and SS for BP.

• Alternatives are "MOV CX,[BX+10]" or "MOVCX,10[BX]"

• Again the low address contents will go into CLand the high address contents into CH.

• In the case of the BP register:

• Alternatives are "MOV AL,[BP+5]" or "MOV AL,5[BP]".

NAYANA.B.P

[6] Indexed relative addressing mode:

• Works thesame as the based relative addressing mode, except that registers DI & SI hold the offset

address.

[7] Based indexed addressing mode:

• By combining based & indexed addressing modes,a new addressing mode is derived called thebased

indexed addressing mode.

• One base register and one index register are used.

Segment Overrides

♦ The segment override prefix, allows the programmer to deviate from the default segment.

♦ The segment override prefix is appended at the front of an instruction to select an alternate segment

register.

♦ For example, the MOV AX,[DI] instruction accesses data within the data segment by default. If required

by a program, this can be changed by prefixing the instruction.

♦ Suppose that the data are in the extra segment instead of in the data segment. This instruction addresses

the extra segment if changed to MOV AX, ES: [DI]

NAYANA.B.P

THE STACK:

• What is a stack? Why is it needed?

• There must be some place for the CPU to store information safely and temporarily.

• The CPU needs this storage area since there are only a limited number of registers.

• The main disadvantage of the stack is access time.

• Some very powerful (expensive) computers do nothave a stack.

• The stack memory is pointed by SS (stack segment) register and SP (stack pointer) register.

• These registers must be loaded before anyinstructions accessing the stack are used.

• Every register inside the x86 can be stored in thestack, and brought back into the CPU from thestack

memory, except segment registers and SP.

• Storing a CPU register in the stack is called a push.

• Loading the contents of the stack into the CPU registeris called a pop.

• The x86 stack pointer register (SP) points at thecurrent memory location of thestack.

PUSH

• As each PUSH is executed, the register contents aresaved on the stack and SP is decremented by 2.

• When an instruction pushes or pops a generalpurposeregister, it must be the entire 16-bitregister.One must code "PUSH AX".

• There are no instructions such as "PUSH AL" or "PUSH AH".

POP

• As each pop is executed, the register contents are removed from the stack placed into the CPU and SP is incremented by 2

NAYANA.B.P

• The exact physical location of the stack depends onthe value of the stack segment (SS) register andSP, the stack pointer.

• To compute physical addresses for the stack, shiftleft SS one hex digitand then add offset SP to it.

Overlapping:

• It is possiblethat two segments can overlap which is desirable in some circumstance is shown below

NAYANA.B.P

Assignment question:

1. Name the thee features of the 8086 that were improvement over the 8080/8085

2. What are the major difference between 8086 and 8088 microprocessor?

3. Give the size of the address bus and physical memory capacity of the following

(a) 8086 (b) 80286 (c) 80386

4. The 80286 is a …………… bit microprocessor, whereas the 80386 is a .................... bit microprocessor

5. List the additional feature introduced in the 80286 that were not present in the 8086

6. List the additional feature introduced in the 80486 that were not present in the 80386

7. List the additional feature introduced in the Pentium that were not present in the 80486

8. How many transistors did the Pentium II use?

9. Which microprocessor was the first to incorporate MMX technology on-chip?

10. List the additional feature introduced in the Pentium II that were not present in the Pentium

11. Tue o false. Itanium has a 64-bit architecture.

12. Write the assembly language instruction to move value 1234h into register BX.

13. Write the assembly language instruction to add the values 16H and ABH. Place the result in the register

AX.

14. No value can be moved directly into which register?

15. What is the largest hex value that can be moved into a 16-bit register? Into an 8-bit register? What are

the decimal equivalents of these hex values?

16. A segment is an area of memory that includes up to ............. bytes.

17. State the difference between the physical and logical addresses.

18. A physical address is a ……. bit address and offset address is a ............ bit address.

19. Which register is used as the offset register with segment register CS?

20. If BX= 1234H and the instruction MOV [2400], BX were executed, what would be the content of

memory location at offsets 2400 and 2401?

21. Which register is used to access the stack?

22. with each push instruction, the stack pointer register SP is incremented/decremented by 2

23. with each pop instruction, the stack pointer register SP is incremented/decremented by 2

24. The ADD instruction can affect which bits of the flag register?

25. The carry flag will be set to 1 in an 8-bit addition if there is a carry out from bit ……..

26. The carry flag will be set to 1 in a 16-bit addition if there is a carry out from bit ……..

27. Explain the internal architecture of 8086, with neat diagram. 10M June/Dec 2010,june 12,14 & Dec 15

28. What is meant by pipelining? How is it implemented in 8086? 4M Dec 2010 June 2013

29. What is flag register? Explain the flag register format, in detail? 6M June 2011,14,15 and Dec 12,13

30. List and explain the addressing modes with examples. June 2010,11,14,Dec-11,13,15[6M]

31. What is the use of stack memory? Explain the execution of push and pop instruction? Dec-12[6M]

32. What do BIU and EU stands for and what are their functions?

33. Which of the following register cannot be split into high and low bytes?

CS, AX, DS, SS, BX, DX, CX, DI, DI

34. Name the segment register and their function in the 8088/86 6M Dec 2011,14,15 and June 12,13

35. If CS = 3499H and IP = 2500H find the logical, physical and lower and upper range of the address of the

code segment?

36. If DS = 3499H and offset = 3FB9H find the logical, physical and lower and upper range of the address

of the data segment?

NAYANA.B.P

37. If SS = 2000H and SP = 4578H find the logical, physical and lower and upper range of the address of

the stack segment?

38. Explain segment override with an example? Show the override register and the default segment register

used (if there were no override) in each of the following cases.

(a) MOV SS:[BX], AX

(b) MOV SS:[DI], BX

(c) MOV DX, DS:[BP+6]

39. Find the status of the CF,PF,AF,ZF and SF for the following operation

(a) MOV BL, 9FH (b) MOV AL, 23H (c) MOV DX, 10FFH

ADD BL, 61H ADD AL, 97H ADD DX, 1

40. Give the addressing mode for the each of the following:

(a) MOV AX, DS (g) MOV BX, 5678H

(b) MOV CX, [3000] (h) MOV AL, CH

(c) MOV [DI], BX (i) MOV AL, [BX]

(d) MOV CX, DS (j) MOV DX, [BP+DI+4]

(e) MOV BL, [SI]+10 (k) MOV AH, [BX+SI+50]

(f) MOV [BP+6], AL (L) MOV [BP][SI]+12, AX

NAYANA.B.P

Module-1 the 80x86 Microprocessor Chapter-2

Introduction to assembly language program: ▪ An Assembly language program consists of series of statements, or lines.

▪ Either Assembly language instructions or statements called directives.

▪ Directives (pseudo-instructions) give directions to the assembler about how the Assembly language

instructions should be translate into machine code.

▪ Assembly language instructions consist of four fields:

[label:] mnemonic [operands][;comment]

▪ Brackets indicate that the field is optional. Do not type in the brackets.

▪ The label field allows the program to refer to a line of code by name. The label field should not exceed

31 characters. A label must end with a colon

▪ The mnemonic (opcode) and operand(s) fields together accomplish the tasks for which the program was

written.

ADD AL, BL

MOV AX, 6764

▪ The mnemonic (opcode) in above example are ADD and MOV.

▪ "AL, BL" and "AX, 6764" are the operands.

▪ The comment field begins with a ";" and written at the end of a line. The assembler ignores comments.

Comments are optional, but if we write it is easier to read and understand the program.

Model defination:

▪ MODEL directive selects the size of the memory model.

▪ The memory model are SMALL, MEDIUM, COMPACT, and LARGE.

.MODEL SMALL

Small is one of the most widely used memory model for assembly language program. The small model uses a

maximum of 64kb of memory for code and another 64kb of for data

.MODEL MEDIUM

Data must fit in 64kb and code can exceed 64kb of memory

.MODEL COMPACT

Code must fit in 64kb and data can exceed 64kb of memory

.MODEL LARGE

Both Data and code can exceed 64kb of memory, but no single set should not exceed 64kb

.MODEL HUGE

Both Data and code can exceed 64kb of memory

.MODEL TINY

Both Data and code must fit 64kb of memory, used with COM files

Segment definition:

♦ An x86 CPU has four segments register.

♦ CS (code segment), DS (data segment), SS (stack segment), ES (extra segment).

♦ The simplified segment definition format uses three simple directives: ".CODE" ".DATA" ".STACK"

.STACK ; marks the beginning of the stack segment

.DATA ; marks the beginning of the data segment

.CODE ; marks the beginning of the code segment

NAYANA.B.P

A sample program:

A structure of assembly language program

STACK SEGMENT

.stack 64

This directive reserves 64 bytes of memory for the stack

DATA SEGMENT

The data segment defines three data items: DATA1, DATA2, and SUM.

Each is defined as DB (define byte).

Data items defined in the data segment will be accessed in the code segment by their labels.

DATA1 and DATA2 are given initial values in the data section.

SUM is not given an initial value. But storage is set aside for it.

NAYANA.B.P

CODE SEGMENT

The first line of the segment after the .CODE directive is the PROC directive.

A procedure is a group of instructions designed to accomplish a specific function.

Every procedure must have a name defined by the PROC directive, followed by the assembly language

instructions, and closed by the ENDP directive.

The PROC and ENDP statements must have the same label.

The PROC directive may have the option FAR or NEAR.

• MOV CX, 05 will load the value 05 into the CX register (looping).

• MOV BX, OFFSET OF DATA_IN will load BX with offset of DATA_IN

• ADD AL, [BX] adds the content of memory location pointed by BX to AL

• INC BX simply increments the pointer by adding 1 to BX, which makes BX to point to next data item.

• DEC CX decrements CX counter by 1 and set the ZF =1 when CX = 0

• JNZ AGAIN will jump back to the label again as long as the zero flag is indicating that CX is not zero

ASSEMBLE, LINK AND RUN ARE THE PROGRAM:

NAYANA.B.P

▪ Many editors can be used to create and/or edit the program.

▪ ".asm" file (the source file) is the file created with an editor.

▪ The ".asm" file is assembled by an assembler, like MASM or TASM.

▪ The assembler will produce an object file and a list file(.lst), along with other files(such as .crf) useful to

the programmer.

▪ The extension for the object file must be ".obj".

▪ Before feeding the ".obj" file into LINK, all syntax errors must be corrected.

▪ Fixing these errors will not guarantee the program will work as intended, as the program may contain

logical errors.

▪ This object file is input to the LINK program, to produce the executable program that ends in ".exe".

▪ The ".exe" file can be executed by the microprocessor.

Note:

“.lst” file which is optional is useful to the programmer because it lists the all the opcode, offset addresses as

well as errors detected by the MASM.

".crf” file (cross reference) it provides an alphabetical list of all symbols & labels used in the program as well

as program line numbers

“.map” file which gives the name of each segment, where it starts, where it stops, and its size in bytes.

The PAGE and TITLE directive

▪ Format of page directive is Page [lines],[columns]

▪ Default setting is 60,132

▪ It is common to put the name of the program immediately after the TITLE pseudo-instruction and a brief

description of the function of the program. Text after the TITLE should not exceed 60 ASCII characters.

CONTROL TRANSFER INSTRUCTIONS

▪ In the sequence of instructions, it is often necessary to transfer program control to a different location.

▪ If control is transferred to a memory location within the current code segment, it is NEAR. Also called

intrasegment (within segment).

▪ In a NEAR jump, the IP is updated and CS remains the same, since control is still inside the current code

segment.

NAYANA.B.P

▪ If control is transferred outside the current code segment, it is a FAR jump. Also called intersegment

(between segments)

▪ In a FAR jump, because control is passing outside the current code segment, both CS and IP have to be

updated to the new values.

CONDITIONAL JUMPS

▪ Conditional jumps have mnemonics such as JNZ (jump not zero) and JC (jump if carry).

▪ In the conditional jump, control is transferred to a new location if a certain condition is met.

▪ The flag register indicates the current condition.

▪ All conditional jumps are short jumps.

▪ The address of the target must be within -128 to +127 bytes of the IP.

▪ The conditional jump is a two-byte instruction.

One byte is the opcode of the jump condition.

The second byte is a value between 00 and FF.

▪ An offset range of 00 to FF gives 256 possible addresses. These are split between backward jump (to -

128) and forward jumps (to +127)

TABLE1: 8086 CONDITIONAL JUMP INSTRUCTION

UNCONDITIONAL JUMP

• An unconditional jump transfers control to the target location label unconditionally.

• unconditional jump have following forms:

SHORT JUMP - in the format "JMP SHORT label ".

• A jump within -128 to +127 bytes of memory relative to the address of the IP, opcode EB.

NEAR JUMP - has the format "JMP label".

• A jump within the current code segment.

• The target address can be any of the addressing modes of direct, register, register indirect, or memory indirect:

NAYANA.B.P

Direct JUMP - exactly like the short jump except that the target address can be anywhere in the segment in

the range +32767 to -32768 of the current IP.

Register indirect JUMP - target address is in a register. Example: "JMP BX", IP takes the value BX.

Memory indirect JMP - target address is the contents of two memory locations, pointed at by the register.

Example: "JMP [DI]" will replace the IP with the contents of memory locations pointed at by DI and DI+1.

FAR JUMP - in the format "JMP FAR PTR label". A jump out of the current code segment. IP and CS are

both replaced with new values.

CALL statements

❖ The CALL instruction is used to call a procedure, to perform tasks that need to be performed frequently.

❖ The target address could be in the current segment, in which case it will be a NEAR call or outside the

current CS segment, which is a FAR call.

❖ The microprocessor saves the address of the instruction following the call on the stack. To know where

to return, after executing the subroutine.

❖ In the NEAR call only the IP is saved on the stack.

❖ In a FAR call both CS and IP are saved.

❖ For control to be transferred back to the caller, the last subroutine instruction must be RET (return).

❖ RET instruction that directs the CPU to POP the top 2 bytes of the stack into the IP and resume

executing of instruction.

RULES FOR NAMES IN ASSEMBLY LANGUAGE

➢ The names used for labels in Assembly language programming consist of…

➢ Alphabetic letters in both upper- and lowercase.

➢ The digits 0 through 9.

➢ Question mark (?); Period (.); At ( @ )

➢ Underline ( _ ); Dollar sign ($)

➢ Each label name must be unique.

➢ Label name can be up to 31 characters long.

➢ The first character must be an alphabetic or special character. It cannot be a digit.

DATA TYPES AND DATA DEFINITION

x86 data types

▪ The 8088/86 processor supports many data types.

▪ Data types can be 8- or 16-bit, positive or negative.

▪ The programmer must break down data larger than 16 bits (0000 to FFFFH, or 0 to 65535 in decimal).

▪ A number less than 8 bits wide must be coded as an 8-bit register with the higher digits as zero.

▪ A number is less than 16 bits wide must use all 16 bits.

ORG (origin):

▪ ORG is used to indicate the beginning of the offset address.

▪ The number after ORG can be either in hex or in decimal.

▪ If the number is not followed by H, it is decimal and the assembler will convert it to hex.

DB ( Define byte):

➢ One of the most widely used data directives

➢ DB directive is used to allocate memory location that is 1 byte (8-bit) in size.

➢ DB can define numbers in decimal, binary, hex, & ASCII.

➢ D after the decimal number is optional.

➢ B (binary) and H (hexadecimal) number is required.

➢ To indicate ASCII, place the string in single quotation marks.

NAYANA.B.P

DUP ( duplicate ):

• DUP is used to duplicate a given number of characters. This can avoids a lot of typing. Two methods of

filling six memory locations with FFH

DW ( Define word):

➢ DW directive is used to allocate memory location that is 2 byte ( one word) in size.

DD ( Define double word):

➢ DD directive is used to allocate memory location that is 4 byte ( two word) in size.

DQ ( Define quad word):

➢ DQ directive is used to allocate memory location that is 8 byte ( four word) in size.

NAYANA.B.P

DT ( Define Ten bytes):

➢ DT directive is used to allocate memory location that is 10 bytes ( five word) in size.

➢ A maximum of 18 digits can be entered

EQU ( equate):

➢ EQU associates a constant value with a data label.

➢ When the label appears in the program, its constant value will be substituted for the label.

➢ Defines a constant without occupying a memory location.

➢ Example: COUNT EQU 25

➢ When executing the instructions "MOV CX,COUNT", the register CX will be loaded with the value 25.

FULL SEGMENT DEFINITION

The older, more traditional definition is called full segment definition.

SEGMENT DEFINITION

The SEGMENT and ENDS directives indicate the beginning &ending of a segment, in this format:

• In full segment definition, the ".MODEL" directive is not used. The directives ".STACK", ".DATA",

and ".CODE" are replaced by SEGMENT and ENDS directives.

• Figure below shows the full segment definition and simplified format, side by side.

NAYANA.B.P

STACK SEGMENT DEFINITION

The following three lines in full segment definition are comparable to ".STACK 64" in simple definition:

DATA SEGMENT DEFINITION

In full segment definition, the SEGMENT directive names the data segment and must appear before the data.

The ENDS segment marks the end of the data segment:

CODE SEGMENT DEFINITION

The code segment also begins and ends with SEGMENT and ENDS directives:

NAYANA.B.P

EXE vs. COM files:

FLOWCHARTS AND PSEUDOCODE

Flowcharts:

• A flowchart uses graphic symbols to represent different types of program operations.

• These symbols are connected together to show the flow of execution of the program.

Pseudocode:

• Flowcharting has been standard industry practice for decades.

• However some programs finds limitation in using flowchart such as we cannot write much in small

boxes and it is hard to get the big picture of what the program does.

• An alternative to flowcharts, pseudocode, involves writing brief descriptions of the flow of the code.

✓ Structured programming is a term used to denote programming techniques that makes the program

easier to code, debug and maintain.

✓ Structured programming uses three basic types of program control structures:

Sequence: is executing instructions one after the other.

NAYANA.B.P

Control: IF-THEN-ELSE and IF-THEN are control programming structures, which can indicate one

statement or a group of statements. Figure below shows the two control programming structure.

Iteration:

REPEAT-UNTIL and WHILE-DO are iteration control structures, which execute a statement or group of

statements repeatedly.

REPEAT-UNTIL structure always executes the statement(s) at least once, and checks the condition after the

each iteration.

WHILE-DO may not execute the statement(s), first condition is checked at the beginning of each iteration.

NAYANA.B.P

Example: Flow chart and pseudocode to a program that adds 5 bytes of data and store the result in sum


1) (a) The input file to the MASM assemble program has the extension ……..

(b) The input file to the LINK program has the extension ……..

2) Select all the file types from the second column that are output of the program in the first column.

…………… Editor (a) .obj (b) .asm

……………. Assembler (c) .exe (d) .lst

……………… linker (e) .crf (f) .map

3) What is the purpose of INC instruction?

4) What is the purpose of DEC instruction?

5) Describe briefly the function of the RET instruction.

6) If control is transferred outside the current code segment is it near or far

7) The DD directive is used to allocate memory location that are....... bytes in length

8) The DQ directive is used to allocate memory location that are....... bytes in length

9) State briefly the purpose of the ORG directive

10) What is the advantage in using the EQU directive to define a constant value

11) How many bytes set aside by each of the following directive

(a) Data DB ‘2345’ (b) Data DW 2345H

12) Which program produces the .exe file

13) Which program produces the .obj file

14) What is flow chart and pseodocode? Write the flowchart and pseudocode for if - then – else ?

15) Write any four difference between .com and .exe

16) Explain full segment with example?

17) Write a program to add 5 bytes of data and store the result in sum using simplified segment definition?

18) Explain call and return statement?

19) Briefly explain conditional and unconditional jump

20) With neat diagram explain assemble, link and run a program?

21) Explain the four fields of assembly language instruction?

22) Explain with example following assembler directives

a) .model tiny b) DB c) segment and ends d) proc and endp e) dup f) equ g) ORG

NAYANA.B.P Page1

Module-2 Arithmetic and Logical instruction, Interrupts

UNSIGNED ADDITION AND SUBTRACTION

Unsigned Numbers:

▪ Unsigned numbers are defined as data in which allthe bits are used to represent data.

▪ No bits are set aside for the positive or negative sign.

▪ Between 00 and FFH (0 to 255 decimal) for 8-bit data.

▪ Between 0000 and FFFFH (0 to 65535 decimal) for 16-bit data.

ADD instruction:

▪ The form of the ADD instruction is:

ADD Destination, Source ; destination = destination + source.

▪ The destination operand can be a register or in memory.

▪ The source operand can be a register, in memory, orimmediate.

▪ The instruction could change ZF, SF, AF, CF, or PF bits ofthe flag register.

Write a program to calculate the total sum of 5 bytes of data?

. MODEL SMALL

.DATA

X DB 125, 235, 197, 91, 48

SUM DW ?

.CODE

MOV AX,@ DATA

MOV DS,AX

MOV CX,05

MOV SI, OFFSET X

MOV AX, 00

BACK: MOV AL, [SI]

JNC OVER

INC AH

OVER: INC SI

DEC CX

JNZ BACK

MOV SUM, AX

MOV AH, 4CH

INT 21H

END

NAYANA.B.P Page2

• Numbers are converted to hex by the assembler:125=7DH, 235=0EBH, 197=0C5H, 91=5BH, 48=30H

• Three iterations of the loop are shown below.In the first, 7DH is added to AL.CF = 0 and AH = 00.CX =

04 and ZF = 0.

• Second, EBH is added to AL & since a carry occurred, AH is incremented, AL = 68H and CF = 1. CX =

03 and ZF = 0.

• Third, C5H is added to AL, again a carry increments AH.AL = 2DH, CX = 02 and ZF = 0.This process

continues until CX = 00 and the zeroflag becomes 1, causing JNZ to fall through.

• The result will be saved in the word-sized memory setaside in the data segment.

• The "ADC AH,00" instruction in reality means add00+AH+CF and place the result in AH.

SUBTRACTION OF UNSIGNED NUMBERS:

▪ In subtraction, x86 processors use 2's complement.

▪ Take the 2's complement of the source operand

▪ Add it to the destination operand

▪ Invert the carry.

▪ The form of the SUB instruction is:

SUB Destination, Source ; destination = destination - source

▪ After the execution, if CF = 0, the result is positive.If CF = 1, the result is negative and the

destinationhas the 2's complement of the result.

▪ NOT performs the 1's complement of the operand.The operand is incremented to get the 2's

complement.

NAYANA.B.P Page3

Multiplication of unsigned numbers:

▪ In multiplying two numbers in the x86 processor, use of registers AX, AL, AH, and DX is necessary.

▪ Three multiplication cases: byte times byte; word time’s word; byte time’s word.

Byte x Byte:

▪ One of the operands must be in the AL register and the second can be in a register or in memory.

▪ After the multiplication, the result is in AX.

Word x Word:

• One operand must be in AX & the second operand can be in a register or memory.

• After multiplication, AX & DX will contain the result.

• Since word-by-word multiplication can produce a 32-bit result, AX will hold the lower word and DX the higher word.

Word x Byte:

• Similar to word-by-word multiplication except that AL contains the byte operand and AH must be set to

zero.

Division of unsigned numbers:

▪ Division of two numbers in the x86 uses of registers AX, AL, AH, and DX.

▪ Four division cases: byte over byte; word over word; word over byte; double-word over word.

▪ In divide, in cases where the CPU cannot perform the division, an interrupt is activated.

▪ Referred to as an exception, and the PC will display a Divide Error message.

▪ If the denominator is zero. (Dividing any number by 00) or if the quotient is too large for the assigned

register.

NAYANA.B.P Page4

Byte/Byte:

▪ The numerator must be in the AL register and AH must be set to zero.

▪ The denominator cannot be immediate but can be in a register or memory

▪ After the DIV instruction is performed, the quotient is in AL and the remainder is in AH.

Word / Word:

• The numerator is in AX, and DX must be cleared.

• The denominator can be in a register or memory.

• After DIV, AX will have the quotient. The remainder will be in DX.

Word/Byte:

▪ The numerator is in AX & the denominator can be in a register or memory.

▪ After DIV, AL will contain the quotient, AH the remainder.

▪ The maximum quotient is FFH.

Doubleword/Word:

▪ The numerator is in AX and DX i.e. the most significant word in DX, least significant in AX.

▪ The denominator can be in a register or in memory.

▪ After DIV, the quotient will be in AX, the remainder in DX.

NAYANA.B.P Page5

LOGIC INSTRUCTIONS

AND:

▪ Syntax:

AND destination, source

▪ This instruction will perform a logical AND on the operands and place the result in the destination.

▪ Source operand can be a register, memory, or immediate.

▪ Destination operand can be a register or in memory.

▪ AND will automatically change the CF & OF to zero.

▪ PF, ZF, and SF are set according to the result.

OR:

▪ Syntax:

OR destination, source

▪ Destination and source operands are ORed, result placed in the destination.

▪ Source operand can be a register, memory, or immediate.

▪ Destination operand can be a register or in memory.

XOR:

▪ Syntax :

XOR dest, src

▪ Destination and source operands are XORed, result placed in the destination.

▪ Sets the result bits to 1 if they are not equal, otherwise, reset to 0.

NAYANA.B.P Page6

SHIFT:

▪ Shifts the contents of a register or memory location right or left.

▪ There are two kinds of shifts:

Logical - for unsigned operands.

Arithmetic - for signed operands.

▪ The number of times (or bits) the operand is shifted can be specified directly if it is once only.

▪ if it is more than once specified through the CL register.

SHR - logical shift right:

▪ Operand is shifted right bit by bit.

▪ For every shift the LSB (least significant bit) will go to the carry flag. (CF)

▪ The MSB (most significant bit) is filled with 0.

SHL - Logical shift left

▪ After every shift, the LSB is filled with 0.

▪ MSB goes to CF.

NAYANA.B.P Page7

CMP (Compare):

▪ Syntax:

CMP destination, source

▪ Compares two operands & changes flags according to the result of the comparison, leaving the operand

unchanged.

▪ Source operand can be in a register, in memory, or immediate.

▪ Destination operand can be in a register or in memory.

▪ CF, AF, SF, PF, ZF, and OF flags reflect the result.

▪ Only CF and ZF are used.

▪ Compare is really a subtraction. Except that the values of the operands do not change.

Write a program by assuming there is a class of five people with following grades: 69, 87, 96, 45, and 75.

Find the highest grade?

.MODEL SMALL

.DATA

GRADE DB 69, 87, 96, 45, 75

HIGHEST DB ?

.CODE

MOV AX,@DATA

MOV DS, AX

MOV CX, 05 ; SET UP LOOP COUNTER

MOV BX, OFFSET GRADE ; SET UP POINTER

SUB AL, AL ;CLEAR AL

AGAIN: CMP AL, [BX]

JA NEXT ; JUMP IF AL STILL HIGHEST

MOV AL, [BX] ; HOLD NEW HIGHEST VALUE

NEXT: INC BX ;POINT TO NEXT GRADE

LOOP AGAIN ; CONTINUE SEARCH

MOV HIGHEST, AL ; SAVE HIGHEST GRADE

MOV AH, 4CH

INT 21H

END

ROTATE INSTRUCTIONS

▪ ROR, ROL and RCR, RCL are designed specifically to perform a bitwise rotation of an operand.

▪ They allow a program to rotate an operand right or left.

▪ If the operand is to be rotated once, the 1 is coded. If it is to be rotated more than once, register CL is

used to hold the number of times it is to be rotated.

▪ The operand can be in a register or memory.

▪ There are two types of rotations.

Simple rotation of the bits of the operand

Rotation through the carry.

NAYANA.B.P Page8

ROR (Rotate Right):

▪ In ROR the LSB is moved to the MSB, & is also copied to CF.

ROL (Rotate Left):

▪ In ROL the MSB is moved to the LSB and is also copied to CF

RCR (Rotate right through carry):

• In RCR, the LSB is moved to CF and CF is moved to the MSB.

• If the operand is to be rotated once, the 1 is coded. If it is to be rotated more than once, register CL is

used to hold the number of times it is to be rotated.

NAYANA.B.P Page9

RCL Rotate left through carry:

• In RCL, the MSB is moved to CF and CF is moved to the LSB.

INT 21H and INT 10H Programming

❖ There are useful function within BIOS and the OS that are available to the user through INT (interrupt)

instruction

❖ When INT is invoked it saves the CS:IP and flag on the stack

❖ The INT instruction has the following format:

INT XX ; the interrupt number XX can be 00-FFH

❖ 00 –FFH gives total of 256 interrupt in x86 microprocessor.

❖ Out of 256, two of them are most widely used are INT 10H and INT 21H

❖ Various function of INT 10H and INT 21H are selected by putting specific value into AH register.

❖ INT XX : is a two byte instruction, 1st byte for the opcode and 2nd byte is for the interrupt number

BIOS [INT 10H]

INT 10H subroutines are burned into the ROM BIOS of the x86 based IBM PC and are used to communicate

with the computer screen video.

Use INT 10H function calls to:

Changing the color of character or background color

Clearing the screen.

Changing the location of the cursor.

Change the video mode.

Monitor screen in text mode

❖ The monitor screen in the x86 PC is divided into 80 columns and 25 rows in normal text mode.

❖ Columns are numbered from 0 to 79.Rows are numbered 0 to 24.

❖ The top left corner has been assigned 00, 00 and the top right 00, 79.

❖ Bottom left is 24, 00 and bottom right 24, 79.

❖ Since both row and column number is associated with each location on the screen, one can move the

cursor to any location on the screen by simply changing the row and column values.

NAYANA.B.P Page10

Clearing the screen: INT 10H function 06H

❖ It is often desirable to clear the screen before displaying data.

❖ To use INT 10H to clear the screen the following registers must contain certain values before INT 10H

is called: AH = 06, AL = 00, BH = 07, CX = 0000, DH = 24, DL = 79.

❖ Option AH = 06 of INT 10H is in reality the “Scroll window up”.

❖ CH &CL registers hold starting row & column.

❖ DH &DL registers hold ending row & column.

Setting the cursor to a specific location: INT 10H function 02H

• INT 10H function AH = 02 will change the position of the cursor to any location.

• Desired position is identified by row/column values in DX.

• Where DH = row and DL = column.

• Video RAM can have multiple pages of text. When AH = 02, page zero is chosen by making BH = 00.

Get current cursor position: INT 10H function 03

• In text mode, determine where the cursor is located at any time by executing the following:

• After execution of the program, registers DH & DL will have current row and column positions.

• CX provides information about the shape of the cursor.

• In text mode, page 00 is chosen for the currently viewed page.

NAYANA.B.P Page11

Changing the video mode

• To change the video mode, use INT 10H with AH = 00 and AL = video mode.

• In text mode, the screen is viewed as a matrix of rows and columns of characters.

• In graphics mode, a matrix of horizontal & vertical pixels.

• Number of pixels depends on monitor resolution & video board.

• There are three different video modes

• Text mode of 80 ×25 characters: in this mode, 16 colors are supported, to select this mode, use AL = 03

for mode selection in INT 10H option AH = 00.

• Graphics mode of 320 ×200 (medium resolution): to select this mode, use AL = 04.

• Graphics resolution of 640 ×200 (high resolution): to select this mode, use AL = 06.

Attribute byte in monochrome monitors:

➢ An attribute associated with each character on the screen.

➢ An attribute provides information to the video circuitry such as color/intensity of the character

(foreground) & background.

➢ The attribute byte for each character on the monochrome monitor is limited.

Attribute byte in CGA (computer graphics adapter) text mode:

➢ CGA attribute byte bit definition is as shown:

➢ The background can take eight different colors by combining the prime colors red, blue, and green.

➢ The foreground can be any of 16 different colors by combining red, blue, green, and intensity

NAYANA.B.P Page12

DOS INTERRUPT 21H

❖ When the OS is loaded, INT 21H can be invoked to perform some extremely useful functions.

❖ Such as inputting information from the keyboard, and displaying it on the screen.

INT 21H Option 09: outputting a data string the monitor

❖ INT 21H can send a set of ASCII data to the monitor.

❖ to do this the following register must be set: AH = 09 and DX = offset address of the ASCII data to be

displayed. then INT 21H invoked.

NAYANA.B.P Page13

❖ INT 21H option 09 will display the ASCII data string pointed at by DX until it encounters the dollar

sign "$".

❖ In the absence of dollar sign "$" display the garbage value found in the memory until it finds "$" sign.

INT 21H Option 02: outputting a single character

❖ When it is necessary to output only a single character to the monitor, put 02 in AH, and DLis loaded

with the character to be displayed.

❖ The following displays the letter "J" :

INT 21H Option 01: inputting a single character, with echo

❖ This function waits until a character is input from the keyboard, and then echoes it to the monitor.

❖ After the interrupt, the input character will be in AL.

INT 21H Option 0AH: inputting a data string from the keyboard

▪ One can get data from keyboard & store it in a predefined data segment memory area.

▪ To do this register are set as follows: AH = 0AH, DX = offset address at which the string of data is

stored.

▪ Commonly referred to as a buffer area.

▪ DOS requires area of buffer to be defined in the data segment.

▪ The first byte specifies the size of the buffer.

▪ The number of characters from the keyboard is in the second byte.

▪ Keyed-in data placed in the buffer starts at the third byte.

▪ This program accepts up to six characters from the keyboard, including the return (carriage return) key.

▪ Six buffer locations were reserved, and filled with FFH.

NAYANA.B.P Page14

▪ Memory contents of offset 0010H:

▪ Assuming the data entered through the keyboard was "USA" <RETURN>, the contents of memory

locations starting at offset 0010H would look like:

▪ 0010H = 06 DOS requires the size of the buffer here.

▪ 0011H = 03 The keyboard was activated three times

▪ 0012H = 55H ASCII hex value for letter U.

▪ 0013H = 53H ASCII hex value for letter S.

▪ 0014H = 41H ASCII hex value for letter A.

▪ 0015H = 0DH ASCII hex value for CR. (carriage return)

Use of carriage return and line feed

❖ CR (carriage return) its ASCII value is 0DH (13), and LF (line feed) its ASCII value is 0AH (10).

❖ 13 represents carriage return i.e. takes the cursor to the left corner of same line

❖ 10 represents newline like /n in C

INT 21H Option 0AH: keyboard input without echo

➢ Option 07 requires the user to enter a single character, which is not displayed (or echoed) on the screen.

➢ The PC waits until a single character is entered and provides the character in AL.

Write a program to clear the screen, set the cursor at the center of the screen and display the message?

.MODEL SMALL

.DATA

.STACK

MSG DB 13, 10, “WELCOME TO INDIA”

.CODE

MOV AX, @ DATA

MOV DS, AX

CALL CLEAR

CALL CURSOR

CALL DISPLAY

MOV AH, 4CH

INT 21H

CLEAR PROC NEAR

MOV AX, 0600H

MOV BH, 07

MOV CX, 0000

MOV DX, 184F

INT 10H

RET

CLEAR ENDP

NAYANA.B.P Page15

CURSOR PROC NEAR

MOV AH, 02H

MOV BH, 00

MOV DH, 12

MOV DL, 39

INT 10H

RET

CURSOR ENDP

DISPLAY PROC NEAR

MOV AH, 09

MOV DX, OFFSET MSG

INT 21H

RET

DISPLAY ENDP

END

8088/86 interrupts:

✓ An interrupt is an external event which informs the CPU that a device needs its service.

✓ In the 8086/88 there are total of 256 interrupts: INT 00, INT 01,… ............ INT FF.

✓ When an interrupt occurs the microprocessor completes the execution of the current instruction an jumps

to the function called ISR and executes the instruction in ISR (interrupt service routine or interrupt

handler).

✓ When an interrupt occurs the microprocessor automatically saves the CS:IP and flag register(FR) on the

stack.

✓ For every interrupt four bytes of memory allocated in interrupt vector table, two bytes for IP and two

bytes for CS of the ISR.

✓ the lowest 1024 bytes(256*4=1024) of memory space are set aside for the interrupt vector table and not

used for any other function

✓ The memory location to which an interrupt goes is always four times the value of the interrupt number.

NAYANA.B.P Page16

❖ A software interrupt is caused either by an exceptional condition in the processor itself, or a special

instruction in the instruction set which causes an interrupt when it is executed.

❖ Hardware interrupts are used by devices to communicate that they require attention from the CPU.

Difference between INT and CALL instruction:

✓ A call instruction can jump to any location within the 1MB of memory, whereas INT XX goes to fixed

memory (lowest 1024 bytes).

✓ A call instruction cannot be masked (disabled), but INT XX belonging to external hardware can be

masked.

✓ Call instruction automatically saves only CS:IP of the next instruction on the stack, while INT XX saves

the CS:IP and flag register(FR) of the next instruction on the stack.

✓ At the end of the call procedure has RET instruction, whereas last instruction fir INT xx is

IRET(interrupt return)

Function associated with INT 00 to INT 04

INT 00 (divide error):

▪ It is invoked by the microprocessor whenever there are conditions (exceptions) that the CPU is unable to

handle.

▪ One such situation is an attempt to divide a number by zero.

INT 01 (single step):

❖ In executing a sequence of instruction, there is a need to examine the content of the CPU registers and

system memory

❖ this is done by executing the program one instruction at a time and then inspecting registers and memory

❖ this is commonly referred to as single stepping or trace

❖ Intel has assigned INT 01 specially for implementing single stepping

❖ To make single step the trap flag (TF) D8 of the flag register must be set to 1

INT 02 (non maskable interrupt)

❖ Intel has set aside INT 02 for the NMI interrupt

❖ The non-maskable interrupt occurs when logic 1 is placed on the NMI input pin to the microprocessor.

INT 03 (breakpoint)

➢ To implement a breakpoint function in the program Intel has set aside INT 03.

➢ In single step mode one can inspect the CPU registers and memory after the execution of each

instruction, a breakpoint is used to examine the CPU registers and memory after the execution of a

group of instructions

INT 04 ( signed number overflow)

➢ this interrupt is invoked by a signed number overflow condition

➢ Overflow is a special interrupt used with the INTO instruction.

NAYANA.B.P Page17

➢ Occurs when overflow flag is set by the microprocessor during signed operation and when INTO

(interrupt on overflow) instruction is executed.

➢ Suppose DATA1 = +64 and DATA2=+64

➢ The above incorrect result causes OF to be set to 1.

➢ INTO causes the CPU to perform INT 04 and jump to physical location 0010H of the vector table to get

the CS:IP of the interrupt service routine

INT 12H: checking the size of RAM on the IBM PC

➢ IBM PC BIOS uses INT 12H to provide the amount of installed conventional (0 to 640KB) RAM

memory on the system.

NAYANA.B.P Page18


1. Explain the following instruction with example: ADD SUB MUL DIV SHR SHL ROR

ROL RCR RCL OR AND XOR CMP

2. What is interrupt and ISR? explain the following interrupt with example

INT 01 INT 02 INT 03 INT 04 INT 12

3. What is the function of BIOS and DOS interrupt?

4. Explain the following BIOS interrupt briefly?

INT 10H option 06H INT 10H option 02H INT 10H option 03H

5. Explain the following DOS interrupt briefly?

INT 21H option 09H INT 21H option 02H INT 21H option 01H

INT 21H option 0AH INT 21H option 07H

6. Write a program to calculate the sum of 5-bytes of data?

7. Explain the attribute byte in monochrome monitors and CGA?

8. Explain how to change video mode? Explain different types of video mode.

9. write a program to clear the screen, make the cursor at the center of screen and display the message

“VTU”

10. Explain byte *byte, word*word and word * byte multiplication with example?

11. Explain byte / byte, word/word and word / byte division with example?

12. Find the physical address and logical address in the interrupt vector table associated with INT 05H and

INT 20.

NAYANA.B.P Page1

Module-3 SIGNED NUMBERS, STRINGS and TABLES Chapter-1

SIGNED NUMBER ARITHMETIC OPERATIONS

▪ Many applications require signed data, & computers must be able to accommodate such numbers.

▪ The most significant bit (MSB) is set aside for the sign(+ or -) & the rest of the bits are used for the

magnitude.

▪ The sign is represented by 0 for positive (+) numbersand 1 for negative (-) numbers.

Signed Byte Operands:

▪ In signed byte operands, D7 (MSB) is the signand D0 to D6 are set aside for the magnitude ofthe

number.

▪ If D7 = 0, the operand is positive.If D7 = 1, it is negative.

Byte-sized signed number ranges

Positive Numbers:

• The range of byte sized positive numbers is 0 to +127.

• If a positive number is larger than +127, a word-sizedoperand must be used.

Negative Numbers:

▪ The range of byte sized negative numbers is -1 to -128.

▪ For negative numbers D7 is 1, but the magnitude isrepresented in 2's complement.

▪ To convert to negative number representation(2's complement), follow these steps:

1. Write the magnitude of the number in 8-bitbinary (no sign).

2. Invert each bit.

3. Add 1 to it.

NAYANA.B.P Page2

Word-Sized Signed Numbers:

▪ In Word-Sized operands, D15 (MSB) is the sign and D0 to D14 are set aside for the magnitude of the

number.

▪ A range of -32768 to +32767.

Word-sized signed number ranges

Overflow Problem in Signed Number Operations:

• When using signed numbers, a serious issue, theoverflow problem, must be dealt with.

• The CPU indicates the existence of the problem by raisingthe OF (overflow) flag.

• If the result of an operation on signed numbers istoo large for the register, an overflow occurs.

NAYANA.B.P Page3

• +96 is added to +70 and the result according to the CPU is -90.Why? The result was more than AL

could handle, because likeall other 8-bit registers, AL could only contain up to +127.

• The CPU designers created the overflow flagto inform the programmer that the result ofthe signed

number operation is erroneous.

• In 8-bit signed number operations, OF is set to 1 if:

There is a carry from D6 to D7 but no carry out of D7.

• In above Example, since there is only a carry fromD6 to D7 and no carry from D7 out, OF = 1.

❖ In a 16-bit operation, OF is set to 1 when there is a carry from D14 to D15, but no carry out of D15.

NAYANA.B.P Page4

Avoiding erroneous result in signed number:

CBW (convert signed byte to signed word):

• CBW will copy D7 (the sign flag) to all bits of AH.

• The operand is assumed to be AL, and the previous contents of AH are destroyed.

CWD (convert signed word to signed double word):

• CWD will copy D15 of AX to allbits of the DX register.

• The operand is assumed to be AX, and the previous contents of DX are destroyed.

Write a program to handle the overflow problem:

.MODEL SMALL

.DATA

XDB +96

Y DB +70

RESULT DB ?

.CODE

MOV AX,@DATA

MOV DS,AX

MOV AH,00 ; AH=00

MOV AL,X ; GET VALUE OF X

MOV BL,Y ; GET VALUE OF Y

ADD AL,BL ; ADD X AND Y

JNO OVER ; IF 0F=0 THEN GO TO OVER OTHERWISE

MOV AL,Y ; GET VALUE OF Y

CBW ; CONVERT BYTE TO WORD

MOV BX,AX ; SAVE IT IN BX

MOV AL,X ; GET VALUE OF X

CBW ; CONVERT BYTE TO WORD

ADD AX,BX ; ADD AX AND BX

OVER: MOV RESULT,AX

MOV AH,4CH

INT 21H

END

NAYANA.B.P Page5

SIGNED DIVISION AND MULTIPLICATION:

IDIV signed number division:

• IDIV means "integer division“, used for signednumber division.

• Syntax: IDIV source

IMUL signed number multiplication

• Similar in operation to the unsigned multiplication.

• Operands in signed number operations can be positiveor negative, and the result must indicate the sign.

Write a program to find the average temperature

.MODEL SMALL

.DATA

TEMP DB +13, -10, +19, -9,+37

AVG DW ?

REMINDER DW ?

.CODE

MOV AX,@DATA

MOV DS, AX

MOV CX, 05 ; LOAD COUNTER

MOV BX,00 ;CLEAR BX

MOV SI, OFFSET TEMP ;SETUP POINTER

BACK:MOV AL, [SI] ;MOVE BYTE INTO AL AND CONVERT TO WORD

CBW

ADD AX, BX ; ADD IT TO BX

INC SI ; INCREMENT POINTER

LOOP BACK ;LOOP IT IF NOT FINISHED

MOV AL, 05 ;MOVE COUNT TO AL CONVERT TO WORD

CBW

MOV CX,AX ; SAVE DENOMINATOR IN CX

MOV AX, BX ; MOVE SUM TO AX & CONVET TO DOUBLE WORD

CWD

IDIV CX ;FIND THE AVERAGE

MOV AVG,AX ; STORE THE AVERAGE (QUOTIENT)

MOV REMINDER, DX ; STORE THE REMINDER

MOV AH, 4CH

INT 21H

END

NAYANA.B.P Page6

Write a program to find the lowest temperature

.MODEL SMALL

.DATA

TEMP DB +13, -10, +19, -9,+37

LOWEST DB ?

.CODE

MOV AX,@DATA

MOV DS, AX

MOV CX, 04 ; LOAD THE COUNTER (NUMBER ITEMS-1)

MOV SI, OFFSET TEMP ; SET UP POINTER

MOV AL, [SI] ; AL HOLDS LOWEST VALUE FOUND SO FAR

BACK: INC SI ; INCREMENT POINTER

CMP AL, [SI] ; COMPRARE NEXT BYTE TO LOWEST

JLE SEARCH ; IF AL IS LOWEST, CONTINUE SEARCH

MOV AL, [SI] ; OTHERWISE SAVE NEW LOWEST

SEARCH: LOOP BACK

MOV LOWEST, AL ; SAVE LOWEST TEMPERATURE

MOV AH, 4CH

INT 21H

END

Arithmetic shift:

❖ There are two types of shifts: logical and arithmetic.

❖ Logical shift used for un-signed numbers and arithmetic shift used for signed numbers

❖ Arithmetic shift is same as logical shift, except that the sign bit is copied to the shifted bits

SAR(shift arithmetic right):

• Syntax:

SAR destination, count

• As the bits of the destination are shifted to the rightinto CF, the empty bits are filled with the sign bit.

SAL (shift arithmetic left):

❖ SAL and SHL (shift left) doexactly the same thing.

❖ Basically the same instruction with two mnemonics.

String instructions:

➢ There is a group of instruction referred to as string instruction in 80x 86 families of microprocessors.

➢ They are capableof performing operations on a series of operands located inconsecutive memory

locations.

➢ Example: CMP can compare only 2 bytes (or words) ofdata, CMPS (compare string) compares two

arraysof data located in memory locations pointed at by the SI and DI registers.

➢ For string operations to work, CPU designers setaside SI and DI registers

➢ In 8088/86 processors, SI & DI registers always pointto the source and destination operands,

respectively.

➢ To generate the physical address, 8088/86 alwaysuses SI as the offset of the DS (data segment) register

and DI as the offset of ES (extra segment).

NAYANA.B.P Page7

➢ The ES register must be initialized for the stringoperation to work.

➢ The operand can be a byte or a word, distinguishedby letters B (byte) & W (word) in the mnemonic.

Direction Flag:

➢ To process operands located in memory requires the pointer to be incremented/decremented.

➢ This is achieved by the direction flag.

➢ In Flag register bit 11 (D10) is set aside for the direction flag (DF).

➢ The direction flag is used only with the string instructions.

CLD (clear direction flag) and STD (set the direction flag):

♦ The CLD instruction clears the DF flag (DF = 0) and the STD instruction sets DF flag (DF = 1).

♦ Therefore, the CLD instruction selects the auto-increment (DF = 0) mode and STD selects the auto-

decrement mode (DF = 1)for the DI and SI registers during string operations..

REP (repeat) prefix

➢ The REP (repeat) prefix allows a string instruction toperform the operation repeatedly.

➢ REP assumes that CX holds the number of times theinstruction should be repeated. (until CX becomes

zero)

LODS: [load string]

➢ The LODS instruction loads AL or AX with data stored at the data segment offset address indexed by

the SI register.

➢ After loading AL with a byte, the contents of SI increment by 1 (if DF = 0) or decrement by 1 (if DF =

1), or after loadingAX with a word, the contents of SI increment by 2 (if DF = 0) or decrement by 2 (if

DF = 1)

➢ LODS is never used with a REP prefix.

➢ Ex:

STOS: [store string]

◘ The STOS instruction stores ALor AX at the extra segment memory location addressed by the DI register.

NAYANA.B.P Page8

◘ The STOSB (stores byte) instruction stores the byte in AL at the extra segment memory location addressed by DI.

◘ The STOSW (stores word) instruction stores AX in the extra segment memory location addressed by DI.

◘ After the byte (AL) or word (AX) is stored, the contents of DI increment or decrement.

MOVS:[move string]

One of the most useful string data transfer instructions is MOVS, because it transfers data from one

memory location to another.

This is the only instruction allows memory-to-memory transfer.

The MOVS instruction transfers a byte or word from the data segment location addressed by SI to the

extra segment location addressed by DI.

REPZ and REPNZ prefixes

➢ Used with CMPS & SCAS instruction for testing purposes.

➢ REPZ (repeat zero) - the same as REPE (repeat equal),will repeat the string operation as long as the

source anddestination operands are equal (ZF = 1) or until CXbecomes zero.

➢ REPNZ (repeat not zero) - the same as REPNE (repeatnot equal), will repeat the string operation as

long as thesource and destination operands are not equal (ZF = 0)or until CX becomes zero.

CMPS (compare string):

➢ CMPS instructionallows the comparison of twoarrays of data pointed at by registers SI & DI.

➢ The comparison can be performed byte at a time or word at a time by using CMPSB or CMPSW

Assuming that there is a spelling of “Europe” in standard dictionary and user types “Euorope”. Write a

program that compares these two and display the following message?

1. If they are equal, display “ spelling is correct”

2. If they are not-equal, display “ spelling is wrong”

Soln:

.MODEL SMALL

.DATA

DATA_DICT DB “Europe”

DATA_TYPED DB “Euorope”

MSG1 DB “ spelling is correct”

MSG2 DB “ spelling is WRONG”

.CODE

MOV AX, @DATA

MOV DS, AX

MOV ES, AX

NAYANA.B.P Page9

CLD ;DF=0 FOR INCREMENT

MOV SI, OFFSET DATA_DICT ;SI= OFFSET OF DICT

MOV DI, OFFSET DATA_TYPED ;DI= OFFSET OF TYPED

MOV CX, 06 ;LOAD THE COUNTER

REPE CMPSB ;REPEAT AS LONG AS EQUAL

JE OVER ;IF ZF=1 DISPLAY MSG1 OR IF ZF=0 DISPLAY MSG2

MOV DX, OFFSET MSG2

JMP DISP

OVER: MOV DX, OFFSET MSG1

DISP: MOV AH,09H

INT 21H

MOV AH, 4CH

INT 21H

END

SCAS (scan string):

➢ SCASB compares each byte of the array pointed atby ES:DI with the contents of the AL register.

➢ SCASB can search for a character in an array & iffound, it will be replaced with the desired character.

Write a program that scans the name “Mr.Gones” and replaces the “G” with letter “J” then displays the

corrected name?

.MODEL SMALL

.DATA

MSG DB “Mr.Gones”

.CODE

MOV AX,@DATA

MOV DS, AX

MOV ES,AX

CLD ;DF=0 FOR INCREMENT

MOV DI, OFFSET MSG ;ES:DI= OFFSET ARRAY

MOV CX,08 ; LENGTH OF ARRAY

MOV AL, „G‟ ;SCANNING FOR THE LETTER g

REPNE SCASB ;REPEAT THE SCANNING IF NOT EQUAL

JNE OVER

DEC DI ;DECREMENT TO POINT AT “G”

MOV [DI], „J‟ ; REPLACE “G” WITH “J”

OVER: MOV DX, OFFSET MSG ;DISPLAY THE CORRECTED NAME

MOV AH, 09H

INT 21H

MOV AH, 4CH

INT 21H

END

XLAT instruction and look-up tables:

➢ There is often a need in a computer application for a table that holds some important information.

➢ To access elements of a table, 8088/86 processors provide the XLAT (translate) instruction.

➢ To understand the XLAT instruction one must first understand the tables.

➢ A table is commonly referred to as a look-up table.

➢ Assume that one needs a table for the values of x2,Wherex is between 0 and 9.

➢ First the table is generated and stored in memory:

NAYANA.B.P Page10

➢ To access the square of any number from 0 to 9, by use of XLAT to do this register BX must have the

offset address of thelook-up table, and the number whose square is soughtmust be in the register AL.

➢ After XLAT execution, AL will have the square of the number.

➢ Example to get the square of 5 from the table:

➢ After execution AL will have 25 (19H), the square of 5.

XLAT:[translate byte in AL]

❖ The XLAT instruction translates or replaces a byte in the AL register with a byte from a lookup table in

memory.

❖ An XLAT instruction first adds the contents of AL to BX to form a memoryaddress within the data

segment.

❖ It then copies the contents of this address into AL.

Example: consider lookup table stored in table at 1000H, DS=1000H and AL=05H,after executions AL=6DH.

The operation of the XLAT instruction at the point just before 6DH is loaded into AL.

MISCELLANEOUS DATA TRANSFER INSTRUCTIONS

➢ This group consists of following instructions XCHG, LAHF, SAHF, XLAT, IN and OUT.

XCHG: [EXCHANGE]

The XCHG (exchange) instruction exchanges the contents of a register with the contents of any other

register or memory location.

The XCHG instruction cannot exchange segment registers or memory-to-memory data.

XCHG AL, BL ;Exchanges the contents of AL with BL

Example: Let AL=45H and BL=15H

After XCHG AL=15H and BL=45H

LAHF (load AH with flag register) and SAHF (load AH in flag register):

❖ The instruction LAHF copies the lower byte of the flag register to AH register

❖ Example: let AX=1234H and Flag register= 5678H

After LAHF AX=7834H and Flag register= 5678H

❖ The instruction SAHF copies the contents of AH into lower byte of the flag register

❖ Example: let AX=1234H and Flag register= 5678H

After LAHF AX=1234H and Flag register= 5612H

NAYANA.B.P Page11

IN and OUT:

▪ The IN and OUT instructions, perform I/O operations.

▪ An IN instruction transfers data from an external I/O device into AL, AX, or EAX

▪ An OUT transfers data from AL or AX to an external I/O device.

▪ Example:

IN AL, DX ;8 bits are input to AL from I/O port DX

OUT DX, AL ;8 bits are output to I/O port DX form AL

LEA:

◘ The LEA instruction loads a 16bit register with the offset address of the data.

◘ Example: LEA AX, NUMB ; loads AX with the offset address of NUMB

◘ The OFFSET directive performs the same function as an LEA instruction.

◘ For example, the MOV BX, OFFSET LIST performs the same function as LEA BX,LIST. Both

instructions load the offset address of memory location LIST into the BX register.

◘ What is the difference between MOV and LEA:

MOV BX, [DI] loads the data stored at the memory location addressed by [DI] into register BX.

LEA BX, [DI] loads the offset address specified by [DI] (contents of DI) into the BX register.

Increment (INC):

ʘ Increment (INC) adds 1 to a register or a memory location.

ʘ The INC instruction adds 1 to any register or memory location, except a segment register.

ʘ Example: INC BL ;BL= BL+1

Decrement (DEC):

ʘ Decrement (DEC) subtracts 1 from a register or the contents of a memory location.

ʘ Example:DEC BH ;BH = BH - 1

Assignments:

1. Explain the following instruction with an example: [June and Dec 2010, 11,12,13 ,14,15]

i) XLAT ii) SCAS iii) SAR iv) RENZ v) LODS

vi) CBW vii) MOVS viii) STOS ix) LAHF x)XCHG

2. What is positive and negative number?

3. Write a program to find the highest temperature

*** Life is your journey, Goals are your destination and Hard Work is your set of wheels. ***

NAYANA.B.P Page12

Module-3 MEMORY ADDRESS DECODING and I/O INTERFACE Chapter-2

MEMORY ADDRESS DECODING:

▪ In order to attach a memory device to the microprocessor, it is necessary to decode

the address sent from the microprocessor.

▪ Why to Decode Memory? Ans:-The 8088 has 20 address connections and the EPROM has 11

connections. The 8088 sends out a 20-bit memory address whenever it reads or writes data. Because the

EPROM has only 11 address pins, there is a mismatch that must be corrected.

▪ If only 11 of the 8088‟s address pins are connected to the memory, the 8088 can use only 2K bytes of

memory instead of the 1M bytes.

▪ The decoder corrects the mismatch by decoding address pins that do not connect to the memory

component.

▪ Without an address decoder, only one memory device can be connected to a microprocessor, which

would make it virtually useless.

▪ We can use NAND and 74LS138 chips as decoders.

Simple logic gate as address decoder:

▪ Memory chips have one or more CS (chip select) or CE (chip enable) pins that must be activated to

access the memory content.

▪ In connecting a memory chip to the CPU, the data bus is connected directly to the data pins of the

memory.

▪ Control signals MEMR and MEMW are connected to OE and WR pins of the memory chip.

▪ In case of address buses, the lower bits of the address go directly to the memory chip address pins, the

upper bits of the address are used to activate the Cs pin of the memory chip.

▪ The CS input is active low and can be activated using some simple logic gates such as NAND and

inverters.

Address range above memory chip

Example 1: For a given circuit find the address range?

NAYANA.B.P Page13

Soln:

Example 2:

74LS138 as decoder:

• 74LS138 has 3 inputs A, B, C generates 8 active low o/p‟s Yo to Y7.

• Each Y o/p is connected to the CS pin of memory chip allowing control of 8 memory block by single

74LS138.

• This eliminates the need for NAND and inverter gates.

• 74LS138 has additional three inputs i.e. G2A , G2B and G1

• To enable 74SL138: G2A = 0, G2B = 0, G1 = 1.

Example 1:

• In above figure A0 –A15 from CPU (µP) goes directly to A0 –A15 of the memory chip.

• A16 –A18 are used for A, B , C inputs of 74LS138. A19 is controlling the G1 pin of 74LS138.

NAYANA.B.P Page14

• For 74LS138 to be enable we need G2A & G2B should be grounded; G1 = 1.

• Depending on the status of the pins A, B, C one of the Y‟s is selected.

• To select Y4 we need CBA=100.

• This gives the address range C0000H to CFFFFH.

Problem 1: For a below figure find the address range for Y4, Y2, Y7 and verify the block size.

DATA INTEGRITY IN RAM AND ROM:

➢ When storing or transferring data from one place to another, a major concern is data integrity.

➢ There are many ways to ensure data integrity depending on the type of storage.

➢ The checksum method is used for ROM.

➢ The parity bit method is used for DRAM.

➢ The CRC (cyclic redundancy check) method is employed for mass storage devices such as hard disks

and for internet data transfer.

CHECKSUM BYTE:

❖ To ensure the integrity of the contents of ROM, every PC must perform a checksum calculation.

❖ Using a checksum byte, an extra byte tagged to the end of a series of bytes of data.

❖ To calculate the checksum byte of a series of bytes:

1. Add the bytes together and drop the carries.

2. Take the 2's complement of the total sum, and that is checksum byte, which becomes the last

byte of the stored information.

3. Add all the bytes, including the checksum byte.

❖ The result must be zero; if it is not zero; one or more bytes of data have been changed (corrupted).

NAYANA.B.P Page15

Parity bit generator/checker in the IBM PC

▪ Parity is used to detect two types of DRAM errors

▪ Hard error - some bits, or an entire row of memory cells in the memory chip get permanently stuck

high or low. Thereafter always producing 1 or 0, regardless of what is written into the cell(s).

▪ Soft error - a single bit is changed from 1 to 0 or 0 to 1. Due to current surge or certain particle

radiation in the air.

▪ Parity is used to detect such errors

▪ Including a parity bit to ensure RAM data integrity is the most widely used simplest & cheapest method.

NAYANA.B.P Page16

▪ This method can only indicate if there is a difference between the data written to memory, and data read.

▪ It cannot correct the error.

▪ IBM PC uses 74S280 parity bit generator and checker to implement the concept of parity bit

74S280 parity bit generator and checker:

▪ It has 9 inputs & 2 outputs.

▪ Depending on whether an even or odd number of ones appear in the input, the even or odd output is

activated as in Table.

▪ If all 9 inputs have an even number of 1 bits, the even output goes high, as in cases 1 and 4.

▪ If the 9 inputs have an odd number of high bits, the odd output goes high, as in cases 2 and 3.

▪ Inputs “A to H” is connected to the data bus, 8 bits.

▪ The “I” input is used as a parity bit to check the data byte read from memory.

16- BIT MEMORY INTERFACING:

ODD and EVEN banks:

• Figure above shows 1MB of memory, the concept of odd and even bank applies to the entire memory space of a given processor with 16 bit data bus.

• The 8086 has 20 bit address bus, so it can address 220 =1048576 addresses.

NAYANA.B.P Page17

• Each address represents a stored byte.

• To make it possible to read or write word with one machine cycle, memory for an 8086 is set up into 2

bank of up to 512KB each.

• One bank (even or low) contain all the data bytes which have even numbered address (data lines of this

bank is connected to the lower 8bit data line of processor i.e. D0 -D7)

• Other bank (odd or high) contain all the data bytes which have odd numbered address (data lines of this

bank is connected to the higher 8bit data line of processor i.e. D8 -D15)

• To distinguish between odd & even bytes, the CPU provides a signal called BHE (bus high enable).

• BHE, with A0 is used to select odd/even bytes.

• One bank (low bank) holds all the even numbered memory locations and the other bank (high bank)

holds all the odd numbered memory locations.

• The 8086, 80186, 80286 and 80386SX use the BHE signal (high bank) and the A0 address bit or BLE

signal (bus low enable) to select one or both banks of memory used for data transfer.

Memory cycle time and inserting waiting state:

▪ To access an external device such as memory or I/O, the CPU provides a fixed amount of time called

bus cycle time.

▪ The time from when the CPU provides the address at its address pins to when data is expected at its data

pins is called memory read cycle time.

▪ The processor such as 8088, the memory cycle time takes 4 clocks.

▪ In newer CPU, the memory cycle time is 2 clocks.

▪ If memory is slow and its access time does not match the memory cycle time of CPU, extra time can be

requested from the CPU to extend the cycle time. This extra time is called a wait state (WS).

▪ A wait state (TW) is an extra clocking period, inserted between T2 and T3 to lengthen the bus cycle.

▪ By having the WAIT state, slow memory and devices has at least one more cycle to get its data output.

▪ If data are written to the memory (Fig-A), the microprocessor sends or places the memory address on the

address bus, and issues a write (WR) to memory and IO/M = 0 for the 8088 and M/IO = 1 for the 8086.

▪ If data are read from the memory (Fig-B), the microprocessor sends or places the memory address on the

address bus, issues a read memory signal (RD), and accepts the data via the data bus.

Fig-A: simplified 8086/8088 write bus cycle Fig-B: simplified 8086/88 read bus cycle

Timing in General:

Microprocessors use the memory and I/O in bus-cycles. Each bus cycles equals to four system clocking periods

(1 clock period is often called a T state). If the clock is operated at 5 MHz (the basic operating frequency

8086/88 microprocessors), one bus cycle is complete in 800 ns.

▪ T1 - start of bus cycle.

▪ T2 – the WR or RD signals are issued by the µp-8088/86.

▪ These events cause the memory or I/O device to begin to perform a read or a write.

▪ T3 – During T3 data transferred between microprocessor and memory or I/O.

▪ T4 - all bus signals are deactivated in preparation for the next clock cycle.

NAYANA.B.P Page18

Write cycle is very similar to the read cycle. Main differences are

1. RD Strobe is replaced by WR

2. Data bus contains data for memory rather than data from memory

3. DT/R = 1instead of DT/R = 0

Bus Bandwidth:

• The rate of data transfer is called bus bandwidth.

• The wider the data bus, the higher the bus bandwidth.

• Bus bandwidth is measured in MB (megabytes) per second and is calculated as follows:

NAYANA.B.P Page19

THE PROGRAMMABLE PERIPHERAL INTERFACE (82C55)

The 82C55 programmable peripheral interface (PPI) is a very popular, low-cost interfacing

component found in many applications.

The PPI, which has 24 pins for I/O, that is divided into two groups (group-A & group-B) each of groups

consists of 12 pins.

Group-A consist of port A (PA7–PA0) and the upper half of port C (PC7–PC4), and group-B consists of

port B (PB7–PB0) and the lower half of port C (PC3–PC0).

The 82C55 can interface any TTL-compatible I/O device to the microprocessor.

The 82C55 is used in interfacing the keyboard and the printer to personal computers

It is form Intel and 8bit-wide.

It provides multiple I/O ports

Basic Description of the 82C55

Figure below illustrates the pin-out diagram of the 82C55

OR

PA7 – PA0: these lines are bidirectional; these lines can be selected as input or output lines based on

configuration.

PB7 – PB0: these lines are bidirectional; these lines can be selected as input or output lines based on

configuration.

PC7 – PC0: these lines are bidirectional; these lines can be selected as input or output lines based on

configuration. This port can be used as Port-C upper and Port-C lower.

D7 – D0: these lines are bidirectional and are connected to microprocessor data bus. The data, control word and

status signals are transferred on these lines between microprocessor and ports.

RD (read): when this pin is made low, the microprocessor reads the data from the port

WR (write): when this pin is made low, the microprocessor writes the data to the port

CS (Chip select): enables 82C55 for programming and reading or writing to port.

RESET: this is activated by the microprocessor

GND: ground connected to ground for proper operation

Vcc: is connected to +5V power supply.

A1 – A0: these address input pin selects

NAYANA.B.P Page20

Modes of operation of 82C55:

i) I/O mode

ii) Bit Set Reset (BSR) mode

The control word allows the programmer to select the pots, mode of operation, and type of operation

(read/write).

➢ Bit position 7 selects either command byte A or command byte B. If a 1 is placed in bit position 7,

command byte A is selected. If a 0 is placed in bit position 7, command byte B is selected

Mode-0 Operation (simple I/O)

➢ This mode is used to initialize ports to perform simple I/O function.

Mode –1 operation (handshake I/O)

➢ This mode is used to perform I/O operation using handshake signals.

➢ In this most of the pins of port C provides the handshake signals for port A and port B.

➢ Port C lines PC2-PC0 provides handshake signals to port B and PC5-PC3 provides handshake signals to

port A. The port C pins PC7 and PC6 are general-purpose I/O pins that are available for any purpose.

➢ Handshake signals used in mode-1 input are STB (strobe), IBF(input buffer full), INTR (interrupt

request) and INTE (interrupt enable)

➢ Handshake signals used in mode-1 output are OBF(output buffer full), ACK (acknowledge) INTR

(interrupt request) and INTE (interrupt enable)

Mode 2 operation (Bidirectional bus)

➢ In mode 2, which is allowed with group A only, port A becomes bidirectional, allowing data to be

transmitted and received over the same eight wires.

➢ Bidirectional bused data are useful when interfacing two computers.

➢ Handshake signals used in mode-2 are STB (strobe), IBF(input buffer full), OBF(output buffer full),

ACK (acknowledge) , INTR (interrupt request) and INTE (interrupt enable)

Control word format of 82C55

NAYANA.B.P Page21


1. With functional block diagram, explain working principle of 8255 PPI? Write the control words for

i) PORT A input, PORT B output and PORT C output (8M June 2010, Dec 2013)

ii) PORT A output, PORT B input and PORT C input in simple I/o mode.

iii) Port A and Port C lower as input and Port B and Port C upper as output ports

2. Explain with neat diagram control word format of 82C55?

3. Explain checksum byte in ROM with an example?

4. Explain 74S280 parity bit generator and checker?

5. Explain memory odd and even bank in association with BHE and A0?

6. Explain the following terms?

(i).bus cycle time (ii).waiting state (iii).bus bandwidth

7. What is address decoding? Explain with example NAND and 3:8 decoder?

NAYANA.B.P Page 1

Module-4 ARM Embedded Systems Chapter-1

▪ An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set computer)

architecture developed by Acorn Computers in the 1980s. Now it is developed by Advanced RISC

Machines (ARM).

▪ ARM does not make CPUs. They sell licenses for others to build and sell CPUs of their design and

architecture.

▪ ARM makes 32-bit and 64-bit RISC multi-core processors.

▪ Processors can have a single core or multiple cores. A processor with two cores is called a dual-core

processor and four cores are called a quad-core processor. The more cores a processor has, computation

is faster.

▪ A core is the processing unit which receives instructions and performs calculations, or actions, based on

those instructions.

▪ The ARM processor core is a key component of many successful 32-bit embedded systems.

▪ One of ARM’s most successful cores is the ARM7TDMIand is known for its high code density and low

power consumption.

▪ ARM processors are extensively used in consumer electronic devices such as smartphones, tablets,

multimedia players and other mobile devices.

▪ Because of their reduced instruction set, operate at a higher speed (executes millions of instructions per

second (MIPS), they require fewer transistors, which enables a smaller die size for the integrated

circuitry (IC) and lower power consumption.

Computer Architecture: It includes two types of architecture

Von Neumann architecture:

⬧ The computing system consists of a central processing unit (CPU) and a memory.

⬧ CPU fetches instruction from memory, decodes and executes it.

⬧ The memory holds both data and instructions.

⬧ Mathematician John Von Neumann implemented this architecture.

⬧ A single set of address/data bus between CPU and memory.

Harvard architecture:

♦ Harvard machine has separate memories for data and program.

♦ A two set of address/data bus between CPU and memory, this increases the performance.

♦ Harvard allows two simultaneous memory fetches.

♦ Most DSPs use Harvard architecture

http://whatis.techtarget.com/definition/CPU-central-processing-unit

http://search400.techtarget.com/definition/RISC

http://searchdatacenter.techtarget.com/definition/64-bit-processor

http://searchdatacenter.techtarget.com/definition/multi-core-processor

http://searchdatacenter.techtarget.com/definition/MIPS

NAYANA.B.P Page 2

Difference between Von Neumann architecture and Harvard architecture

Von Neumann architecture Harvard architecture

It is µp based It is µc based

It is general purpose system It is an embedded system

Power consumption is more Power consumption is more is less

Code enhancement is possible It is handy product code enhancement is not possible

Note: An embedded system is a system that has software embedded into computer-hardware, which makes a

system dedicated for an application (s) or specific part of an application or product or part of a larger system.”

Where Embedded Systems Are Using?

▪ Home: Ovens, TV, camera, dishwasher, cell phones, MP3 players etc.

▪ Medical: imaging system (XRAY, MRI), patient monitors etc.

▪ Automotive: Braking System, Music Player, Tire-Pressure Monitoring System, Airbags, Power

Windows and GPS etc.

▪ Communications: satellites, network routers, switches, hubs, ATM [automatic teller machines] etc.

▪ Computer peripherals: printer, scanner, displays, fax machines etc.

The RISC design philosophy

▪ The ARM core uses RISC architecture. RISC is a design philosophy aimed at deliveringsimple but

powerful instructions that execute within a single cycle at a high clock speed.

▪ The RISC philosophy concentrates on reducing the complexity of instructions performedby the

hardware.

▪ The RISC philosophy is implemented with four major design rules:

Instructions:

• RISC processors have a reduced number of instructions. These instructions can be executed in a single

cycle.

• Each instruction is a fixed length to allowthe pipeline to fetch next instructions before decoding the

current instruction.

• Incontrast, in CISC processors the instructions are often of variable size and take manycycles to execute.

Pipelines:

• The processing of instructions is broken down into smaller units that can beexecuted in parallel by

pipelines.

• The pipeline advances by one step on each cyclefor maximum throughput.

• There isno need for an instruction to be executed by a mini-program called microcode as onCISC

processors.

Registers:

• RISC machines have a large general-purpose register set.

• Any register cancontain either data or an address.

• In contrast, CISC processors have dedicated registers for specificpurposes.

Load-store architecture:

• The processor operates on data held in registers.

• Separate loadand store instructions transfer data between the register bank and memory.

• Memory accesses are costly, we can use data items held in the register bank multipletimes without

needing multiple memory accesses.

• In contrast, with a CISC design thedata processing operations act on memory directly.

NAYANA.B.P Page 3

Figure CISC v/s RISC

• These design rules allow a RISC processor to be simpler, and thus the core can operateat higher clock frequencies. In contrast, CISC processors are more complexand operate at lower clock frequencies

Reduced instruction set computer-[RISC] Complex instruction set computer-[CISC]

RISC processors have smaller set of instruction with few addressing modes

CISC processors have lager set of instruction with many addressing modes

Pipelining is the major feature Does not supports pipelining

Single clock is used Multiple clock is used

RISC emphasizes compiler complexity CISC emphasizes hardware complexity

Decoding of instruction is simple complex

Execution time is very less more

Easy to design Hard to design

POWERPC and SHARC use RISC. The best example is X86 architecture

The ARM Design Philosophy

▪ There are a number of physical features that have driven the ARM processor design.

▪ First,portable embedded systems require some form of battery power. The ARM processor hasbeen

specifically designed to be small to reduce power consumption and extend battery operation-essential

for applications such as mobile phones and personal digital assistants(PDAs).

▪ High code density is another major requirement since embedded systems have limitedmemory due to

cost and/or physical size restrictions. High code density is useful forapplications that have limited on-

board memory.

▪ Embedded systems are price sensitive and use slow and low-cost memorydevices. The use of low-cost

memory devices produces substantial savings.

▪ Another important requirement is to reduce the area of the die taken up by the embeddedprocessor. For

a single-chip, the smaller the area used by the embedded processor,the more available space for

specialized peripherals. This in turn reduces the cost of thedesign and manufacturing.

▪ ARMhas incorporated hardware debug technology within the processor so that softwareengineers can

view what is happening while the processor is executing code. So that software engineers can resolve

issues faster, this has a direct effect on the time to market and reduces overall development costs.

Instruction Set for Embedded Systems

The ARM instruction set differs from the pure RISC definition in several ways that makethe ARM instruction

set suitable for embedded applications:

■ Variable cycle execution for certain instructions:

Not every ARM instruction executesin a single cycle. For example, load-store-multiple instructions vary in the

numberof execution cycles depending upon the number of registers being transferred.

■ Inline barrel shifter:

The inline barrel shifter isa hardware component that preprocesses one of the input registers before it is usedby

an instruction. This improves coreperformance.

NAYANA.B.P Page 4

■ Thumb 16-bit instruction set:

ARM enhanced the processor core by adding a second16-bit instruction set called Thumb that permits the ARM

core to execute either16- or 32-bit instructions.

■ Conditional execution:An instruction is only executed when a specific condition hasbeen satisfied. This

feature improves performance and code density by reducing branchinstructions.

■ Enhanced instructions:

The enhanced digital signal processor (DSP) instructions wereadded to the standard ARM instruction set. These

instructions allow ARM processor to performfaster operation, insome cases to replace the traditional

combinations of a processor plus a DSP.

These additional features have made the ARM processor one of the most commonlyused 32-bit embedded

processor cores. Many of the top semiconductor companies aroundthe world produce products based around the

ARM processor.

Embedded System Hardware:

▪ Figure shows a typical embedded device based on an ARM core. Each box representsa feature or

function. The lines connecting the boxes are the buses carrying data.

Four main hardware components:

▪ The ARM processorcontrols the embedded device. Different versions of the ARM processor are

available to suit the desired operation.

▪ Controllers coordinate important functional blocks of the system. Two commonly found controllers are

interrupt and memory controllers.

▪ The peripherals: provide all the input-output capability external to the chip.

▪ A busis used to communicate between different parts of the device.

ARM Bus Technology

➢ Embedded devices use an on-chip bus and that allows different peripheral devices to be interconnected

with an ARM core.

➢ There are two different classes of devices attached to the bus.

➢ The ARM processor core(bus master): a logical device capable of initiating a data transfer with another

device across the same bus.

NAYANA.B.P Page 5

➢ Peripherals (bus slaves):—logical devices capable only of responding to a transfer request from a bus

master device.

A bus has two architecture levels.

❖ The first is a physical level that covers the electricalcharacteristics and bus width (16, 32, or 64 bits).

❖ The second level deals with protocol—the logical rules that govern the communication between the

processor and a peripheral.

AMBA Bus Protocol

✓ The Advanced Microcontroller Bus Architecture (AMBA) was introduced in 1996 and has been widely

adopted as the on-chip bus architecture used for ARM processors.

✓ The first AMBA buses introduced were the ARM System Bus (ASB) and the ARM Peripheral Bus

(APB).

✓ Later ARM introduced another bus design, called the ARM High Performance Bus (AHB).

✓ AHB provides higher data throughput than ASB

✓ AHB bus for the high performance peripherals, an APB bus for the slower peripherals, and a third bus

for external peripherals.

✓ This external bus requires a specialized bridge to connect with the AHB bus.

Memory

• An embedded system has some form of memory to store and execute code.

Hierarchy

• All computer systems have memory arranged in some form of hierarchy.

• Figure shows the memory trade-offs: the fastest memory cache is physically located nearer the ARM processor core and the slowest secondary memory is set further away.

• Generally the closer memory is to the processor core, the more it costs and the smaller its capacity.

• The cache is placed between main memory and the core.

• It is used to speed up data transfer between the processor and main memory.

• The main memory is large—around 256 KB to 256 MB (or even greater), depending on the application

• Secondary storage is the largest and slowest form of memory.

• Hard disk drives and CD-ROM drives are examples of secondary storage.

• These days secondary storage may vary from 600 MB to 60 GB.

Width

• The memory width is the number of bits the memory returns on each access—typically 8, 16, 32, or 64

bits.

• The memory width has a direct effect on the overall performance

Types

• There are many different types of memory.

• Some of the most popular memory devices found in ARM-based embedded systems are:

NAYANA.B.P Page 6

• Read-only memory (ROM) is used in high-volume devices that require no updates or corrections.

• Many devices also use a ROM to hold boot code.

• Flash ROM can be written to as well as read, but it is slow to write so you shouldn’t use it for holding

dynamic data.

• Its main use is for storing long term data that needs to be preserved after power is off.

• Dynamic random access memory(DRAM)is the most commonly used RAM for devices. Its cost is low.

• DRAM is dynamic— it needs to have its storage cells refreshed and we need to set up a DRAM before

using the memory.

• Static random access memory (SRAM) is faster than the DRAM.

• SRAM is static—the RAM does not require refreshing.

• Synchronous dynamic random access memory (SDRAM) is one of many subcategories of DRAM.

• Even faster synchronous DRAMs, known as double-data rate (DDR) SDRAMs or DDR2 and DDR3

SDRAMs, are now in use.

Peripherals

▪ Embedded systems that interact with the outside world need some form of peripheral device.

▪ A peripheral device performs input and output functions for the chip by connecting to other devices or

sensors that are off-chip.

▪ Controllers are specialized peripherals that implement higher levels of functionality within an embedded

system.

▪ Two important types of controllers are memory controllersand interrupt controllers.

Memory Controllers

▪ Memory controllers connect different types of memory to the processor bus.

▪ On power-up a memory controller is configured in hardware to allow certain memory devices to be

active.

▪ Some memory devices must be set up by software; for example, when using DRAM, we have to set up

thememory timings and refresh rate before it can be accessed.

Interrupt Controllers

▪ When a peripheral or device requires attention, it raises an interrupt to the processor.

▪ There are two types of interrupt controller available for the ARM processor: the standard interrupt

controller and the vector interrupt controller (VIC).

▪ The standard interrupt controller sends an interrupt signal to the processor core when an external device

requests servicing.

▪ The interrupt handler determines which device requires servicing by reading a device bitmap register in

the interrupt controller.

▪ The VIC is more powerful than the standard interrupt controller because it prioritizes interrupts and

simplifies the determination of which device caused the interrupt.

Embedded System Software

➢ An embedded system needs software to drive it. Figure below shows four typical software components

required to control an embedded device.

➢ The initialization code is the first code executed on the board

➢ It sets up the minimum parts of the board before handing control over to the operating system.

NAYANA.B.P Page 7

➢ The operating system provides an infrastructure to control applications and managehardware system

resources.

➢ Many embedded systems do not require a full operating system but merely a simple task scheduler.

➢ ARM processors support over 50 operating systems. We can divide operating systemsinto two main

categories: real-time operating systems (RTOSs) and platform operatingsystems.

➢ RTOSs provide guaranteed response times to events.

➢ The Linux operating system isa typical example of a platform operating system.

➢ The device drivers provide a software interface to the peripherals on the hardware device.

➢ Finally, an application performs one of the tasks required for a device.

➢ For example, a mobile phone might have a diary application. There may be multiple applications

running on the same device, controlled by the operating system.

Difference between Microprocessor and microcontroller:

SN Microprocessor (µP) Microcontroller (µC)

1 µP = CPU µC = CPU + Memory + peripherals

2 It is a processor. Memory and i/o components have to be connect externally

It is a processor along Memory and i/o components

3 Larger circuit small

4 Cost of entire system is large less

5 General purpose Specific purpose

6 Only few instructions are conditional All instructions are conditional

7 Has many opcode for moving data from memory to CPU

One or two opcode for moving data from memory to CPU

8 Used in PC Mobiles, MP3 players, washing m/c etc

9 Ex: 8086, Intel Pentium Ex: 8051 etc

10

Block diagram of µP

Block diagram of µC

NAYANA.B.P Page 8

Module-4 ARM Processor Fundamentals Chapter-2

ARM CORE:

▪ ARM core as functional units connected by data buses, as shown in below Figure.

▪ Where, the arrows represent the flow of data, the lines represent thebuses, and the boxes represent either

an operation unit or a storage area.

▪ Data enters the processor core through the Data bus. The data may be an instruction toexecute or a data

item.

▪ The instruction decoder translates instructions before they are executed.

▪ The ARM processor, like all RISC processors, uses load-store architecture.

▪ Loadinstructions copy data from memory to registers in the core, and the store instructions copy data

from registers to memory.

▪ Data items are placed in the register file—a storage bank made up of 32-bit registers.

▪ Since the ARM core is a 32-bit processor, most instructions treat the registers as holdingsigned or

unsigned 32-bit values.

▪ The sign extend hardware converts signed 8-bit and 16-bitnumbers to 32-bit values as they are read from

memory and placed in a register.

▪ ARM instructions typically have two source registers, Rn and Rm, and a single result ordestination

register, Rd.

▪ Source operands are read from the register file using the internalbuses A and B, respectively.

▪ The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values Rn and

Rm from the A and B buses and computes a result.

▪ Data processinginstructions write the result in Rd directly to the register file.

▪ One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel

shifter before it enters the ALU.

▪ For load and store instructions the incrementer updates the address register before the core reads or

writes the next register value from or to the next sequentialmemory location.

▪ The processor continues executing instructions until an exception orinterrupt changes the normal

execution flow.

NAYANA.B.P Page 9

Registers:

▪ General-purpose registers hold either data or an address.

▪ They are identified with theletter r prefixed to the register number.

▪ For example, register 4 is given the label r4.

▪ The register file contains all the registers available to a programmer.

▪ Which registers arevisible to the programmer depend upon the current mode of the processor.

▪ Figure below shows the active registers available in user mode.

▪ All the registers shown are 32 bits in size.

▪ There are up to 18 active registers: 16 data registers and 2 processor status registers.

▪ Thedata registers are visible to the programmer as r0 to r15.

▪ The ARM processor has three registers assigned to a particular task or special function:r13, r14, and r15.

▪ Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stackin the current

processor mode.

▪ Register r14 is called the link register (lr) and is where the core puts the return addresswhenever it calls

a subroutine.

▪ Register r15 is the program counter (pc) and contains the address of the next instructionto be fetched by

the processor.

▪ In addition to the 16 data registers, there are two program status registers: cpsrand spsr(the current and

saved program status registers, respectively).

Pipeline

▪ A pipeline is the mechanism a RISC processor uses to execute instructions.

▪ Using a pipelinespeeds up execution by fetching the next instruction while other instructions are

beingdecoded and executed.

▪ Figure shows a ARM7 three-stage pipeline:

Fetch:loads an instruction from memory or the instruction is fetched from memory.

NAYANA.B.P Page 10

Decode:identifies the instruction to be executed or the instruction’s opcode and operands are decoded to

determine what function to perform.

Execute:processes the instruction and writes the result back to a register or the decoded instruction is

executed.

▪ Example:The three instructions are placed into the pipeline sequentially. In the first cycle thecore

fetches the ADD instruction from memory. In the second cycle the core fetches theSUB instruction and

decodes the ADD instruction. In the third cycle, both the SUB andADD instructions are moved along

the pipeline. The ADD instruction is executed, the SUBinstruction is decoded, and the CMP instruction

is fetched.

▪ The pipeline allows the core to execute an instruction every cycle.

▪ As the pipeline length increases, the amount of work done at each stage is reduced.

▪ The pipeline design for each ARM family differs.

ARM9 five-stage pipeline

ARM10 six-stage pipeline

Exceptions, Interrupts, and the VectorTable

• When an exception or interrupt occurs, the processor suspends normal execution and starts loading

instructions from the exception vector table

• When an exception or interrupt occurs, the processor sets the pcto a specific memoryaddress.

• The address is within a special address range called the vector table.

• The vector table contains an instructions are designed to handle aparticular exception or interrupt.

• The memory map address 0x00000000 is reserved for the vector table. On some processors the vector

table can be optionally located at a higher addressin memory (starting at the offset 0xffff0000).

• Reset vectoris the location of the first instruction executed by the processor when poweris applied.

• Undefined instruction vectoris used when the processor cannot decode an instruction.

• Software interrupt vectoris called when you execute a SWI instruction.

• Pre-fetch abort vectoroccurs when the processor attempts to fetch an instruction from anaddress

without the correct access permissions.

• Data abort vectoris similar to a pre-fetch abort but is raised when an instruction attemptsto access data

memory without the correct access permissions.

NAYANA.B.P Page 11

• Interrupt request vectoris used by external hardware to interrupt the normal executionflow of the

processor. It can only be raised if IRQs are not masked in the cpsr.

• Fast interrupt request vectoris similar to the interrupt request but is reserved for hardwarerequiring

faster response times. It can only be raised if FIQs are not masked in the cpsr.

Current Program Status Register:

• The ARM core uses the cpsr to monitor and control internal operations.

• The cpsr is a dedicated 32-bit register and resides in the register file.

• The cpsr is divided into four fields, each 8 bits wide: flags, status, extension, and control.

• In current designs the extension and status fields are reserved for future use.

• The controlfield contains the processor mode, state, and interrupt mask bits.

• The flags field containsthe condition flags.

• Some ARM processor cores have extra bits allocated. For example, the J bit, which canbe found in the

flags field, is only available on Jazelle-enabled processors, which execute8-bit instructions.

OR

NAYANA.B.P Page 12

Processor Modes:

• The processor mode determines which registers are active and the access rights to the cpsr register.

• Each processor mode is either privileged or non-privileged:

• A privileged modeallows full read-write access to the cpsr.

• A non-privileged mode only allows readaccess to the control field in the cpsr but still allows read-write

access to the condition flags.

• There are seven processor modes in total: six privileged modes (abort, fast interruptrequest, interrupt

request, supervisor, system, and undefined) and one nonprivileged mode(user).

• The processor enters abort mode when there is a failed attempt to access memory.

• Fastinterrupt request and interrupt request modes correspond to the two interrupt levels availableon the ARM processor.

• Supervisor mode is the mode that the processor is in after reset.

• System mode is a specialversion of user mode that allows full read-write access to the cpsr.

• Undefined mode is usedwhen the processor encounters an instruction that is undefined or not supported

by theimplementation.

• User mode is used for programs and applications.

Banked Registers:

❖ Figure shows all 37 registers in the register file. Of those, 20 registers are hidden from a program at

different times. These registers are called banked registers and are identifiedby the shading in the

diagram.

NAYANA.B.P Page 13

❖ They are available only when the processor is in a particularmode; for example, abort mode has banked

registers r13_abt, r14_abt and spsr_abt.

❖ Bankedregisters of a particular mode are denoted by _mode.

❖ Every processor mode except user mode can change mode by writing directly to themode bits of the

cpsr.

❖ All processor modes except system mode have a set of associatedbanked registers that are a subset of the

main 16 registers.

❖ The processor mode can be changed by a program that writes directly to the cpsr or by hardware when

the core responds to an exception or interrupt.

❖ Figure also shows a new register appearing in interrupt request mode: r13_irq ,r14_irq and spsr.

❖ The savedprogram status register(spsr), which stores the previous mode’s cpsr.

State and Instruction Sets

♦ The state of the core determines which instruction set is being executed.

♦ There are threeinstruction sets: ARM, Thumb, and Jazelle.

♦ The ARM instruction set (32-bit instruction) is only active whenthe processor is in ARM state.

♦ Similarly the Thumb instruction set is only active whenthe processor is in Thumb state. Once in Thumb

state the processor is executing purelyThumb 16-bit instructions.

♦ The Jazelle J and Thumb T bits in the cpsr reflect the state of the processor.

♦ When bothJ and T bits are 0, the processor is in ARM state and executes ARM instructions.

♦ When the T bit is 1, then the processor is inThumb state.

♦ The ARM designers introduced a third instruction set called Jazelle. Jazelleexecutes8-bit instructions

and is designed to speed up the execution of Java byte codes.

♦ The Jazelle instruction set is a closed instruction set and is not openly available.

Interrupt Masks

▪ Interrupt masks are used to stop specific interrupt requests from interrupting the processor.

▪ There are two interrupt request levels available on the ARM processor core—interruptrequest (IRQ) and

fast interrupt request (FIQ).

▪ The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which control the maskingof IRQ and FIQ,

respectively.

▪ The Ibit masks IRQ when set to binary 1, and similarly theF bit masks FIQ when set to binary 1.

NAYANA.B.P Page 14

Condition Flags

▪ Condition flags are updated by comparisons and the result of ALU operations

▪ When a bit is a binary 1 we use a capital letter; when a bit is a binary 0, we use a lowercaseletter.

▪ For the condition flags a capital letter shows that the flag has been set. For interruptsa capital letter

shows that an interrupt is disabled.

Conditional Execution

• Conditional execution controls whether or not the core will execute an instruction.

• Prior to execution, the processor compares thecondition attribute with the condition flags in the cpsr.

• If they match, then the instructionis executed; otherwise the instruction is ignored.

• The condition attribute is post-fixed to the instruction mnemonic.

• When acondition mnemonic is not present, the default behavior is to set it to always (AL) execute.

Core Extensions:

• The hardware extensions are standard components placed next to theARM core.

• They improve performance, manage resources, and provide extra functionality and are designed to provide flexibility in handling particular applications.

• EachARMfamilyhas different extensions available.

• There are three hardware extensions ARM wraps around the core: cache and tightlycoupled memory, memory management, and the coprocessor interface.

Cache and Tightly Coupled Memory

• The cache is a block of fast memory placed between main memory and the core.

• It allows formore efficient fetches from some memory types.

• With a cache the processor core can runfor the majority of the time without having to wait for data from

slow external memory.

• ARM has two forms of cache. The first is found attached to the Von Neumann–stylecores. It combines

both data and instruction into a single unified cache, as shown in Figure.

NAYANA.B.P Page 15

• A cache provides an overall increase in performance but at the expense of predictableexecution.

• But for real-time systems it is paramount that code execution is deterministic—the time taken for

loading and storing instructions or data must be predictable.

• This isachieved using a form of memory called tightly coupled memory (TCM).

• TCM is fast SRAMlocated close to the core and guarantees the clock cycles required to fetch

instructions ordata—critical for real-time algorithms requiring deterministic behavior.

Coprocessors

• Coprocessors can be attached to the ARM processor.

• A coprocessor extends the processingfeatures of a core by extending the instruction set

• More than one coprocessor can be added to the ARM core via the coprocessorinterface.

Assignment Questions:

1. Explain the ARM design philosophy?

2. Explain the RISC design philosophy?

3. Explain embedded system hardware with diagram briefly

4. Mention any five difference between RISC and CISC

5. Mention any five difference between µp and µc

6. Explain embedded system software

7. With neat diagram explain ARM core?

8. Briefly explain CPSR with neat diagram?

9. What is pipeline? Explain ARM7 three stage pipeline?

10. What is Exceptions, Interrupts, and the Vector Table

11. Explain with neat diagram ARM registers?

12. What is banked register? Explain with neat diagram.

13. What is the different state of ARM processor? Mention its instruction size and status of J and T bit?

EMBEDDED SYSTEM OF HARDWARE

EMBEDDED SYSTEM OF SOFTWARE

ARM CORE DATA FLOW MODEL

REGISTERS

Program Status Register

Process modes

• There are seven processor modes in total: six privileged modes (abort, fastinterrupt request, interrupt request, supervisor, system, and undefined) and onenonprivileged mode(user).

• The processor enters abort mode when there is a failed attempt to accessmemory.

• Fast interrupt request and interrupt request modes correspond to the twointerrupt levels available on the ARM processor.

• Supervisor mode is the mode that the processor is in after reset.

• System mode is a special version of user mode that allows full read-write access tothe cpsr.

• Undefined mode is used when the processor encounters an instruction that isundefined or not supported by the implementation.

• User mode is used for programs and applications.

BANKED REGISTERS

CONDITIONAL FLAGS

PIPELINING

Brief History of the 80x86 familiesise.svcengg.com/images/userfiles/files/17CS44 - MPMC.pdf ·...

Documents

Transcript of Brief History of the 80x86 familiesise.svcengg.com/images/userfiles/files/17CS44 - MPMC.pdf ·...