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Dice GameChap 22

1-to-6 Cntr

1-to-6 Cntr

Adder

CntbCnta

PointRegister

Comparator

dicesum

TestLogic

Control

Roll

D7

D11D2312

eq

Dpathb.vhd

Dpatha.vhd

control.vhd

Rb

Ra

sp

win

lose

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Dice Game Implementation

• Dice game implemented in three 22V10 PLDs– control.vhd (Finite State Machine)

– dpatha.vhd (two 1-6 counters, adder)

– dpathb.vhd (point register, comparator, test logic)

• The Control FSM is implemented using one-hot encoding.– Outputs q0, q1, q5 are states S0, S1, S5. Output “win” is

state S2, output “lose” is state S3. Outputs q0,q1,q5 are available just for debugging purposes.

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Finite State Machine Changes

Asynchronous Reset now use to exit states S2, S3. Resets back to State S0.

S2 Win

S3 Lose

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Finite State Machine Changes (cont).

Because we don’t have debounced switches, added extra “roll” input called “Ra”. Changed States S1, S5 to use Ra, not Rb.

S1

Ra 0

1Roll

S5

Ra 0

1Roll

This means that to roll the dice, you use flip switch Rb up, then down. This starts the dice rolling. To stop the dice, Flip Ra switch up then down.

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“dpatha” Details

ClkC 3

EN

R

Cntr

Q

Roll(from control)

Reset

C 3

EN

R

QLogic

Roll

Clk

Reset

Cntb

Cnta

A

dder

4

dicesum

3

Ena

Ena = 1 when Cntb = 6 and Roll = 1

Counters count 1,2,3,4,5,6,1,2, etc

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“dpathb” Details

DIN4

C

LD

Register

Point

4

R

Dicesum(from dpatha)

sp(from control)

Compare

Clk

Reset

Eq(1 if point = sum)

TestLogic

D7 (1 if sum=7)

D7 (1 if sum=11)

D2312 (1 if sum=2,3 or 12)

“sp” (save point) loads value of dicesum into register.