booth_wallace_multiplier.ppt

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Booth Encoded Wallace Tree Multiplier Booth Encoded Wallace Tree Multiplier Ruida Yun Ruida Yun Nahid Rahman Nahid Rahman

description

powerpoint for booth wallace multiplier

Transcript of booth_wallace_multiplier.ppt

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Booth Encoded Wallace Tree MultiplierBooth Encoded Wallace Tree Multiplier

Ruida YunRuida Yun

Nahid RahmanNahid Rahman

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ImportanceImportance

Booth encoding is an effective method for Booth encoding is an effective method for multiplication of both positive and multiplication of both positive and negative numbers.negative numbers.

Wallace tree reduces the number of partial Wallace tree reduces the number of partial products to be added into 2 final products to be added into 2 final intermediate results.intermediate results.

Carry Look-ahead Adder used to add these Carry Look-ahead Adder used to add these results to generate the final output.results to generate the final output.

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Background of our work…Background of our work…

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Multiplication of unsigned (+ve ) Multiplication of unsigned (+ve ) numbersnumbers

Multiplicand 0110 (=6)Multiplicand 0110 (=6)Multiplier x 1011 (=11) Multiplier x 1011 (=11) ---------------------- 0110 0110

0110 0110 00000000

01100110----------------------01000010 (=66)01000010 (=66)

Logically can be expressed as AND operation:Logically can be expressed as AND operation:if MR=1 assign MDif MR=1 assign MD

if MR=0 assign all zerosif MR=0 assign all zeros

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In a 4-bit 2’s complement number In a 4-bit 2’s complement number system…..system…..

Multiplicand 0110 (=6)Multiplicand 0110 (=6)Multiplier Multiplier x 1011 (=-5, signed x 1011 (=-5, signed

number) number) ---------------------- 0110 0110

0110 0110 00000000

01100110 ---------------------- 01000010 (=66)01000010 (=66)

Therefore, 8-bit result cannot be generated from 2 Therefore, 8-bit result cannot be generated from 2 4- 4- bit inputs in a signed number system.bit inputs in a signed number system.

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Standard Multiplier MethodStandard Multiplier Method

Multiplicand 00000110 (=6)Multiplicand 00000110 (=6)Multiplier x 11111011 (=-5, signed number) Multiplier x 11111011 (=-5, signed number) ------------------------------

00000110000001100000011000000110

0000000000000000 0000011000000110 0000011000000110 0000011000000110

0000011000000110 ------------------------------------------------ 11100010 (=-30) 11100010 (=-30)

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Booth’s AlgorithmBooth’s Algorithm

Introduces a new symbol: í indicating Introduces a new symbol: í indicating multiplication by -1.multiplication by -1.

Multiplier is recoded in terms of 1, 0 & í.Multiplier is recoded in terms of 1, 0 & í. Example: 1011 is recoded as: í10 íExample: 1011 is recoded as: í10 í AND operation changes as:AND operation changes as:

if MR=1 assign MDif MR=1 assign MD if MR=0 assign all zerosif MR=0 assign all zeros if MR= í assign -MD if MR= í assign -MD

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Our MR now becomes 4-bit again..Our MR now becomes 4-bit again..

Multiplicand 0110 (=6)Multiplicand 0110 (=6)

Multiplier x Multiplier x í10 íí10 í (=-5) (=-5)

------------------------------

11111010 (-MD, sign extended) 11111010 (-MD, sign extended) 00000000 (All zeros) 00000000 (All zeros) 00000110 (MD, sign 00000110 (MD, sign extended) extended)

11111010 (-MD, sign extended)11111010 (-MD, sign extended)

--------------------------------

11100010 (=-30 , 8 bits of LSB)11100010 (=-30 , 8 bits of LSB)

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GeneratingGenerating ííRecoRecoded ded MRMR

M[i]M[i] M[i-1]M[i-1] xx zz

00 00 00 00 00

11 00 11 00 11

íí 11 00 11 11

00 11 11 00 00

Not possible to implement Not possible to implement in hardware.in hardware.

Therefore, done by Therefore, done by inspecting a multiplier bit inspecting a multiplier bit and its previous bit and and its previous bit and generating 2 control generating 2 control signals x and z. signals x and z.

Whether the MR is í, 1 or 0, Whether the MR is í, 1 or 0, depends on these signals depends on these signals according to:according to:

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Wallace TreeWallace Tree

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Tasks in ProjectTasks in Project

Generating 2’s complement of MD for Generating 2’s complement of MD for –MD.–MD.

Recoding MR/generating x and z.Recoding MR/generating x and z. Generating partial products.Generating partial products. Sign extension.Sign extension. Compressing the partial products.Compressing the partial products. Adding the final 2 operands for Adding the final 2 operands for

multiplication result.multiplication result.

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Team ManagementTeam Management

Nahid:Nahid:• Booth EncoderBooth Encoder• Partial Product GeneratorPartial Product Generator

Ruida:Ruida:• Wallace TreeWallace Tree• Carry Look-ahead AdderCarry Look-ahead Adder

(Smaller modules generated and tested as (Smaller modules generated and tested as necessarynecessary

Website: http://www.eecs.tufts.edu/~ryun01/vlsi)Website: http://www.eecs.tufts.edu/~ryun01/vlsi)

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Modules in our Modules in our project…..project…..

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2’s Complement Generator2’s Complement Generator

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Booth EncoderBooth Encoder

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Partial Product Generator (a)Partial Product Generator (a)

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Partial Product generatorPartial Product generator

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Wallace TreeWallace Tree

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Carry Look-ahead AdderCarry Look-ahead Adder

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MultiplierMultiplier

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Chip ArchitectureChip Architecture

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Floor planFloor plan

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Final LayoutFinal Layout

No, it’s not a No, it’s not a

gun…gun…

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Verilog Simulation ResultsVerilog Simulation Results

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LVS for Final ChipLVS for Final Chip

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Spectre_S Simulation for Final ChipSpectre_S Simulation for Final Chip

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Post-Layout Simulation for Final ChipPost-Layout Simulation for Final Chip

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Full Chip Implementation DetailsFull Chip Implementation Details

• Fabrication Process: Fabrication Process: AMI 0.6u C5NAMI 0.6u C5N• Final Chip Area: Final Chip Area: 4.2mm*1.5mm4.2mm*1.5mm• Number of PMOS: Number of PMOS: 30403040• Number of NMOS: Number of NMOS: 30403040• Total number of transistors: Total number of transistors: 60806080• Speed: Speed: 20 MHz20 MHz• Power Dissipation: Power Dissipation: 15.14 mW15.14 mW

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DrawbacksDrawbacks

• Original Booth’s algorithm used where modified Original Booth’s algorithm used where modified radix-4 algorithm could be used.radix-4 algorithm could be used.

• Ripple Carry Adder used in 2’s Complement Ripple Carry Adder used in 2’s Complement Generator.Generator.

• Area and time not optimized; very slow chip.Area and time not optimized; very slow chip.

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Goals AchievedGoals Achieved

As novice cadence users, our primary goal for this project As novice cadence users, our primary goal for this project was more of an academic nature: was more of an academic nature:

• We  have been able to achieve  completeness and overall We  have been able to achieve  completeness and overall

functional accuracy in our work. functional accuracy in our work. • The project was foundational and served as a great learning The project was foundational and served as a great learning

experience. experience. • It also provided us with valuable experience in effective It also provided us with valuable experience in effective

collaboration, work ethics, and a very enjoyable ongoing collaboration, work ethics, and a very enjoyable ongoing intercommunication between different project groups.intercommunication between different project groups.

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AcknowledgementsAcknowledgements

• Our research advisor Prof. Valencia Joyner for all her Our research advisor Prof. Valencia Joyner for all her support.support.

• All our new friends at the ECE department.All our new friends at the ECE department.

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Thank you…..Thank you…..

~Ruida,~Ruida,

Nahid.Nahid.