book
2
Philips Semiconductors Preliminary specification ATSC 8-VSB Demodulator and Decoder TDA8960 1 FEATURES General features • One chip ATSC compliant 8-VSB demodulator and concatenated Trellis (Viterbi)/Reed-Solomon decoder with deinterleaver and de-randomizer • 3.3V device • 64 lead QFP64 package • Boundary Scan Test • Output format: 8-bit wide MPEG-2 transport stream 8-VSB demodulator • On-chip digital circuitry for tuner AGC control • Square-Root Raised-Cosine filter with 11.5% roll-off factor • Fully internal carrier recovery loop with programmable loop filter • Mostly internal clock recovery and AGC loops with programmable loop filters • External indication of demodulator lock Adaptive Equalizer • Feed forward including a decision feedback structure (DFE) • Range of -2.3 μs to +10.5 μs • Adaptation based on ATSC field sync (trained) and/or 8-VSB data (blind) • Capability to read and write taps via I 2 C-bus Trellis (Viterbi) decoder • Rate 2/3 (Rate 1/2 Ungerboeck code based) Reed-Solomon decoder • Internal convolutional de-interleaving • External indication of uncorrectable error (Transport Error Indicator bit in MPEG packet header is also set) • Followed by de-randomizer based on ATSC standard I 2 C interface • I 2 C-bus interface to initialize and monitor the demodulator and FEC decoder. An operation without I 2 C (default) is possible. Applications • Digital ATSC compliant TV receivers • Personal computers with digital television capabilities • Set top boxes 2 PINNING 3 GENERAL DESCRIPTION The TDA8960 is an ATSC compliant demodulator and forward error correction decoder for reception of 8-VSB modulated signals for terrestrial and cable applications: Most of the loop components needed to recover the data from the received symbols are internal. The only required external loop components are a low-speed serial D/A converter and VCXO for the symbol timing recovery and an OPAMP integrator for the AGC. Loop parameters of the clock and carrier recovery can be controlled by I 2 C. A tuner converts the incoming RF frequency to a fixed IF frequency centred at 44 MHz. The output of the tuner is filtered, followed by a down conversion in an IF block to a low IF centred at 1/2 the VSB symbol rate or approximately 5.38 MHz. The low IF signal is connected to the A/D converter. The A/D converter is located within what is typically a fine AGC loop that includes a variable gain stage at the output of the IF block. However, it is also possible to apply the VSB IC AGC control output directly to the tuner. The detector for the VSB IC AGC output is located just after the A/D and determines the peak level of the incoming signals. After gain control, the low IF signal is sampled at a nominal rate of twice the VSB symbol fre- quency, or approximately 21.5 MHz. The carrier recovery is performed completely internally. This function consists of a digital frequency and frequency and phase-locked loop (FPLL). Data shaping is performed with a square root raised cosine (half Nyquist) filter with roll-off factor of 11.5%. Purchase of Philips I 2 C components conveys a license under the Philips' I 2 C patent to use the components in the I 2 C system provided the system conforms to the I 2 C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. handbook, full pagewidth MXXxxx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 TDA8960 ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 ADIN8 ADIN9 VDDD5 VSSD5 SCL SDA A0 A1 TDI TMS TCK RST_AN TRST TDO DATA6 DATA7 VDDD6 VSSD6 VDDD1 VSSD1 ERROR SOP DATAVALID DATACLK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 VDDD7 VSSD7 VDDD2 VSSD2 VDDD3 VSSD3 NC NC NC NC NC NC NC CLK VDDD4 VSSD4 VDDD8 VSSD8 NC TR_SDO TR_STB TR_CS TR_LD LOCK_INDIC EQLOCK_INDIC AGCOUT Fig.1 Pin configuration. 7001002
description
book
Transcript of book
Philips Semiconductors Preliminary specification
ATSC 8-VSB Demodulator and Decoder TDA8960
1 FEATURES
General features
• One chip ATSC compliant 8-VSB demodulator and concatenated Trellis(Viterbi)/Reed-Solomon decoder with deinterleaver and de-randomizer
• 3.3V device
• 64 lead QFP64 package
• Boundary Scan Test
• Output format: 8-bit wide MPEG-2 transport stream
8-VSB demodulator
• On-chip digital circuitry for tuner AGC control
• Square-Root Raised-Cosine filter with 11.5% roll-off factor
• Fully internal carrier recovery loop with programmable loop filter
• Mostly internal clock recovery and AGC loops with programmable loopfilters
• External indication of demodulator lock
Adaptive Equalizer
• Feed forward including a decision feedback structure (DFE)
• Range of -2.3 µs to +10.5 µs
• Adaptation based on ATSC field sync (trained) and/or 8-VSB data(blind)
• Capability to read and write taps via I2C-bus
Trellis (Viterbi) decoder
• Rate 2/3 (Rate 1/2 Ungerboeck code based)
Reed-Solomon decoder
• Internal convolutional de-interleaving
• External indication of uncorrectable error (Transport Error Indicator bitin MPEG packet header is also set)
• Followed by de-randomizer based on ATSC standard
I2C interface
• I2C-bus interface to initialize and monitor the demodulator and FECdecoder. An operation without I 2C (default) is possible.
Applications
• Digital ATSC compliant TV receivers
• Personal computers with digital television capabilities
• Set top boxes
2 PINNING
3 GENERAL DESCRIPTION
The TDA8960 is an ATSC compliant demodulator and forward errorcorrection decoder for reception of 8-VSB modulated signals for terrestrialand cable applications:
Most of the loop components needed to recover the data from the receivedsymbols are internal. The only required external loop components are alow-speed serial D/A converter and VCXO for the symbol timing recoveryand an OPAMP integrator for the AGC. Loop parameters of the clock andcarrier recovery can be controlled by I2C.
A tuner converts the incoming RF frequency to a fixed IF frequencycentred at 44 MHz. The output of the tuner is filtered, followed by a downconversion in an IF block to a low IF centred at 1/2 the VSB symbol rate orapproximately 5.38 MHz. The low IF signal is connected to the A/Dconverter.
The A/D converter is located within what is typically a fine AGC loop thatincludes a variable gain stage at the output of the IF block. However, it isalso possible to apply the VSB IC AGC control output directly to the tuner.The detector for the VSB IC AGC output is located just after the A/D anddetermines the peak level of the incoming signals. After gain control, thelow IF signal is sampled at a nominal rate of twice the VSB symbol fre-quency, or approximately 21.5 MHz.
The carrier recovery is performed completely internally. This functionconsists of a digital frequency and frequency and phase-locked loop(FPLL).
Data shaping is performed with a square root raised cosine (half Nyquist)filter with roll-off factor of 11.5%.
Purchase of Philips I2C components conveys a license under thePhilips' I2C patent to use the components in the I2C system providedthe system conforms to the I2C specification defined by Philips. Thisspecification can be ordered using the code 9398 393 40011.
handbook, full pagewidth
XXX
MXXxxx
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52
TDA8960
ADIN0ADIN1ADIN2ADIN3ADIN4ADIN5ADIN6ADIN7
ADIN8ADIN9
VDDD5VSSD5
SCLSDA
A0
A1TDI
TMSTCK
RS
T_A
N
TR
ST
TD
O
DAT
A6
DAT
A7
VD
DD
6
VS
SD
6
VD
DD
1
VS
SD
1
ER
RO
R
SO
PD
ATA
VA
LID
DAT
AC
LK
DATA0DATA1
DATA2DATA3DATA4
DATA5
VDDD7VSSD7
VDDD2
VSSD2
VDDD3
VSSD3
NCNC
NCNCNC
NCNC
CLK
VD
DD
4
VS
SD
4
VD
DD
8
VS
SD
8
NC
TR
_SD
OT
R_S
TB
TR
_CS
TR
_LD
LOC
K_I
ND
ICE
QLO
CK
_IN
DIC
AG
CO
UT
Fig.1 Pin configuration.
7001002
Philips Semiconductors Preliminary specification
ATSC 8-VSB Demodulator and Decoder TDA8960
Symbol timing recovery is performed mostly within the VSB IC, except thata low cost D/A converter and VCXO are required externally to generatethe nominal 21.52 MHz clock for the A/D converter and VSB IC.
After carrier recovery, half Nyquist filtering, and symbol timing recovery,adaptive equalization is performed based on the use of the ATSC fieldsync (trained equalization) and/or the 8-VSB data itself (blindequalization). The adaptive equalizer uses a decision feedback equalizer(DFE) structure.
After trellis decoding, the stream is de-interleaved with a convolutionalde-interleaver (interleaving depth 52). The memory for de-interleaving ison-chip. The Reed-Solomon decoder is ATSC-compliant, has a length 207
and can correct up to 10 bytes. Next the decoded stream is de-randomizedusing a pseudo-random binary sequence (PRBS).. Finally the data ispassed to a FIFO that prevents the appearance of irregular gaps in theoutput data.
The output of the VSB IC is an ATSC compliant MPEG-2 transport streamtogether with a clock. Furthermore some signal flags are provided toindicate the sync bytes and the valid data bytes. Uncorrected blocks arealso indicated.
The 8-bit wide MPEG-2 stream can be provided to an MPEG-2 transportstream demultiplexer.
Philips Electronics N.V. 1998
Tuner A/D VSB IC
D/AVCXO
AGC
21.52 MHz
MPEG transport stream
I2C-bus
I2C controller
Terrestial/cableUHF/VHF
Fig.2 Front end unit for reception of 8-VSB signals.
TDA9819/9829T TDA8763IF downconverter
DATACLK SOPDATA[7:0] DATAVALIDERROR
TDI
TDO
TCK
TRST
TMS
LOCK_INDIC EQLOCK_INDIC
LOCKDECTECTORS
TR_SDO
TR_STB
TR_CS
TR_LD
AGCOUT ADIN[9:0]
RST_AN
SCLSDA
A0A1
CLK
DE-INTERLEAVER
REED-SOLOMON DECODER
RESET
SERIALDAC
INTERACE
BOUNDARYSCAN TEST
SYNCHRO-NIZATION
DIGITAL FRONTEND:
• FINE AGC
• CARRIER RECOVERY
• HALF-NYQUIST FILTERING
• SYMBOL TIMING RECOVERY
• SYNC RECOVERY AND PILOTREMOVAL
• ADAPTIVE EQUALIZATION
DE-RANDOMIZERI2C
FIFO
VETERBI DECODER
Fig.3 Block diagram of the TDA8960.
