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 BRUSHLESS DC MOTOR DRIVE CONTROLLED BY MICRO CONTROLLER  Project report submitted in partial fulfillment of the requirements For the award of the degree of BACHELOR OF TECHNOLOGY IN ELECTRICAL AND ELECTRONICS ENGINEERING By MD.ABDUL BASID (08241A0256) K.DHANASEKHA R REDDY (08241A026 5) B.RAMAKRISHNA (08241A0289) P.SRAVAN KUMAR (08241A02A3) Under the guidance of E.Venkateswarlu Assistant Professor Department of Electrical and Electronics Engineering GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING & TECHNOLOGY, BACHUPALLY, HYDERABAD-72 2012 

Transcript of BLDC MOTOR DRIVE.pdf

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“BRUSHLESS DC MOTOR DRIVE CONTROLLED

BY MICRO CONTROLLER ” 

Project report submitted in partial fulfillment of the requirementsFor the award of the degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRICAL AND ELECTRONICS ENGINEERING

By

MD.ABDUL BASID (08241A0256)K.DHANASEKHAR REDDY (08241A0265)B.RAMAKRISHNA (08241A0289)P.SRAVAN KUMAR (08241A02A3)

Under the guidance of

E.Venkateswarlu Assistant Professor

Department of Electrical and Electronics Engineering

GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING & TECHNOLOGY,

BACHUPALLY, HYDERABAD-72

2012 

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GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND

TECHNOLOGY

Hyderabad, Andhra Pradesh.

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

C E R T I F I C T E

This is to certify that the project report entitled “BRUSHLESS DC MOTOR DRIVE

CONTROLLED BY MICROCONTROLLER ”   that is being submitted by Mr. MD.

ABDUL BASID, K.DHANASEKHAR REDDY, B.RAMAKRISHNA and P.SRAVAN

KUMAR   in partial fulfillment for the award of the Degree of Bachelor of Technology in

Electrical and Electronics Engineering to the Jawaharlal Nehru Technological University is arecord of bonafide work carried out by him under my guidance and supervision. The results embodied inthis project report have not been submitted to any other University or Institute for the award of anygraduation degree. 

Mr.P.M.Sarma   Mr. E.Venkateswarlu

HOD, EEE Assistant Professor.

GRIET, Hyderabad GRIET, Hyderabad(Internal Guide)

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Acknowledgement

This is to place on record my appreciation and deep gratitude to the persons without whose

support this project would never seen the light of day.

I have immense pleasure in expressing my thanks and deep sense of gratitude to my guide

MR. E.VENKATESWARLU, Assistant Professor Department of Electrical Engineering,

and G.R.I.E.T for his guidance throughout this project.

I also express my sincere thanks to Mr.P.M.Sarma, Head of the Department, and

Mr.M.Chakravarthy Associate Proffessor G.R.I.E.T for extending his help.

I express my gratitude to The Dr.S.N.Saxena, Project Supervisor  G.R.I.E.T for his valuable

recommendations and for accepting this project report.

Finally I express my sincere gratitude to all the members of faculty and my friends who

contributed their valuable advice and helped to complete the project successfully.

MD.ABDUL BASID

K.DHANASEKHAR REDDY

B.RAMAKRISHNA

P.SRAVAN KUMAR

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AbstractA DC Brushless Motor uses a permanent magnet external rotor, three phases of driving coils, oneor more Hall effect devices to sense the position of the rotor, and the associated drive electronics.The coils are activated, one phase after the other, by the drive electronics as cued by the signalsfrom the Hall effect sensors, they act as three-phase synchronous motors containing their

own variable frequency drive electronics.

The following are properties of BLDC Motor

  Electronic commutation based on Hall position sensors  Less required maintenance due to absence of brushes  Speed/Torque- flat, enables operation at all speeds with rated load  High efficiency, no voltage drop across brushes  High output power/frame size.

Reduced size due to superior thermal characteristics. Because BLDC has the windings onthe stator, which is connected to the case, the heat disipation is better

  Higher speed range - no mechanical limitation imposed by brushes/commutator  Low electric noise generation

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Abbreviations

1.  BLDC: Brushless Direct Current2.  PMSM: Permanent Magnet Synchronous Motor3.  ASD: Adjustable Speed Drive4.  VSI: Voltage Source Inverter5.  CSI: Current Source Inverter6.  UPS: Uninterrupted Power Supply7.  LED: Light Emitting Diode8.  VSM: Virtual State Machine

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CONTENTS

S.NO TITLE  Page No. 

a) Acknowledgement  vi

b) Abstract vi

c) Abbreviations vi

d) List of Figures v

e) List of Tables vi

1. INTRODUCTION

1.1  BLDC MOTORS

1.2 COMPARISION OF BLDC AND PMSM1.3 BLDC MOTOR CONTROL

1

2

3

2. ELECTRIC MOTOR

2.1 DC MOTOR

2.2 AC MOTOR

2.3 MOTOR SELECTION 

5

5

6

6

3. HALL SENSORS

3.1 HALL EFFECT

3.2 BLOCK DIAGRAM AND WORKING3.3 HALL EFFECT SENSOR INTERFACE

3.4 HALL PROBE

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10

1011

11

4. MICROCONTOLLER

4.1 HISTORY

4.1.1 Volumes

4.2 IMPORTANT FEATURES AND APPLICATIONS

4.3 MEMORY ARCHITECHTURE

4.4 PROGRAMMING

4.5 INSTRUCTION SET

4.6 RELATED PROCESSORS4.7 USE AS INTELLECTUAL PROPERTY

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5. INVERTER

5.1 INTRODUCTION

5.2 THREE PHASE INVERTERS

5.3POWER MOSFETS

5.3.1 MOSFET STRUCTURE

5.3.2 ON-STATE RESISTANCE

5.3.3 MOSFET OPERATION

5.4MOSFET DRIVER

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6. SIMULATION

6.1 SOFTWARE USED

6.2 KEIL µVISION

6.2.1 Features

6.3 PROGRAM FOR MICROCONTROLLER

6.4 PROTEUS

6.4.1 INTRODUCTION

6.4.2 SCHEMATIC ENTRY

6.4.3 CIRCUIT SIMULATION

6.4.4ADVANTAGES OF PROTEUS

6.5 PSIM

6.6 KEY FEATURES OF PSIM

6.6.1 EASY TO USE

6.6.2Fast Simulation

6.6.3 Flexible Control Representation

6.6.4 COSIMULATION WITH MATLAB/SIMULINK

6.6.5 FREQUENCY RESPONSE ANALYSIS

6.7 SIMULATION CIRCUIT

6.7.1 CIRCUIT DIAGRAM

6.7.2 OUTPUT WAVEFORMS

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7. HARDWARE IMPLEMENTATION

7.1 CIRCUIT SPECIFICATION

7.2 CIRCUIT DESCRIPTION

7.2.1 STARTING POWER SUPPLY

7.2.2WORKING OF HALL SENSORS

7.2.3 MICROCONTOLLER CIRCUIT

7.2.4 BLDC MOTOR DEMONSTRATION

7.2.5 MOSFET DRIVER AND INVERTER

7.2.6 TOTAL CIRCUIT

7.3 HARDWARE OUTPUT WAVEFORMS

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8. CONCLUSION AND SCOPE OF FUTURE

8.1 FUTURE SCOPE

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9. Appendix-A

Appendix-B

Appendix-C

Appendix-D

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LIST OF FIGURES1. Figure.1.1 A three-phase synchronous motor with a one permanent magnet pair pole rotor

2. Figure 1.2 Electrical Waveforms in the Two Phase ON Operation and Torque Ripple

3. Figure.1.3 Torque Ripple in a Sinusoidal Motor Controlled as a BLDC

4. Figure.3.1 Hall sensor

5. Figure.3.2 Block diagram of hall sensor

6. Figure.4.1 8051 Microcontroller

7. Figure 4.2 Block diagram of Microcontroller

8. Figure 4.3: Intel 8031 processors

9. Figure 5.1 Basic inverter circuit

10. Figure 5.2: Three Phase VSI Topology

11. Figure5.3: Waveforms of Three Phase Inverter with 120 degrees of operation

12. Figure5.4 Device symbols:(a)n-channel enhancement mode;(b)p-channel enhancement mode

(c)n-channel depletion mode;(d) p-channel depletion mode

13. Figure 5.5 Mosfet characteristics

14. Figure 5.6: vertical cross sectional view of Power Mosfet

15. Figure 6.1: simulation circuit of microcontroller.

16. Figure 6.2: Three phase Inverter with 120 degrees of operation

17. Figure 6.3 output waveforms

18. Figure 7.1 BLDC demonstration

19. Figure 7.2: Mosfet driver and inverter

20. Figure 7.3 : Total hardware

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LIST OF TABLES1. Table-1.1 Comparison of BLDC and PMSM motors2.Table-2.1:Advantages and Disadvantages of different types of motor3. Table-2.2: Characteristic between a DC, BLDC and an Induction motor  

4. Table -5.1 Valid Switch states for a three phase VSI

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1. INTRODUCTION

The economic constraints and new standards legislated by governments place increasingly stringentrequirements on electrical systems. New generations of equipment must have higher performance

 parameters such as better efficiency and reduced electromagnetic interference. System flexibility must be high to facilitate market modifications and to reduce development time. All these improvementsmust be achieved while, at the same time, decreasing system cost.

Brushless motor technology makes it possible to achieve these specifications. Such motors combinehigh reliability with high efficiency, and for a lower cost in comparison with brush motors. This paperdescribes the use of a Brushless DC Motor (BLDC). Although the brushless characteristic can be applyto several kinds of motors –  AC synchronous motors, stepper motors, switched reluctance motors, ACinduction motors - the BLDC motor is conventionally defined as a permanent magnet synchronousmotor with a trapezoidal Back EMF waveform shape. Permanent magnet synchronous machines withtrapezoidal Back-EMF and (120 electrical degrees wide) rectangular stator currents are widely used as

they offer the following advantages first, assuming the motor has pure trapezoidal Back EMF and thatthe stator phases commutation process is accurate, the mechanical torque developed by the motor isconstant; secondly, the Brushless DC drives show a very high mechanical power density

1.1 BLDC MOTORS:

The BLDC motor is an AC synchronous motor with permanent magnets on the rotor (moving part) andwindings on the stator (fix part). Permanent magnets create the rotor flux and the energizedstator windings create electromagnet poles. The rotor (equivalent to a bar magnet) is attracted by theenergized stator phase. By using the appropriate sequence to supply the stator phases, a rotating field

on the stator is created and maintained. This action of the rotor - chasing after the electromagnet poleson the stator - is the fundamental action used in synchronous permanent magnet motors. The lead between the rotor and the rotating field must be controlled to produce torque and this synchronizationimplies knowledge of the rotor position.

Fig.1.1 A three-phase synchronous motor with a one permanent magnet pair pole rotor

1

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On the stator side, three phase motors are the most common. These offer a good compromise between precise control and the number of power electronic devices required to control the stator currents. Forthe rotor, a greater number of poles usually create a greater torque for the same level of current. On theother hand, by adding more magnets, a point is reached where, because of the space needed

 between magnets, the torque no longer increases. The manufacturing cost also increases with the

number of poles. As a consequence, the number of poles is a compromise between cost, torque andvolume.

Permanent magnet synchronous motors can be classified in many ways, one of these that is of particular interest to us is that depending on back-emf profiles: Brushless Direct Current Motor(BLDC) and Permanent Magnet Synchronous Motor (PMSM). This terminology defines the shape ofthe back-emf of the synchronous motor. Both BLDC and PMSM motors have permanent magnets onthe rotor but differ in the flux distributions and back-emf profiles. To get the best performance out ofthe synchronous motor, it is important to identify the type of motor in order to apply the mostappropriate type of control as described in the next chapters.

1.2 COMPARISION OF BLDC AND PMSM:

Table 1.1 Comparison of BLDC and PMSM motors

BLDC  PMSM 

Synchronous machine Synchronous machine

Fed with direct currents Fed with sinusoidal currents

Trapezoidal Bemf Sinusoidal Bemf

Stator Flux position commutation each 60 Continuous stator flux position variation

Only two phases ON at the same time Possible to have three phases ON at the same

Torque ripple at commutations No torque ripple at commutations

Low order current harmonics in the audible Less harmonics due to sinusoidal excitation

Higher core losses due to harmonic content Lower core loss

Less switching losses Higher switching losses at the same switching

Control algorithms are relatively simple Control algorithms are mathematically intensive

motor types are synchronous machines. The only difference between them is the shape of theinduced voltage, resulting from two different manners of wiring the stator coils. The back-emf istrapezoidal in the BLDC motor case, and sinusoidal in the PMSM motor case.

machines could be driven with sinusoidal currents and PMSM with direct currents, but for better performance, PMSM motors should be excited by sinusoidal currents and BLDC machines bydirect currents.

can structure (hardware and software) of a sinusoidal motor required several current sensorsand sinusoidal phase currents were hard to achieve with analog techniques. Therefore many motors(sinusoidal like trapezoidal) were driven with direct current for cost and simplicity reasons ,compromising efficiency and dynamic behavior.

2

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1.3 BLDC MOTOR CONTROL:

The BLDC motor is characterized by a two phase ON operation to control the inverter. In thiscontrol scheme, torque production follows the principle that current should flow in only two

of the three phases at a time and that there should be no torque production in the region of BackEMF zero crossings. The following figure describes the electrical wave forms in the BLDC motor inthe two phases ON operation.

This control structure has several advantages:

Only one current sensor is necessary

The positioning of the current sensor allows the use of low cost sensors as a shunt.

We have seen that the principle of the BLDC motor is, at all times, to energize the phase pair whichcan produce the highest torque. To optimize this effect the Back EMF shape is trapezoidal. Thecombination of a DC current with a trapezoidal Back EMF makes it theoretically possible to produce aconstant torque. In practice, the current cannot be established instantaneously in a motor phase; as aconsequence the torque ripple is present at each 60 degree phase commutation.

Fig 1.2 Electrical Waveforms in the Two Phase ON Operation and Torque Ripple

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If the motor used has a sinusoidal Back EMF shape, this control can be applied but the producedtorque is:

Firstly, not constant but made up from portions of a sine wave. This is due to its being thecombination of a trapezoidal current control strategy and of a sinusoidal Back EMF. Bear in mind that a

sinusoidal Back EMF shape motor controlled with a sine wave strategy (three phase ON) produces aconstanttorque.

Secondly, the torque value produced is weaker.

Fig.1.3 Torque Ripple in a Sinusoidal Motor Controlled as a BLDC

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2. ELECTRIC MOTOR

An electric motor is an electromechanical device that converts electrical energy into mechan-ical

energy. Most electric motors operate through the interaction of  magnetic fields and current-carrying conductorsto generate force. The reverse process, producing electrical energy from mechanical energy, isdone by generators such as an alternator or a dynamo; some electric motors can also be used asgenerators, for example, a traction motor on a vehicle may perform both tasks. Electric motors andgenerators are commonly referred to as electric machines. Electric motors are found in applications as diverse as industrial fans, blowers and pumps, machinetools, household appliances, power tools, and disk drives. They may be powered by direct current, e.g., a

 battery powered portable device or motor vehicle, or by alternating current from a central electricaldistribution grid or  inverter. The smallest motors may be found in electric wristwatches. Medium-sizemotors of highly standardized dimensions and characteristics provide convenient mechanical power forindustrial uses. The very largest electric motors are used for propulsion of ships, pipeline compressors,and water pumps with ratings in the millions of  watts. Electric motors may be classified by the source ofelectric power, by their internal construction, by their application, or by the type of motion they give.The physical principle behind production of mechanical force by the interactions of an electric currentand a magnetic field, Faraday's law of induction, was discovered by Michael Faraday in 1831. Electricmotors of increasing efficiency were constructed from 1821 through the end of the 19th century, butcommercial exploitation of electric motors on a large scale required efficient electrical generators andelectrical distribution networks. The first commercially successful motors were made around 1873.Some devices convert electricity into motion but do not generate usable mechanical power as a primaryobjective, and so are not generally referred to as electric motors. For example, magnetic solenoids and

loudspeakers are usually described as actuators and transducers, respectively, instead of motors. Someelectric motors are used to produce torque or force.

2.1 DC MOTOR:

There are many different types of DC motor commonly used.

The first type is the  Brushed DC electric motor . The brushed DC electric motor generates torquedirectly from DC power supplied to the motor by using internal commutation, stationary magnets or

rotating electrical magnets.There is also a  brushless type k nown as  Brushless DC motor which is a synchronous 

electric motor that are electric motors powered by direct-current (DC) electricity and having electronic

commutation systems, rather than mechanical brushes and commutators.

A Stepper Motor is also a  brushless, electric motor that can divide a full rotation into a large

number of steps. The motor's position can be controlled precisely without any feedback mechanism, as

long as the motor is carefully sized to the application. Signal pulses will drive the motor and the shaft

of the stepper motor moves between discrete positions proportional to the pulses. Steppers are

generally commutated open loop as the driver has no feedback on where the rotor actually is.

Lastly is the Servo motor. The servo motor is driven by a voltage value and the output shaft of

the servo motor is commanded to a particular angular position corresponding to the input voltage.5

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They are commonly used in radio controlled airplanes to control the wing flaps and also in RC radio

cars to control the steering of the car.

2.2 AC MOTOR:

An AC motor is an electric motor driven by an alternating current.

It commonly consists of two basic parts, an outside stationary stator having coils supplied with

alternating current to produce a rotating magnetic field, and an inside rotor attached to the output

shaft that is given a torque by the rotating field.

There are two main types of AC motors, depending on the type of rotor used.

The first type is the induction motor, which runs slightly slower than the supply

frequency. The magnetic field on the rotor of this motor is created by an induced current.

The second type is the synchronous motor, which does not rely on induction and as a result,can rotate exactly at the supply frequency or a sub-multiple of the supply frequency.

The magnetic field on the rotor is either generated by current delivered through slip rings or by a

 permanent magnet. Other types of motors include eddy current motors, and also AC/DC mechanically

commutated machines in which speed is dependent on voltage and winding connection.

2.3 MOTOR SELECTION:

This table will compare the advantages and disadvantages of each type of motor.The Table summarizes the comparison between BLDC motor and other types of motor.

Table 2.1: Advantages and Disadvantages of different types of motor

Type Advantages Disadvantages Typical Application Typical Drive

AC Induction

(Shaded Pole)

Least expensive

Long lifeHigh power

Rotation slips fromFrequency 

Low starting torqueFans

Uni/Poly-phas

AC

AC Induction

(split-phasecapacitor)

High power

High startingtorque

Rotation slips fromfrequency

AppliancePower Tools

Uni/Poly-phasAC

Brushed DC Low initial costSimple speed

control

Maintenance(brushes) Medium lifespan

Treadmill exercisersAutomotive motors

(seats, blowers, windows)

Direct DC orPWM

Brushless DC

Long lifespan

low maintenanceHigh efficiency

High initial cost

Requires a controller

Hard drives

CD/DVD RomElectric vehicles

Direct DC orPWM

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Table-2.2: Characteristic between a DC, BLDC and an Induction motor  

FEATURES BLDC Motor Brushed DC Motor Induction Motor

Commutation Electronic commutation

 based on Hall position

sensors.

Brushed commutation. Driven by EMF

created when an

alternating current 

Maintenance Less required due to

absence of brushes.

Periodic maintenance is

required.

Less required due to

absence of brushes.

Life  Long.  Shorter.  Long. 

Speed/TorqueCharacteristics

Flat –  Enables operation atall speeds with rated load.

Moderately flat –  At higher

speeds, brush friction

increases, thus reducing

 Nonlinear –  Lowertorque at lower speeds.

Output Power/Frame Size High –  Reduced size dueto superior thermal

characteristics. Because

BLDC has the windings on the stator, which is

connected to the case, theheat dissipation is better. 

Moderate/Low –  The heat produced by the armature is

dissipated in the air gap,thus increasing the

temperature in the air gap and limiting specs

on the output power/frame

Moderate –  Since bothstator and rotor have

windings, the output

 power to size is lower

than BLDC. 

Rotor Inertia Low, because it has

 permanent magnets on the

rotor. This improves the

dynamic response. 

Higher rotor inertia which

limits the dynamic

characteristics.

High –  Poor dynamic

characteristics.

Speed Range Higher –  No mechanical

limitation imposed by

 brushes/commutator.

Lower –  Mechanical

limitations by the brushes.

Lower speeds.

Electric Noise 

Generation 

Low.  Arcs in the brushes will

generate noise causing EMI

in the equipment nearby. 

High 

Cost Of Motor Medium –  Since it has permanent magnets,

 building costs are higher. 

Low.  High - As the phycialdesign is moreComplex

Control Complex and expensive. Simple and inexpensive. Complex and

Control 

Requirement 

A controller is alwaysrequired to keep the motor

running. The samecontroller can be used for

variable speed control. 

 No controller is required forfixed speed; a controller isrequired only if variable

speed is desired. 

 No controller isr equire for fixed speed;a controller is requiredonly if variable speed is

desired. 

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Comparing brushed DC motors and induction motors to BLDC motors, BLDC motors havemany advantages over disadvantages. Brushless DC motors require less maintenance andtherefore have a longer life span as compared to brushed DC motors. BLDC motors producemore output power per frame size than brushed DC motors and induction motors. Because therotor is made of permanent magnets, the rotor inertia is less, comparing with other types of

motors. This low rotor inertia improves acceleration and deceleration characteristics,shortening operating cycles. Their linear speed/torque characteristics produce predictable speedregulation. With brushless motors, brush inspection is eliminated, making them ideal for areaswith limited access and applications where servicing is difficult. BLDC motors operate muchmore quietly than brushed DC motors, reducing Electromagnetic interference (EMI). Low-voltage models are ideal for battery operation, portable equipment or medical applications. Italso reduces the risk of electric shock.

Based on the above findings, although a BLDC motor is more expensive and harder to control,

its overall advantage proves to be worthy of implementation. Therefore a BLDC motor is

selected for this project.

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 3. HALL SENSORS

A Hall Effect sensor is a transducer that varies its output voltage in response to a magnetic field. Hall

Effect sensors are used for proximity switching, positioning, speed detection, and current sensingapplications.

In its simplest form, the sensor operates as an analogue transducer, directly returning a voltage. With a

known magnetic field, its distance from the Hall plate can be determined. Using groups of sensors, the

relative position of the magnet can be deduced.

Figure 3.1: Hall sensor

Electricity carried through a conductor will produce a magnetic field that varies with current, and a Hallsensor can be used to measure the current without interrupting the circuit. Typically, the sensor is

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 integrated with a wound core or permanent magnet that surrounds the conductor to be measured.

Frequently, a Hall sensor is combined with circuitry that allows the device to act in a digital (on/off)

mode, and may be called a switch in this configuration. Commonly seen in industrial applications such a

the pictured pneumatic cylinder, they are also used in consumer equipment; for example some computer

 printers use them to detect missing paper and open covers. When high reliability is required, they are

used in keyboards.

Hall sensors are commonly used to time the speed of wheels and shafts, such as for internal combustionengine ignition timing, tachometers and anti-lock braking systems. They are used in brushless DCelectric motors to detect the position of the permanent magnet. In the pictured wheel with two equallyspaced magnets, the voltage from the sensor will peak twice for each revolution. This arrangement iscommonly used to regulate the speed of disc drives

3.1 HALL EFFECT:

The Hall effect is the production of a voltage difference (the Hall voltage) across an electrical conductor,

transverse to an electric current in the conductor and a magnetic field perpendicular to the current. It was

discovered by Edwin Hall in 1879.

The Hall coefficient is defined as the ratio of the induced electric field to the product of the current

density and the applied magnetic field. It is a characteristic of the material from which the conductor is

made, since its value depends on the type, number, and properties of the charge carriers that constitute

the current.

3.2 BLOCK DIAGRAM AND WORKING:

Figure 3.2: Block diagram of hall sensor

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 From the figure 3.2 notice that sensor are three-wire sensor. This means that two wires, the + V, and the

ground provide dc voltage for the power supply portion of the sensor.

Terminal 0 and ground are used as the output terminals for the sensor. Since this is a three-wire sensor,

the ground terminal is part of the power supply and part of the output circuit. The power supply uses a

voltage regulator to provide the initial current for the Hall-effect element and voltage for the op amp. Th

small sensor terminals are connected to the op amp input terminals.

When a magnetic field is sensed, a small voltage is sent to the op amp and the output of the op amp is

sent to a Schmitt trigger and then to the base of an NPN transistor. When the base of the transistor is

 biased, it will go into saturation and current will flow through its emitter-collector circuit to provide a

digital (on/off) output signal. In the current-sinking circuit, notice that the transistor provides a path to

ground when the transistor is biased to saturation.

3.3 HALL EFFECT SENSOR INTERFACE:

Hall effect sensor may require analog circuitry to be interfaced to microprocessors. These interfaces may

include input diagnostics, fault protection for transient conditions, and short/open circuit detection. It

may also provide and monitor the current to the Hall Effect sensor itself. There are precision IC products

available to handle these features.

3.4 HALL PROBE:

A Hall probe contains an indium compound semiconductor crystal such as indium antimonite, mountedon an aluminum backing plate, and encapsulated in the probe head. The plane of the crystal is

 perpendicular to the probe handle. Connecting leads from the crystal are brought down through the

handle to the circuit box.

When the Hall Probe is held so that the magnetic field lines are passing at right angles through the sensor

of the probe, the meter gives a reading of the value of magnetic flux density (B). A current is passed

through the crystal which, when placed in a magnetic field has a ―Hall effect‖ voltage developed across

it. The Hall Effect is seen when a conductor is passed through a uniform magnetic field. The natural

electron drift of the charge carriers causes the magnetic field to apply a Lorentz force (the force exertedon a charged particle in an electromagnetic field) to these charge carriers. The result is what is seen as a

charge separation, with a buildup of either positive or negative charges on the bottom or on the top of the

 plate. The crystal measures 5 mm square. The probe handle, being made of a non-ferrous material, has n

disturbing effect on the field.

A Hall Probe is enough to measure the Earth's magnetic field. It must be held so that the Earth's field

lines are passing directly through it. It is then rotated quickly so the field lines pass through the sensor in

the opposite direction. The change in the flux density reading is double the Earth's magnetic flux density

A hall probe must first be calibrated against a known value of magnetic field strength. For a solenoid thehall probe is placed in the center .

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 4. MICROCONTOLLER  

The Intel MCS-51(Commonly referred to as 8051) is Harvard architecture, single chip microcontroller

Series which was developed by Intel in 1980 for use in embedded systems. Intel‘s original popular in the1980s and early 1990s.While Intel no longer manufactures the MCS-51, binary compatible derivativesRemain popular today. In addition to these physical devices, several companies also offer MCS -51derivatives as IP cores for use in FPGAs or ASICs designs.

Figure 4.1 8051 Microcontroller

Intel's original MCS-51 family was developed using NMOS technology, but later versions, identified ba letter C in their name (e.g., 80C51) used CMOS technology and consumed less power than thei

 NMOS predecessors. This made them more suitable for battery-powered devices.

4.1 HISTORY:

The first single-chip microprocessor was the 4-bit Intel 4004 released in 1971, with the Intel 8008 andother more capable microprocessors becoming available over the next several years. However, both

 processors required external chips to implement a working system, raising total system cost, and makingit impossible to economically computerize appliances.

The Smithsonian Institution says TI engineers Gary Boone and Michael Cochran succeeded in creating

the first microcontroller in 1971. The result of their work was the TMS 1000, which went commercial in

1974. It combined read-only memory, read/write memory, processor and clock on one chip and was

targeted at embedded systems.

Partly in response to the existence of the single-chip TMS 1000, Intel developed a computer system on a

chip optimized for control applications, the Intel 8048, with commercial parts first shipping in 1977. It

combined RAM and ROM on the same chip. This chip would find its way into over one billion PC

keyboards, and other numerous applications. At that time Intel's President, Luke J. Valenter, stated that

the microcontroller was one of the most successful in the company's history, and expanded the division's

 budget over 25%.

Most microcontrollers at this time had two variants. One had an erasable EPROM program memory,

which was significantly more expensive than the PROM variant which was only programmable once.Erasing the EPROM required exposure to ultraviolet light through a transparent quartz lid. One-time

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  parts could be made in lower-cost opaque plastic packages.

In 1993, the introduction of EEPROM memory allowed microcontrollers (beginning with the

Microchip PIC16x84) to be electrically erased quickly without an expensive package as required

for EPROM, allowing both rapid prototyping, and In System Programming.The same year, Atmel

introduced the first microcontroller using Flash memory. Other companies rapidly followed suit, wi-

th both memory types.

Cost has plummeted over time, with the cheapest 8-bit microcontrollers being available for under

$0.25 in quantity (thousands) in 2009, and some 32-bit microcontrollers around $1 for similar qua-

ntities.

 Nowadays microcontrollers are cheap and readily available for hobbyists, with large online communities

around certain processors.

In the future, MRAM could potentially be used in microcontrollers as it has infinite endurance and its

incremental semiconductor wafer process cost is relatively low.

4.1.1 Volumes:

About 55% of all CPUs sold in the world are 8-bit microcontrollers and microprocessors. According to

Semico, over four billion 8-bit microcontrollers were sold in 2006.

A typical home in a developed country is likely to have only four general-purpose microprocess-

ors but around three dozen microcontrollers. A typical mid-range automobile has as many as 30

Or more microcontrollers. They can also be found in many electrical devices such as washing

Machines, microwave ovens, and telephones.

4.2 IMPORTANT FEATURES AND APPLICATIONS:

The 8051 architecture provides many functions (CPU, RAM, ROM, I/O, interrupt logic, timer, etc.) in a

single package

  8-bit ALU, Accumulator and 8-bit Registers; hence it is an 8-bit microcontroller

  8-bit data bus –  It can access 8 bits of data in one operation

  16-bit address bus –  It can access 216 memory locations –  64 KB (65536 locations)

  each of RAM and ROM

  On-chip RAM –  128 bytes (data memory)

  On-chip ROM –  4 Kbyte (program memory)

Four byte bi-directional input/output port

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   UART (serial port)

  Two 16-bit Counter/timers

  Two-level interrupt priority

  Power saving mode (on some derivatives)

One particularly useful feature of the 8051 core was the inclusion of a Boolean processing engine

Which allows bit-level Boolean logic operations to be carried out directly and efficiently on select

internal registers and select RAM locations. This advantageous feature helped cement the 8051's

 popularity in industrial control applications because it reduced code size by as much as 30%. Anot

her valued feature is the including of four bank selectable working register sets which greatly reduce

the amount of time required to complete an interrupt service routine. With a single instruction 8051

can switch register banks as opposed to the time consuming task of transferring the critical registers

to the stack or designated RAM locations. These registers also allowed the 8051 to quickly perform

a context switch which is essential for time sensitive real-time applications

.

The MCS-51 UARTs make it simple to use the chip as a serial communications interface. External pins

can be configured to connect to internal shift registers in a variety of ways, and the internal timers can

also be used, allowing serial communications in a number of modes, both synchronous and

asynchronous. Some modes allow communications with no external components. A mode compatible

with an RS-485 multi-point communications environment is achievable, but the 8051's real strength is

fitting in with existing ad-hoc protocols (e.g., when controlling serial-controlled devices).

Once a UART, and a timer if necessary, have been configured, the programmer needs only to write a

simple interrupt routine to refill the send  shift register whenever the last bit is shifted out by the UART

and/or empty the full receive shift register (copy the data somewhere else). The main program then

 performs serial reads and writes simply by reading and writing 8-bit data to stacks.

MCS-51 based microcontrollers typically include one or two UARTs, two or three timers, 128 or 256

 bytes of internal data RAM (16 bytes of which are bit-addressable), up to 128 bytes of I/O, 512 bytes to64 kB of internal program memory, and sometimes a quantity of extended data RAM (ERAM) located in

the external data space. The original 8051 core ran at 12 clock cycles per machine cycle, with most

instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could

thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second.

Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine

cycle, and have clock frequencies of up to 100 MHz, and are thus capable of an even greater number of

instructions per second. All SILabs, some Dallas and a few Atmel devices have single cycle cores.

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 Features of the modern 8051 include built-in reset timers with brown-out detection, on-chip oscillators,

self-programmable Flash ROM program memory, built-in external RAM, extra internal program storage

 bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, and USB host

interfaces, CAN or LIN bus, PWM generators, analog comparators, A/D and D/A converters, RTCs,

extra counters and timers, in-circuit debugging facilities, more interrupt sources, and extra power

saving modes.

Figure 4.2 Block diagram of microcontroller

4.3 MEMORY ARCHITECHTURE:

The MCS-51 has four distinct types of memory –  internal RAM, special function registers, program

memory, and external data memory.

Internal RAM (IRAM) is located from address 0 to address 0xFF. IRAM from 0x00 to 0x7F can be

accessed directly, and the bytes from 0x20 to 0x2F are also bit-addressable. IRAM from 0x80 to

0xFF must be accessed indirectly, using the @R0 or @R1 syntax, with the address to access loaded

in R0 or R1.

Special function registers (SFR) are located from address 0x80 to 0xFF, and are accessed directly using

the same instructions as for the lower half of IRAM. Some of the SFR's are also bit-addressable.

Program memory (PMEM, though less common in usage than IRAM and XRAM) is located starting

at address 0. It may be on- or off-chip, depending on the particular model of chip being used. Program

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 memory is read-only, though somevariants of the 8051 use on-chip flash memory and provide a method

of re-programming the memory in-system or in-application. Aside from storing code, program memory

can also store tables of constants that can be accessed by MOVC A, @DPTR, using the 16-bit special

function register DPTR.

External data memory (XRAM) also starts at address 0. It can also be on- or off-chip; what makes it

"external" is that it must be accessed using the MOVX (Move external) instruction. Many variants of

the 8051 include the standard 256 bytes of IRAM plus a few KB of XRAM on the chip. If more XRAM

is required by an application, the internal XRAM can be disabled, and all MOVX instructions will fetch

from the external bus.

4.4 PROGRAMMING:

There are various high-level programming language compilers for the 8051. Several C compilers are

available for the 8051, most of which feature extensions that allow the programmer to specify where

each variable should be stored in its six types of memory, and provide access to 8051 specific hardware

features such as the multiple register banks and bit manipulation instructions. There are many

commercial compilers. SDCC is a popular open source C compiler. Other high level languages such

as Forth, BASIC, Pascal/Object Pascal, PL/M and Modula-2 are available for the 8051, but they are less

widely used than C and assembly.

Because IRAM, XRAM, and PMEM(read only) all have an address 0, C compilers for the 8051

architecture provide compiler-specific pragmas or other extensions to indicate where a particular piece of

data should be stored (i.e. constants in PMEM or variables needing fast access in IRAM). Since data

could be in one of three memory spaces, a mechanism is usually provided to allow determining to which

memory a pointer refers, either by constraining the pointer type to include the memory space, or by

storing metadata with the pointer .

4.5 INSTRUCTION SET:

The MCS-51 instruction set offers several addressing modes, including

  direct register, using ACC (the accumulator) and R0-R7

  direct memory, which access the internal RAM or the SFR's, depending on the address

  indirect memory, using R0, R1, or DPTR to hold the memory address. The instruction used may

  vary to access internal RAM, external RAM, or program memory.

  individual bits of a range of IRAM and some of the SFR's

Many of the operations allow any addressing mode for the source or the destination, for example, MOV

020h, 03fh will copy the value in memory location 0x3f in the internal RAM to the memory location

0x20, also in internal RAM.

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 Because the 8051 is an accumulator-based architecture, all arithmetic operations must use the

accumulator, e.g. ADD A, 020h will add the value in memory location 0x20 in the internal RAM to the

accumulator.

One does not need to master these instructions to program the 8051. With the availability of good quality

C compilers, including open source SDCC, virtually all programs can be written with high-level

language.

4.6 RELATED PROCESSORS:

The 8051's predecessor, the 8048, was used in the keyboard of the first IBM PC, where it converted

keypresses into the serial data stream which is sent to the main unit of the computer. The 8048 andderivatives are still used today for basic model keyboards.

The 8031 was a cut down version of the original Intel 8051 that did not contain any internal program

memory (ROM). To use this chip, external ROM had to be added containing the program that the 8031

would fetch and execute. An 8051 chip could be sold as a ROM-less 8031, as the 8051's internal ROM is

disabled by the normal state of the EA pin in an 8031-based design. A vendor might sell an 8051 as an

8031 for any number of reasons, such as faulty code in the 8051's ROM, or simply an oversupply of

8051's and undersupply of 8031's.

Figure 4.3 :Intel 8031 processors

The 8052 was an enhanced version of the original 8051 that featured 256 bytes of internal RAM instead

of 128 bytes, 8 KB of ROM instead of 4 KB, and a third 16-bit timer. The 8032 had these same features

except for the internal ROM program memory. The 8052 and 8032 are largely considered to be obsolete

 because these features and more are included in nearly all modern 8051 based microcontrollers.

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 Intel discontinued its MCS-51 product line in March 2007, however there are plenty of enhanced 8051

 products or silicon intellectual property added regularly from other vendors. Current vendors of MCS-51

compatible processors include more than 20 independent manufacturers including Atmel, Infineon

Technologies (formerly Siemens AG), Maxim Integrated Products (via its Dallas

Semiconductor subsidiary), NXP (formerly Philips Semiconductor), Microchip Technology, Nuvoton

(formerly Winbond), ST Microelectronics, Silicon Laboratories (formerly Cygnal), Texas

Instruments, Ramtron International, Silicon Storage Technology, Cypress Semiconductor and Analog

Devices.

The 80C537 and 80C517 are CMOS versions, designed for the automotive industry. Enhancements

mostly new peripheral features and expanded arithmetic instructions. The 80C517 has fail save

mechanisms, analog signal processing facilities and timer capabilities and 8 KB on-chip program

memory. Other features include:

  256 byte on-chip RAM

  256 directly addressable bits

  External program and data memory expandable up to 64 KB

  8-bit A/D converter with 12 multiplexed inputs

  Arithmetic unit can make division, multiplication, shift and normalize operations

  Eight data pointers instead of one for indirect addressing of program and external data memory

  Extended watchdog facilities

   Nine ports

  Two full-duplex serial interfaces with own baud rate generators

  Four priority level interrupt systems, 14 interrupt vectors

  Three power saving modes

4.7 USE AS INTELLECTUAL PROPERTY:

Today, 8051s are still available as discrete parts, but they are mostly used as silicon intellectual

 property cores. Available in high-level language source code (VHDL or Verilog) or FPGA netlist forms,

these cores are typically integrated within embedded systems, in products ranging from USB flashdrives to washing machines to complex wireless communication systems on a chip. Designers use 8051

silicon IP cores, because of the smaller size, and lower power, compared to 32 bit processors like ARM

M series, MIPS and BA22. Modern 8051 cores are faster than earlier packaged versions. Design

improvements have increased 8051 performance while retaining compatibility with the original MCS 51

instruction set. The original Intel 8051 ran at 12 clock cycles per machine cycle, and most instructions

executed in one or two machine cycles. A typical maximum clock frequency of 12 MHz meant these old

8051s could execute one million single-cycle instructions, or 500,000 two-cycle instructions, per second

In contrast, enhanced 8051 silicon IP cores now run at one clock cycle per machine cycle, and have clock

frequencies of up to 450 MHz. That means an 8051-compatible processor can now execute 450 million

instructions per second

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 5. INVERTER  

5.1 INTRODUCTION:

The main objective of inverters is to produce an ac output waveform from a dc power supply. These are

the types of waveforms required in adjustable speed drives (ASDs), uninterruptible power supplies

(UPS), static var compensators, active filters, flexible ac transmission systems , and voltage

compensators, which are only a few applications. For sinusoidal ac outputs, the magnitude,

frequency, and phase should be controllable. According to the type of ac output waveform, these

topologies can be considered as voltage source inverters (VSIs), where the independently controlled ac

output is a voltage waveform. These structures are the most widely used because they naturally behave a

voltage sources as required by many industrial applications, such as adjustable speed drives (ASDs),

which are the most popular application of inverters; see Fig.5.1

Figure 5.1 Basic inverter circuit

Similarly, these topologies can be found as current source inverters (CSIs), where the independently

controlled ac output is a current waveform. These structures are still widely used in medium-voltage

industrial applications,

where high-quality voltage waveforms are required. Static power converters, specifically inverters, are

constructed from power switches and the ac output waveforms are therefore made up of discrete values.This leads to the generation of waveforms that feature fast transitions rather than smooth ones. For

instance, the ac output voltage produced by the VSI of a standard ASD is a three-levelwaveform (Fig.

14.1c). Although this waveform is not sinusoidal as expected (Fig. 14.1b), its fundamental component

 behaves as such. This behavior should be ensured by a modulating technique that controls the amount of

time and the sequence used to switch the power valves on and off. The modulating techniques most used

are the carrier-based technique (e.g., sinusoidal pulse width modulation, SPWM), the space-vector

technique, and the selective-harmonic-elimination (SHE) technique. The discrete shape of the ac output

waveforms generated by these topologies imposes basic restrictions on the applications of inverters. TheVSI generates an ac output voltage waveform composed of discrete values (highd v =dt ); therefore, the

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 load should be inductive at the harmonic frequencies in order to produce a smooth current waveform. A

capacitive load in the VSIs will generate large current spikes. If this is the case, an inductive filter

 between the VSI ac side and the load should be used. On the other hand, the CSI generates an ac output

current waveform composed of discrete values (highdi = dt ); therefore, the load should be capacitive at

the harmonic frequencies in order to produce a smooth voltage waveform.An inductive load in CSIs will

generate large voltage spikes. If this is the case, a capacitive filter between the CSI ac side and

the load should be used. A three-level voltage waveform is not recommended for

medium voltage ASDs due to the high d v =dt that would apply to the motor terminals. Several negative

side effects of this approach have been reported (bearing and isolation problems). As alternatives to

improve the ac output waveforms in VSIs are the multistage topologies (multilevel and multicell). The

 basic principle is to construct the required ac output waveform from various voltage levels, which

achieves medium-voltage waveforms at reduced d v = dt . Although these topologies are well developedin ASDs, they are also suitable for static var compensators, active filters, and voltage compensators.

Specialized modulating techniques have been developed to switch the higher number of power valves

involved in these topologies. Among others, the carrier-based (SPWM) and SV-based techniques have

 been naturally extended to these applications. In many applications, it is required to take energy from the

ac side of the inverter and send it back into the dc side. For instance, whenever ASDs need to either

 brake or slow down the motor speed, the kinetic energy is sent into the voltage dc link (Fig. 14.1a). This

is known as the regenerative mode operation and, in contrast to the motoring mode, the dc link current

direction is reversed due to the fact that the dc link voltage is fixed. If a capacitor is used to maintain thedc link voltage (as in standard ASDs) the energy must either be dissipated or fed back into the

distribution system, otherwise, the dc link voltage gradually increases. The first approach requires the dc

link capacitor be connected in parallel with a resistor, which must be properly switched only when the

energy flows from the motor load into the dc link. A better alternative is to feed back such energy into

the distribution system. However, this alternative requires a reversible-current topology connected

 between the distribution system and the dc link capacitor. A modern approach to such a requirement is

to use the active front-end rectifier technologies, where the regeneration mode is a natural operating

mode of the system.

5.2 THREE PHASE INVERTERS:

Single-phase VSIs cover low-range power applications and three-phase VSIs cover the medium- to high-

 power applications. The main purpose of these topologies is to provide a three-phase voltage source,

where the amplitude, phase, and frequency of the voltages should always be controllable. Although most

of the applications require sinusoidal voltage waveforms (e.g., ASDs, UPSs, var compensators), arbitrary

voltages are also required in some emerging applications (e g active filters voltage compensators)

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 The standard three-phase VSI topology is shown in Fig.14.13 and the eight valid switch states are given

in Table 14.3.

Figure 5.2:Three Phase VSI Topology

As in single-phase VSIs, the switches of any leg of the inverter ( S1and S4, S3 and S6,or S5 and S2)

cannot be switched on simultaneously because this would result in a short circuit across the dc link

voltage supply. Similarly, in order to avoid undefined states in the VSI, and thus undefined ac output line

voltages, the switches of any leg of the inverter cannot be switched off simultaneously as this will result

in voltages that will depend upon the respective line current polarity. Of the eight valid states, two of

them (7 and 8 in Table 5.1) produce zero ac line voltages. In this case, the ac line currents freewheel

through either the upper or lower components. The remaining states (1 to 6 in Table 5.1) produce

nonzero ac output voltages. In order to generate a given voltage wave-form, the inverter moves from onestate to another. Thus the resulting ac output line voltages consist of discrete values of voltages that are v

i, 0, and ÿ v i. The selection of the states in order to generate the given waveform is done by the

modulating technique that should ensure the use of only the valid states.

Table 5.1 Valid Switch states for a three phase VSI

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Figure5.3: Waveforms of Three Phase Inverter with 120 degrees of operation

5.3POWER MOSFETS:

In three phase or single inverters Thyristor or Mosfet or IGBT‘s are used in general ,but due to

commutation circuit present in Thyristors are not used in inverters . So Mosfets are used because of nocommutation circuit is present so power Mosfets are used for high frequency switching applications likeinverters and choppers.

Unlike the bipolar junction transistor (BJT), the MOSFET device belongs to the unipolar device family because it uses only the majority carriers in conduction . The development of metal- oxidesemiconductor (MOS) technology for microelectronic circuits opened the way for development of th

 power metal oxide semiconductor field effect transistor (MOSFET) device in 1975. Selecting the mosappropriate device for a given application is not an easy task because it requires knowledge about thdevice characteristics, their unique features, innovation, and engineering design experience. Unlike low

 power (signal devices), high-power devices are more complicated in structure, driver design, and theioperational i -v characteristics are difficult to understand. This knowledge is very important for poweelectronics engineers when designing circuits that will make these devices close to ideal. The devicsymbol for a p - and n-channel enhancement and depletion types are shown in Fig. 5.1. Figure 5.2 showthe i -v characteristics for the n -channel enhancement-type MOSFET. It is the fastest power switchingdevice, with switching frequency >MHz, and with voltage power ratings up to 600 V and current ratingas high as 40 A. Regions of operations for MOSFET will be studied.

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Figure 5.4 Device symbols: (a) n-channel enhancement mode; (b) p-channel enhancement mode(c)n-channel depletion mode; (d) p-channel depletion mode

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Figure 5.5 Mosfet characteristics

5.3.1 MOSFET STRUCTURE:

Unlike the lateral channel MOSET devices used in much of the IC technology in which the gate, sourceand drain terminals are located at the same surface of the silicon wafer, power MOSFETs use verticachannel structure in order to increase the device power rating . In the vertical channel structure,

the source and drain are on opposite side of the silicon wafer. Figure 6.7a shows a vertical cross-sectionaview for a power MOSFET. Figure 6.7b shows a more simplified representation. There are severadiscrete types of the vertical structure power MOSFET available commercially today, including VMOSFET,U-MOSFET, D-MOSFET, and S-MOSFET [1, 2]. The p – n junction between the p -base (alsreferred to as body or bulk region) and the n -drift region provide the forward voltage blockingcapabilities. The source metal contact is connected directly to the p -base region through a break inthe n-source region in order to allow for a fixed potential to the p -base region during normal devicoperation. When the gate and source terminal are set to the same potential( VGSˆ 0), no channel i

established in the p -base region, that is, the channel region remains un modulated. The lowerdoping in the n -drift region is needed in order to achieve higher drain voltage blocking capabilities. Fothe drain-source current I D to flow, a conductive path must be established between the n- and n

ÿ-regions through the p -base diffusion region.

5.3.2 ON-STATE RESISTANCE:When the MOSFET is in the on-state (triode region), the channel of the device behaves like a constanresistance R DS… on† that is linearly proportional to the change between v DS and i D as given by the

following relation:

The total conduction (on-state) power loss for a given MOSFET with forward current I

D and on-resistance R DS on is given by

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Figure 5.6: vertical cross sectional view of Power Mosfet

The value of R DS… on†can be significant and varies between tens of milliohms and a few ohms fo

low-voltage and high-voltage MOSFETS, respectively. The on-state resistance is an important data shee parameter, because it determines the forward voltage drop across the device and its total power lossesUnlike the current-controlled bipolar device, which requires base current to allow the current to flow inthe collector, the power MOSFET device is a voltage-controlled unipolar device and requires only small amount of input (gate) current. As a result, it requires less drive power than the BJT. However, it ia nonlatching current like the BJT, that is, a gate source voltage must be maintained. Moreover, as onlymajority carriers contribute to the current flow, MOSFETs surpass all other devices in switching speedwhich switching speeds can exceed a few megahertz. Comparing the BJT and the MOSFET, the BJT hagreater power handling capabilities and smaller switching speed, while the MOSFET device has les

 power handling capabilities and relatively fast switching speed. The MOSFET device has a higher onstate resistor than the bipolar transistor. Another difference is that the BJT parameters are more sensitiveto junction temperature when compared to the MOSFET and, unlike the BJT,MOSFET devices do nosuffer from second breakdown voltages and sharing current in parallel devices is possible

5.3.3 MOSFET OPERATION:

Most MOSFET devices used in power electronics applications are of the n -channel, enhancement typelike that shown in Fig. 6.6a. For the MOSFET to carry drain current, a channel between the drain and thesource must be created. This occurs when the gate-to-source voltage exceeds the device threshold voltagV Th. For v GS > V Th , the device can be either in thetriode region, which is also called ‗‗constan

resistance‘‘ region, or in the saturation region, depending on the value of v DS .Forgiven v GS , wi tsmall v DS( v DS< v GSÿ V Th), the device operates in the triode region (saturation region in the BJT)and forlarger v DS… vDS> v GSÿ V Th), the device enters the saturation region (active region in th

BJT). For v GS < V Th, the device turns off, with drain current almost equal to zero. Under both region

of operation, the gate current is almost zero. This is why the MOSFET is known as a voltage-drivendevice and, therefore, requires simple gate control circuit.The characteristic curves in Fig. 6.6b show tha

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 there are three distinct regions of operation labeled as triode region, saturation region, and cut-off regionWhen used as a switching device, only triode and cut-off regions are used, whereas, when it is used as anamplifier, the MOSFET must operate in the saturation region, which corresponds to the active region inthe BJT. The device operates in the cut-off region (off-state) when V GS< v Th, resulting in no inducedchannel. In order to operate the MOSFET in either the triode or saturation region, a channel must first b

induced. This can be accomplished by applying gate-to-source voltage that exceeds v Th, that is,.

5.4MOSFET DRIVER:

To turn a power MOSFET on, the gate terminal must be set to a voltage at least 10 volts greater than thesource terminal (about 4 volts for logic level MOSFETs). This is comfortably above the V gs(th) parameter

One feature of power MOSFETs is that they have a large stray capacitance between the gate and thother terminals, Ciss. The effect of this is that when the pulse to the gate terminal arrives, it must firscharge this capacitance up before the gate voltage can reach the 10 volts required. The gate terminal theneffectively does take current. Therefore the circuit that drives the gate terminal should be capable osupplying a reasonable current so the stray capacitance can be charged up as quickly as possible. Th

 best way to do this is to use a dedicated MOSFET driver chip.

Some require the MOSFET source terminal to be grounded (for the lower 2 MOSFETs in a full bridge o just a simple switching circuit). Some can drive a MOSFET with the source at a higher voltage. Theshave an on-chip charge pump, which means they can generate the 22 volts required to turn the upperMOSFET in a full bridge on.

Often you will see a low value resistor between the MOSFET driver and the MOSFET gate terminalThis is to dampen down any ringing oscillations caused by the lead inductance and gate capacitancwhich can otherwise exceed the maximum voltage allowed on the gate terminal. It also slows down thrate at which the MOSFET turns on and off. This can be useful if the intrinsic diodes in the MOSFET donot turn on fast enough

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6. SIMULATION 

6.1 SOFTWARE USED:

In the micro controller based equipment, the hardware works only when the relevant software i

written into the ROM area of the micro controller. Whenever the power is switched on to the micro

controller, the CPU runs the specified program and generates the relevant outputs to control the interna

and external peripheral devices to accomplish the required task. 

6.2 KEIL µVISION:

The Keil C51 C Compiler for the 8051 microcontroller is the most popular 8051 C compiler in the world

It provides more features than any other 8051 C compiler available today. 

The C51 Compiler allows to write 8051 microcontroller applications in C that, once compiled, have th

efficiency and speed of assembly language. Language extensions in the C51 Compiler give full access t

all resources of the 8051.

The C51 Compiler translates C source files into relocatable object modules which contain full symbolic

information for debugging with the µVision Debugger or an in-circuit emulator. In addition to the objec

file, the compiler generates a listing file which may optionally include symbol table and cross referenc

information.

The Keil 8051 Development Tools are designed to solve the complex problems facing embedde

software developers.

  When starting a new project, simply select the microcontroller from the Device Database an

the µVision IDE sets all compiler, assembler, linker, and memory options.

   Numerous example programs are included to help get started with the most popula

embedded 8051 devices.

  The Keil µVision Debugger accurately simulates on-chip peripherals (I²C, CAN, UART, SPI

Interrupts, I/O Ports, A/D Converter, D/A Converter, and PWM Modules) of 8051 deviceSimulation helps to understand hardware configurations and avoids time wasted on setu

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  problems. Additionally, with simulation, can be written and test applications before targe

hardware is available.

6.2.1 Features:

   Nine basic data types, including 32-bit IEEE floating-point,

  Flexible variable allocation with bit, data, bdata, idata, xdata, and pdata memory types,

  Interrupt functions may be written in C,

  Full use of the 8051 register banks,

  Complete symbol and type information for source-level debugging,

  Use of AJMP and ACALL instructions,

  Bit-addressable data objects,

  Built-in interface for the RTX51 Real-Time Kernel,

  Support for dual data pointers on Atmel, AMD, Cypress, Dallas Semiconductor, Infineon

Philips, and Triscend microcontrollers,

  Support for the Philips 8xC750, 8xC751, and 8xC752 limited instruction sets,

  Support for the Infineon 80C517 arithmetic unit.

6.3 PROGRAM FOR MICROCONTROLLER:

#include <REGX51.H>

sbit P20=P2^0;

sbit P21=P2^1;

sbit P22=P2^2;

sbit P10=P1^0;

sbit P11=P1^1;

sbit P12=P1^2;

sbit P13=P1^3;

sbit P14=P1^4;

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 sbit P15=P1^5;

sbit P16=P1^6;

void main()

{

P20=P21=P22=1;

P10=1;

P11=0;

P12=0;

P13=1;

P14=0;

P15=0;

while(1)

{

if(P20==0&&P21==0&&P22==0)

{

P10=0;

P11=1;

}

if(P20==0&&P21==0&&P22==1)

{

P13=0;

P15=1;

}

if(P20==0&&P21==1&&P22==0)

{

P11=0;

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 P12=1;

}

if(P20==0&&P21==1&&P22==1)

{

P15=0;

P14=1;

}

if(P20==1&&P21==0&&P22==0)

{

P12=0;

P10=1;

}

if(P20==1&&P21==0&&P22==1)

{

P14=0;

P13=1;

}

}

}

6.4 PROTEUS:

6.4.1 INTRODUCTION:

Proteus for 8051 contains everything you need to develop test and virtually prototype your embedded

System designs based around the popular 8051 series of microcontrollers. The unique nature o

schematic based microcontroller simulation with Proteus facilitates rapid ,flexible and paralle

development of both the system hardware and the system firmware. This design synergy allow

engineers to evolve their projects more quickly empowering them with the flexibility to make hardwar

or firmware changes at will and reducing the time to market.

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 Proteus Virtual System Modeling (VSM) combines mixed mode SPICE circuit simulation, animated

components and microprocessor models to facilitate co-simulation of complete microcontroller base

designs. For the first time ever, it is possible to develop and test such designs before a physical prototyp

is constructed.

This is possible because you can interact with the design using on screen indicators such as LED and

LCD displays and actuators such as switches and buttons. The simulation takes place in real time (or near

enough to it): a 1GMHz Pentium III can simulate a basic 8051 system clocking at over 12MHz. Proteus

VSM also provides extensive debugging facilities including breakpoints, single stepping and variable

display for both assembly code and high level language source..

6.4.2 SCHEMATIC ENTRY:

Proteus VSM uses our proven Schematic Capture software to provide the environment for design entry

and development. ISIS is a long established product and combines ease of use with powerful editin

tools. It is capable of supporting schematic capture for both simulation and PCB design. Designs entered

in to Proteus VSM for testing can be netlisted for PCB layout either with our own PCB Design product

or with third party PCB layout tools. ISIS also provides a very high degree of control over the drawing

appearance, in terms of line widths, fill styles, fonts, etc. These capabilities are used to the full in

 providing the graphics necessary for circuit animation.

6.4.3 CIRCUIT SIMULATION:

Figure 6.1: simulation circuit of microcontroller

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 PROTEUS Software is used for simulating the microcontroller circuit .In this project supply to the stator

winding depending up on rotor position. The rotor position is sensed by Hall sensors. The hall senso

output is given as input to microcontroller. For simulation purpose the hall sensors are replaced by

switches. In BLDC motors three phase inverter with six step pulses are used for stator supply. The gat

 pulses are taken from micocontroller. Depending upon the output of the hall sensor we generate six

 pulses from microcontroller which are observed by placing LEDs as shown in above figure 

6.4.4ADVANTAGES OF PROTEUS:

The Proteus Design Suite is wholly unique in offering the ability to co-simulate both high and low-level

micro-controller code in the context of a mixed-mode SPICE circuit simulation. With this Virtual System

Modeling facility, you can transform your product design cycle, reaping huge rewards in terms of

reduced time to market and lower costs of development.

If one person designs both the hardware and the software then that person benefits as the hardware

design may be changed just as easily as the software design. In larger organizations where the two roles

are separated, the software designers can begin work as soon as the schematic is completed; there is no

need for them to wait until a physical prototype exists.

In short, Proteus improves efficiency, quality and flexibility throughout the design process. 

6.5 PSIM:

PSIM is a simulation software specifically designed for power electronics and motor control. With fastsimulation and friendly user interface, PSIM provides a powerful simulation environment to address yousimulation needs.

PSIM provides an intuitive and easy-to-use graphic user interface for schematic editing. A circuit can beeasily created and edited. Extensive on-line help is available for each component. To handle largesystems, PSIM provides the sub circuit function which allows part of a circuit to be represented by a subcircuit block .

PSIM simulator is the engine of the simulation environment. It uses efficient algorithms to overcome theconvergence problem and long simulation time existing in many other simulation software. The fastsimulation allows repetitive simulation runs and significantly shortens the design cycle.

Simulation results are displayed and evaluated in Simview. Various waveform processing functions, suchas multiple screens and line styles, are provided. Post-processing functions such as addition/subtractionand average/rms value calculation are also provided. 

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 6.6 KEY FEATURES OF PSIM :

6.6.1 EASY TO USE: PSIM is so easy to use that one hardly needs the User Manual to use the software. Even without prior

experience with CAD software, one could start building a circuit and obtaining results in minutes.

6.6.2 Fast Simulation:PSIM is one of the fastest simulators for power electronics simulation. It achieves fastsimulation while retaining excellent simulation accuracy. This makes it particularly efficient insimulating converter systems of any size, and performing multiple-cycle simulation.

6.6.3 Flexible Control Representation: 

PSIM can simulate control circuit in various forms: in analog circuit, s-domain transfer function bloc

diagram, z-domain transfer function block diagram, custom C code, or in Matlab/Simulink. PSIM'control library provides a comprehensive list of components and function blocks, and makes it possible

to build virtually any control scheme quickly and conveniently. 

6.6.4  COSIMULATION WITH MATLAB/SIMULINK:

PSIM can perform co-simulation with Matlab/Simulink. This feature (available with the Sim Couple

Module) allows users to make full use of PSIM and Matlab/Simulink in a complementary way.

6.6.5  FREQUENCY RESPONSE ANALYSIS:

While almost all the simulation software require that a switchmode circuit be represented by an average

model first before performing ac analysis, PSIM can perform ac analysis even if the circuit is in switch

mode. This feature greatly reduces the time required to obtain frequency response. 

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 6.7 SIMULATION CIRCUIT:

6.7.1 CIRCUIT DIAGRAM:

Figure 6.2: Three phase Inverter with 120 degrees of operation

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6.7.2 OUTPUT WAVEFORMS:

Figure 6.3 output waveforms

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 7. HARDWARE IMPLEMENTATION

7.1 CIRCUIT SPECIFICATIONThis section covers a BLDC motor drive controlled by microcontroller with the following specifications

  Input : 24 volts to 3 phase inverter  Power supplies: 5V to microcontroller and Hall sensors

  5V and 15 V to MOSFET Driver

  Output :

 

  Microcontroller:AT89C51

  Hall Sensors :281

  Protection : None

7.2 CIRCUIT DESCRIPTION

7.2.1 Starting Power Supply

A power supply is a device that supplies electrical energy to one or more electric loads.

Every power supply must obtain the energy it supplies to its load, as well as any energy itconsumes while performing that task, from an energy source depending on its design.

The power supply circuit will required to provide +5Vdc, +15Vdc and +24Vdc to the whole

system. The table below explains the voltage supply needed for each component.

Components Voltage Required FunctionMicrocontroller +5V Used to power up the

device

Hall Sensors +5V +15V DC is used for the

control the power supply

Motor Drive +15V and +24V Used to power up the

device

Table 7.1: Power Supply

7.2.2WORKING OF HALL SENSORS:Hall Sensors senses the magnetic field means when North pole of a magnet is nearer to the sensor itgives output is high and when south pole of a magnet is nearer to the sensor it gives output is lowWe connect resistor between input and output terminal as shown in figure and output is shown with thehelp of LED and output value is measured with the help of multimeter

In BLDC motor , supply given to the stator depend upon the rotor position and rotor position is sensed by the hall sensor and the output of the hall sensor output is given as input to the microcontroller.We use three hall sensors and the outputs of the three hall sensors are given as input to microcontroller

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7.2.3 MICROCONTOLLER CIRCUIT:With the help of microcontroller we generate six waveforms for the three phase inverter circuit in 120degrees of mode of operation (output is six stepped waveform). Depends upon the rotor positionmicrocontroller gives two pulses only means when one pulse is going to be OFF, at the same time

another pulse is ON.7.2.4 BLDC MOTOR DEMONSTRATION:We demonstrate the BLDC motor by the following procedure. We can take two circular plate and are

fixed on a stand .we can place permanent magnets on one circular plate and hall sensors on the anotherPlate. In BLDC motor hall sensors are placed in stator and permanent magnets are placed in rotor. In thesame way we can place a hall sensor on circular plate which can be stationary and permanent magnetsare placed in another circular place which can be rotating part and shown in the figure. Hall sensors are

 placed electrically 120 degrees apart means mechanically 60 degrees apart. Magnets are placed 90degrees apart. When rotating circular plate is rotated by hand manually and hall sensors outputs are givento the microcontroller. Depending upon the position of hall sensors we generate the pulses from themicrocontroller.

Figure 7.1 BLDC demonstration

7.2.5 MOSFET DRIVER AND INVERTER:The output pulses from the microcontroller is 5V and it is not sufficient to drive the MOSFET gate so we

need to place the driver circuit for increasing the magnitude and to maintain the constant value in highermagnitude because gate pulse is maintained constant for the full time. when gate pulse is removed mosfeturns off. In 3phase inverter we use 6 mosfets and 3 mosfet drivers are used. One mosfet driver IR2110

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 gives 2 pulses for mosfets so we use three mosfet drivers. The circuit diagram of mosfet driver andinverter shown in figure. The output of the inverter is a six stepped waveform. In BLDC motor thesupply to the stator is the six stepped waveform ( not sinusoidal ).The wave forms can be observed byconnecting three resistors in star and observed the phase voltages with respect to common point of starconnected resistors.

Figure 7.2: MOSFET DRIVER AND INVERTER

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7.2.6 Total Circuit Now joining all the circuits described above form the total circuit of BLDC motor drive controlled bymicrocontroller is shown as below.

Figure 7.3 : Total hardware 

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 7.3 HARDWARE OUTPUT WAVEFORMSThe waveforms obtained from the hardware circuit are shown below,

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8. CONCLUSION AND SCOPE FOR FUTURE WORK

By this project, we have shown the working of BLDC motor which is controlled by microcontroller.By rotating the circular plate with permanent magnets and obtain the output from the hall sensors and

inverter with six stepped waveforms. BLDC motors possess high efficiency.  In BLDC motor PM are onthe rotor & electromagnets are on the stator controlled by software

8.1 FUTURE SCOPE:Brushless motor technology makes it possible to achieve specifications. Such motors combine higreliability with high efficiency, and for a lower cost in comparison with brush motor. In futureapplications of DC motors in appliances like hard disks, wheel chairs and toys are replaced by BLDCmotors due to their low maintenance cost and high efficiency

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REFERENCES

1. Dr. P.S.Bimbhra, Power Electronics, Khanna publications.2. Muhammad H.Rashid, Power Electronics: Circuits, Devices and applications3. Gopal.K.Dubey Fundamentals of Electrical Drives4. Wikepedia.org, Brushless DC electric motor ,

< http://en.wikipedia.org/wiki/Brushless_DC_electric_motor >5. www.microchip.com.

< ww1.microchip.com/downloads/en/AppNotes/00857a.pdf  >

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APPENDIX -A

MH281 LOW SENSITIVITY UNIPOLARHALL EFFECT SWITCH

MH 281 is an unipolar Hall effect sensor IC. It incorporates advanced chopperstabilization technology to provide accurate and stable magnetic switch points. The design,specifications and performance have been optimized for applications of solid state switches.

The output transistor will be switched on (BOP) in the presence of a sufficiently strong South pole magnetic field facing the marked side of the package. Similarly, the output will be switchedoff (BRP) in the presence of a weaker South field and remain off with ―0‖ field. 

The package type is in a Green version was verified by third party organization. Green package is available by customer ‘s option.

Features and Benefits 

  CMOS Hall IC Technology  Solid-State Reliability  Chopper stabilized amplifier stage  Unipolar, output switches with absolute value of South pole from magnet  Operation down to 3.0V  High Sensitivity for direct reed switch replacement applications  100% tested at 125℃ for K Spec.  Custom sensitivity / Temperature selection are available.

Applications 

  Solid state switch  Limit switch  Current limit  Interrupter  Current sensing  Magnet proximity sensor for reed switch replacement

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Characteristics  Values  Unit 

Supply voltage,(V DD ) 27  V 

Out Voltage 27  V 

Reverse Voltage , (V DD ) (V OUT ) -0.3  V Magnetic flux density Unlimited Gauss

Output current , ( I OUT ) 50  mA

Operating Temperature Range, (Ta)―E‖ ver sion -40 to +85 °C

―K‖ version -40 to +125 °C

Storage temperature range, (Ts) -55 to +150 °C

Maximum Junction Temp,(Tj) 150  °C

Thermal Resistance(θ  ja) UA / SO  206 / 543  °C / W 

(θ  jc) UA / SO  148 / 410  °C / W Package Power Dissipation, ( P  D) UA / SO  606 / 230  mW

Absolute Maximum Ratings At (Ta=25°C) 

Note : Do not apply reverse voltage to VDD and VOUT  Pin, It may be caused for Miss function or damaged device. 

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Electrical Specifications 

DC Operating Parameters TA=+25℃, VDD=12V (Unless otherwise specified) 

Parameters  Test Conditions  Min  Type  Max  Units 

Supply Voltage Operating  3.0 24.0 VoltsSupply Current B<Bop  2.5 5.0 mA

Output Saturation Voltage IOUT = 20 mA, B>BOP  500.0 mV

Output Leakage Current IOFF B<BRP, VOUT = 20V  10.0 uA 

Output Rise Time VDD = 12V, R L=1k Ω, CL =20pF  0.04 uS 

Output Fall Time R L=1k Ω; CL=20pF  0.18 uS 

Typical application circuit 

Vcc 

D1 D1:1N4148 or 100Ω 

R2 C1:1000PF

V C2:15PF C1 MH281 O

Out

C2

R2:10K Ω 

MH 281 Magnetic Specifications 

DC Operating Parameters TA=25℃, VSUPPLY=12V

Parameter  Symbol  Test condition  Min  Typ  Max  Unit 

Operate Point Bop 175 250 Gauss

Release Point Brp 95  Gauss

Hysteresis Bhys 45  Gauss

Output Behavior versus Magnetic Pole  DC Operating Parameters Ta = -40 to 125℃, Vdd = 3.0 to 24V (unless otherwise specified)

Parameter   Test condi tion   OUT(UA)   OUT(SO)  

South pole  B>Bop[(250)~(175)]  Low  Open(Pull-up Voltage) 

Null or weak magnetic field  -Brp ~ +Brp  Open(Pull-up Voltage)  Open(Pull-up Voltage) 

North pole  B< -Bop(-250~-175)  Open(Pull-up Voltage)  Low 

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  O u

  t p u

  t   L e a

  k a g e

  C u r r e n

  t  ( u  A  )

  O u

  t p u

  t   S a  t u r a

  t  i o n

  V o  l  t a g e

  ( m  V  )

  S u p p

  l y  C u r r e n

  t   ( m  A  )

  O u

  t p u

  t   S a  t u r a

  t  i o n

  V o

  l  t a g e

  ( m  V  )

  S u p p

  l y  C u r r e n

  t   ( m  A

  )

  P a c  k a g e p o w e r   D

  i s s  i p a  t  i o n

  ( m  W  )

 ypical Temperature(T  A ) Versus Supply Current(I  DD ) Typical Supply Voltage(V  DD ) Versus Supply Current(I  DD ) 

5.0 

4.5 

4.0 

3.5 

3.5

3.0

2.5

3.0 

2.5 

2.0 

1.5 

1.0 

0.5 

0.0 

‐ 40 ‐ 20 0 25 50 75 100125 

Temperature( ℃ )  

2.0

1.5

1.0

0.5

0.0

3 5.0 8 12 15 18.0 2024 

Supply Voltage(V)  

Typical Supply Voltage(V  DD ) Versus Output Voltage(V  DSON  ) Typical Temperature(T  A ) Versus Output Voltage(V  DSON  ) 

200.0 

180.0 

160.0 

140.0 

120.0 

100.0 

80.0 

60.0 

40.0 

20.0 

0.0 

3 5.0 8 12 15 18.0 2024 

Supply Voltage(V)  

200.0 

180.0 

160.0 

140.0 

120.0 

100.0 

80.0

60.0

40.0

20.0

0.0 

‐ 40 ‐ 20 0 25 50 75 100125 

Temperature( ℃ )  

Typical Supply Voltage(V  DD ) Versus Leakage Current(I OFF  ) Power Dissipation versus Temperature(T  A ) 

0.05  800

0.04 

700

600

UA Package 

Rθja= 206℃/w 

0.03  500

0.02 

400

300

0.01 

0.00 

3 5.0 8 12 15 18.0 2024

200 

100 

SO Package 

Rθja 

= 543℃/w 

-40 0 40 80 120 160

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R

D

Package Power Dissipation The power dissipation of the Package is a function of the pad size. This can vary from the

minimum pad size for soldering to a pad size given for maximum power dissipation. Power

dissipation for a surface mount device is determined by TJ(max), the maximum rated junction

temperature of the die, R θJA, the thermal resistance from the device junction to ambient, and the

operating temperature, Ta. Using the values provided on the data sheet for the Package, PD can

 be calculated as follows: 

T - Ta P  

J(max)

D

  j a 

The values for the equation are found in the maximum ratings table on the data sheet.Substituting these values into the equation for an ambient temperature Ta of 25°C, one can

calculate the power dissipation of the device which in this case is 606 milliwatts.  

P (UA)  150C - 25C

 606mW 206C/ W 

The 206°C/W for the UA package assumes the use of the recommended footprint on a glass

epoxy printed circuit board to achieve a power dissipation of 606 milliwatts. There are otheralternatives to achieving higher power dissipation from the Package. Another alternative would

 be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board

material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled

using the same footprint.

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 APPENDIX -B

45

8-Bit

Microcontroller

with 4K Bytes

Flash 

AT89C51 

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 APPENDIX -B

46

P 1 .0  1  4 0  V C C 

P 1 .1  2  3 9  P 0 . 0  (  A D 0 ) 

P 1 .2  3  3 8  P 0 . 1  (  A D 1 ) 

P 1 .3  4  3 7  P 0 . 2  (  A D 2 ) 

P 1 .4  5  3 6  P 0 . 3  (  A D 3 ) 

P 1 .5  6  3 5  P 0 . 4  (  A D 4 ) 

P 1 .6  7  3 4  P 0 . 5  (  A D 5 ) 

P 1 .7  8  3 3  P 0 . 6  (  A D 6 ) 

R S T  9  3 2  P 0 . 7  (  A D 7 ) 

( RX D )  P 3 . 0  1 0  3 1  E A / V P P 

(T X D )  P 3 . 1  1 1  3 0   A L E / P R O G 

( INT 0 )  P 3 . 2  1 2  2 9  P S E N 

( INT 1 )  P 3 . 3  1 3  2 8  P 2 .7  ( A 1 5 ) 

( T 0 )  P 3 . 4  1 4  2 7  P 2 .6  ( A 1 4 ) 

( T 1 )  P 3 . 5  1 5  2 6  P 2 .5  ( A 1 3 ) 

( WR )  P 3 . 6  1 6  2 5  P 2 .4  ( A 1 2 ) 

( RD )  P 3 . 7  1 7  2 4  P 2 .3  ( A 1 1 ) 

3 8 3 7 

   (   W   R   )

   P   3

 .   6

   (   R   D   )

   P   3

 .   7

   X   T   A   L   2

   X   T   A   L   1

   G   N   D

   G   N   D

   (   A   8   )

   P   2

 .   0

   (   A   9   )

   P   2

 .   1

   (   A   1   0   )

   P   2

 .   2

   (   A   1   1   )

   P   2

 .   3

   (   A   1   2   )

   P   2

 .   4

   P   1

 .   4

   P   1

 .   3

   P   1

 .   2

   P   1

 .   1

   P   1

 .   0

   N   C

   V   C   C

   P   0

 .   0

   (   A   D   0   )

   P   0

 .   1

   (   A   D   1   )

   P   0

 .   2

   (   A   D   2   )

   P   0

 .   3

   (   A   D   3   )

   P   1 .   4

   P   1 .   3

   P   1 .   2

   P   1 .   1

   P   1 .   0

   N

   C 

   V   C

   C 

   P   0

 .   0

   (   A   D

   0   )

   P   0

 .   1

   (   A   D

   1   )

   P   0

 .   2

   (   A   D

   2   )

   P   0 .   3

   (   A   D

   3   )

   (   W   R   )

   P   3

 .   6

   (   R   D   )

   P   3

 .   7

   X   T   A   L   2

   X   T   A   L   1

   G

   N   D

 

   N   C

 

   (   A   8   )

   P   2 .   0

   (   A   9   )

   P   2 .   1

   (   A   1   0   )

   P   2 .   2

   (   A   1   1   )

   P   2 .   3

   (   A   1   2   )

   P   2 .   4

 

Pin Configurations 

PDIP

PQFP/TQFP 

I N D E X C O R N ER 

4 4  4 2  4 0  3 6  3 4 X T  A L 2  1 8  2 3  P 2 . 2  (  A 1 0 ) 

P 1 . 5 

P 1 . 6 

P 1 . 7 R ST ( R X D )  P 

3 . 0 

N C ( T X D )  P 3 . 1 

( I NT 0 ) P 3 . 2 (

I NT 1 ) P 3 . 3 

( T 0 )  P 3 . 4 

( T 1 )  P 3 . 5 

4 3  4 1  3 9 

3 4 

1 0 

1 1 

3 5 

3 3  P 0 . 4  (  A D 4 ) 

3 2  P 0 . 5  (  A D 5 ) 

3 1  P 0 . 6  (  A D 6 ) 3 0  P 0 . 7  (  A D 7 ) 

2 9  E A / V P P 

2 8  N C 

2 7   A L E / P R O G 

2 6  P S E N 

2 5  P 2 . 7  ( A 1 5 ) 

2 4  P 2 . 6  ( A 1 4 ) 

2 3  P 2 . 5  ( A 1 3 ) 

X T  A L 1 

G N D 

I N D E X C O R N E R 

1 9  2 2 

2 0  2 1 

PLCC

P 2 . 1  (  A 9 ) 

P 2. 0 ( A 8 ) 

1 3  1 5  1 7  1 9  2 1 6 4 2 4 4 

5 3 1 4 2  4 0 

1 2  1 4  1 6  1 8  2 0  2 2  P1.5 7 P1.6 8

P1.7 9

R S T  1 0 

( R X D )  P 3 . 0  1 1 

4 3  4 1 3 9 

3 6 

3 5 

P 0 . 4  (  A D 4 ) 

P0.5 ( A D5)

P0.6 ( A D6)

P0.7 ( A D7)

E A / V P P 

N C  1 2  3 4  N C 

(T X D) P 3. 1 ( I NT0 ) P 3 . 2 

( INT1 ) P 3. 3 

(T0) P 3 .4 ( T 1 )  P 3 . 5 

1 3 

1 4 

1 5 

1 6 

1 7 1 9  2 1  2 3  2 5 

3 3 

3 2 

3 1 

3 0 

2 7 2 9 

 A L E / P R O G

P S E N 

P2.7 (A15)

P 2 . 6  ( A 1 4 ) 

P 2 . 5  ( A 1 3 ) 1 8  2 0  2 2  2 4  2 6  2 8 

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The AT89C51 provides the following standard features: 4K

bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, afull duplex serial port, on-chip oscillator and clock cir-

cuitry. In addition, the AT89C51 is designed with static logic

for operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM, timer/counters,

serial port and interrupt system to continue functioning. ThePower Down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the next

hardware reset.

Pin Description VCC 

Supply voltage.

GND 

Ground.

Port 0 

Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external pro-

gram and data memory. In this mode P0 has internal pul-lups.

Port 0 also receives the code bytes during Flash program-

ming, and outputs the code bytes during program verifica-

tion. External pullups are required during program verifica-

tion.

Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes duringFlash programming and verification.

Port 2 

Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application it uses strong internal pullups

when emitting 1s. During accesses to external data mem

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits thecontents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3 

Port 3 is an 8-bit bidirectional I/O port with internal pullups

The Port 3 output buffers can sink/source four TTL inputsWhen 1s are written to Port 3 pins they are pulled high by

the internal pullups and can be used as inputs. As inputsPort 3 pins that are externally being pulled low will sourc

current (IIL) because of the pullups.

Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:

Port Pin  Alternate Functions 

P3.0  RXD (serial input port) 

P3.1  TXD (serial output port) 

P3.2  INT0 (external interrupt 0) 

P3.3  INT1 (external interrupt 1) P3.4  T0 (timer 0 external input) 

P3.5  T1 (timer 1 external input) 

P3.6  WR (external data memory write strobe) 

P3.7  RD (external data memory read strobe) 

Port 3 also receives some control signals for Flash programming and verification.

RST 

Reset input. A high on this pin for two machine cycles whilethe oscillator is running resets the device.

ALE/PROG 

 Address Latch Enable output pulse for latching the low byte

of the address during accesses to external memory. Thi

pin is also the program pulse input (PROG) during Flashprogramming.

In normal operation ALE is emitted at a constant rate of 1/6

the oscillator frequency, and may be used for external tim

ing or clocking purposes. Note, however, that one ALEpulse is skipped during each access to external Data Mem

ory.

If desired, ALE operation can be disabled by setting bit 0 o

SFR location 8EH. With the bit set, ALE is active only dur

ing a MOVX or MOVC instruction. Otherwise, the pin iweakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

PSEN 

Program Store Enable is the read strobe to external pro

gram memory.

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49

When the AT89C51 is executing code from external pro-gram memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped duringeach access to external data memory.

EA/VPP 

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be

internally latched on reset.

EA should be strapped to VCC for internal program execu-tions.

This pin also receives the 12-volt programming enable volt-

age (VPP) during Flash programming, for parts that require12-volt VPP. 

XTAL1 

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2 

Output from the inverting oscillator amplifier.

Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as

an on-chip oscillator, as shown in Figure 1. Either a quartz

crystal or ceramic resonator may be used. To drive thedevice from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 2.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-mum voltage high and low time specifications must beobserved.

It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execu

tion, from where it left off, up to two machine cycles beforethe internal reset algorithm takes control. On-chip hardwareinhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility o

an unexpected write to a port pin when Idle is terminated byreset, the instruction following the one that invokes Idle

should not be one that writes to a port pin or to externamemory.

Figure 1. Oscillator Connections

C2 

XTAL2 

C1 

XTAL1 

GND 

Note:  C1, C2 = 30 pF  10 pF for Crystals 40 pF  10 pF for Ceramic Resonators 

Figure 2. External Clock Drive Configuration

Idle Mode In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked bysoftware. The content of the on-chip RAM and all the spe-cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Status of External Pins During Idle and Power Down Modes Mode  Program Memory  ALE  PSEN  PORT0  PORT1  PORT2  PORT3 

Idle  Internal  1  1  Data  Data  Data  Data 

Idle  External  1  1  Float  Data   Address  Data 

Power Down  Internal  0  0  Data  Data  Data  Data 

Power Down  External  0  0  Float  Data  Data  Data 

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50

Power Down Mode In the power down mode the oscillator is stopped, and theinstruction that invokes power down is the last instructionexecuted. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardware reset.

Reset redefines the SFRs but does not change the on-chipRAM. The reset should not be activated before VCC is

restored to its normal operating level and must be heldactive long enough to allow the oscillator to restart and sta-bilize.

Lock Bit Protection Modes 

Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the addtional features listed in the table below:

When lock bit 1 is programmed, the logic level at the EA pinis sampled and latched during reset. If the device is pow

ered up without a reset, the latch initializes to a randomvalue, and holds that value until reset is activated. It is nec

essary that the latched value of EA be in agreement with

the current logic level at that pin in order for the device tofunction properly.

Program Lock Bits  Protection Type 

LB1  LB2  LB3 

1  U  U  U  No program lock features. 

2  P  U  U  MOVC instructions executed from external program memory are disabled from fetching code

bytes from internal memory, EA is sampled and latched on reset, and further programming of the

Flash is disabled. 

3  P  P  U  Same as mode 2, also verify is disabled. 

4  P  P  P  Same as mode 3, also external execution is disabled. 

Programming the Flash The AT89C51 is normally shipped with the on-chip Flash

memory array in the erased state (that is, contents = FFH)

and ready to be programmed. The programming interface

accepts either a high-voltage (12-volt) or a low-voltage(VCC) program enable signal. The low voltage program-

ming mode provides a convenient way to program the

 AT89C51 inside the user ’s system, while the high-voltageprogramming mode is compatible with conventional thirdparty Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or

low-voltage programming mode enabled. The respectivetop-side marking and device signature codes are listed inthe following table.

VPP = 12V  VPP = 5V 

Top-Side Mark   AT89C51

xxxx yyww  AT89C51

xxxx-5

yyww 

Signature  (030H)=1EH

(031H)=51H

(032H)=FFH 

(030H)=1EH

(031H)=51H

(032H)=05H 

The AT89C51 code memory array is programmed byte-by-

byte in either programming mode. To program any non-

blank byte in the on-chip Flash Memory, the entire memorymust be erased using the Chip Erase Mode.

Programming Algorithm: Be fore pr  ogr  amm ing th

 AT89C51, the address, data and control signals should bset up according to the Flash programming mode table anFigures 3 and 4. To program the AT89C51, take the follow

ing steps.

1. Input the desired memory location on the addres

lines.

2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V for the high-voltage programming

mode.

5. Pulse ALE/PROG once to program a byte in the Flasarray or the lock bits. The byte-write cycle is self-timed and

typically takes no more than 1.5 ms. Repeat steps1 through 5, changing the address and data for the

entire array or until the end of the object file is reached. 

Data Polling: The AT89C51 features Data Polling to indi-cate the end of a write cycle. During a write cycle, a

attempted read of the last byte written will result in the com

plement of the written datum on PO.7. Once the write cyclehas been completed, true data are valid on all outputs, andthe next cycle may begin. Data Polling may begin any tim

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can als

be monitored by the RDY/BSY output signal. P3.4 is pulled

low after ALE goes high during programming to indicateBUSY. P3.4 is pulled high again when programming is

done to indicate READY.

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AT89C51 

51

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the address and data lines for verification. The lock bits

cannot be verified directly. Verification of the lock bits is

achieved by observing that their features are enabled.

Chip Erase: The entire Flash array is erased electrically

by using the proper combination of control signals and byholding ALE/PROG low for 10 ms. The code array is written

with all “1”s. The chip erase operation must be executedbefore the code memory can be re-programmed.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 030H,

031H, and 032H, except that P3.6 and P3.7 must be pulledto a logic low. The values returned are as follows.

(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51

(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming

Programming Interface 

Every code byte in the Flash array can be written and theentire array can be erased by using the appropriate combi

nation of control signals. The write operation cycle is self

timed and once initiated, will automatically time itself tocompletion.

 All major programming vendors offer worldwide support fo

the Atmel microcontroller series. Please contact your loca

programming vendor for the appropriate software revision.

Flash Programming Modes 

Mode  RST  PSEN  ALE/PROG  EA/VPP  P2.6  P2.7  P3.6  P3.7 

Write Code Data  H  L  H/12V  L  H  H  H 

Read Code Data  H  L  H  H  L  L  H  H 

Write Lock  Bit - 1  H  L  H/12V  H  H  H  H 

Bit - 2  H  L  H/12V  H  H  L  L 

Bit - 3  H  L  H/12V  H  L  H  L 

Chip Erase  H  L  (1)  H/12V  H  L  L  L 

Read Signature Byte  H  L  H  H  L  L  L  L Note: 1. Chip Erase requires a 10-ms PROG pulse.

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AT89C51 

52

Absolute Maximum Ratings* 

Operating Temperature .................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage............................................. 6.6V

DC Output Current...................................................... 15.0 mA 

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect devicereliability.

DC Characteristics T A = -40°C to 85°C, VCC = 5.0V 20% (unless otherwise noted) 

Symbol  Parameter   Condition  Min  Max  Units 

VIL  Input Low Voltage  (Except EA)  -0.5  0.2 VCC - 0.1  V 

VIL1  Input Low Voltage (EA)  -0.5  0.2 VCC - 0.3  V 

VIH  Input High Voltage  (Except XTAL1, RST)  0.2 VCC + 0.9  VCC + 0.5  V 

VIH1  Input High Voltage  (XTAL1, RST)  0.7 VCC  VCC + 0.5  V VOL  Output Low Voltage(1) (Ports 1,2,3)  IOL = 1.6 Ma  0.45  V 

VOL1  Output Low Voltage(1) 

(Port 0, ALE, PSEN) IOL = 3.2 mA  0.45  V 

VOH  Output High Voltage

(Ports 1,2,3, ALE, PSEN) IOH = -60 A, VCC = 5V 10%  2.4  V 

IOH = -25 A  0.75 VCC  V 

IOH = -10 A  0.9 VCC  V 

VOH1  Output High Voltage

(Port 0 in External Bus Mode) IOH = -800 A, VCC = 5V 10%  2.4  V 

IOH = -300 A  0.75 VCC  V 

IOH = -80 A  0.9 VCC  V 

IIL  Logical 0 Input Current (Ports 1,2,3)  VIN = 0.45V  -50   A ITL  Logical 1 to 0 Transition Current

(Ports 1,2,3) VIN = 2V, VCC = 5V 10%  -650   A 

ILI  Input Leakage Current (Port 0, EA)  0.45 < VIN < VCC  10   A 

RRST  Reset Pulldown Resistor   50  300  K 

CIO  Pin Capacitance  Test Freq. = 1 MHz, T A = 25°C  10  pF 

ICC  Power Supply Current   Active Mode, 12 MHz  20  mA 

Idle Mode, 12 MHz  5  mA 

Power Down Mode(2)  VCC = 6V  100   A 

VCC = 3V  40   A 

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mA

Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater  than the listed test conditions.

2. Minimum VCC for Power Down is 2V.

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AT89C51 

53

AC Characteristics (Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all otheroutputs = 80 pF)

External Program and Data Memory Characteristics 

Symbol  Parameter   12 MHz Oscillator   16 to 24 MHz Oscillator   Units Min  Max  Min  Max 

1/tCLCL  Oscillator Frequency  0  24  MHz 

tLHLL   ALE Pulse Width  127  2tCLCL-40  ns 

t AVLL   Address Valid to ALE Low  43  tCLCL-13  ns 

tLLAX   Address Hold After ALE Low  48  tCLCL-20  ns 

tLLIV   ALE Low to Valid Instruction In  233  4tCLCL-65  ns 

tLLPL   ALE Low to PSEN Low  43  tCLCL-13  ns 

tPLPH  PSEN Pulse Width  205  3tCLCL-20  ns 

tPLIV  PSEN Low to Valid Instruction In  145  3tCLCL-45  ns tPXIX  Input Instruction Hold After PSEN  0  0  ns 

tPXIZ  Input Instruction Float After PSEN  59  tCLCL-10  ns 

tPXAV  PSEN to Address Valid  75  tCLCL-8  ns 

t AVIV   Address to Valid Instruction In  312  5tCLCL-55  ns 

tPLAZ  PSEN Low to Address Float  10  10  ns 

tRLRH  RD Pulse Width  400  6tCLCL-100  ns 

tWLWH  WR Pulse Width  400  6tCLCL-100  ns 

tRLDV  RD Low to Valid Data In  252  5tCLCL-90  ns 

tRHDX  Data Hold After RD  0  0  ns tRHDZ  Data Float After RD  97  2tCLCL-28  ns 

tLLDV   ALE Low to Valid Data In  517  8tCLCL-150  ns 

t AVDV   Address to Valid Data In  585  9tCLCL-165  ns 

tLLWL   ALE Low to RD or WR Low  200  300  3tCLCL-50  3tCLCL+50  ns 

t AVWL   Address to RD or WR Low  203  4tCLCL-75  ns 

tQVWX  Data Valid to WR Transition  23  tCLCL-20  ns 

tQVWH  Data Valid to WR High  433  7tCLCL-120  ns 

tWHQX  Data Hold After WR  33  tCLCL-20  ns 

tRLAZ  RD Low to Address Float  0  0  ns tWHLH  RD or WR High to ALE High  43  123  tCLCL-20  tCLCL+25  ns 

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AT89C51 

54

External Program Memory Read Cycle 

 ALE PSEN

tLHLL

t AVLL

t

 

tLLAX

LLPL

tPLAZ

tLLIV

tPLIV

tPXIZ

tPXIX 

tPLPH

tPXAV

PORT 0  A0 - A7

t AVIV 

INSTR IN A0 - A7

PORT 2  A8 - A15   A8 - A15

External Data Memory Read Cycle 

 ALE 

tLHLL 

tWHLH 

PSEN 

RD 

t AVLL 

tLLDV 

tLLWL 

tLLAX 

tRLRH 

tRLDV tRHDZ 

RLAZ

tRHDX 

PORT 0   A0 - A7 FROM RI OR DPL 

t AVWL 

t AVDV 

DATA IN  A0 - A7 FROM PCL  INSTR IN 

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH  A8 - A15 FROM PCH 

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AT89C51 

55

External Data Memory Write Cycle 

 ALE PSEN 

WR 

tLHLL 

t AVLL 

tLLWL 

tLLAX 

tQVWX 

tWLWH 

tQVWH 

tWHLH 

tWHQX 

PORT 0   A0 - A7 FROM RI OR DPL 

t AVWL 

DATA OUT  A0 - A7 FROM PCL  INSTR IN 

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH   A8 - A15 FROM PCH 

External Clock Drive Waveforms 

VCC

- 0.5V

tCHCX

0.7 VCC 

tCLCH

tCHCX

tCHCL

0.45V

0.2 VCC - 0.1V

tCLCX

tCLCL 

External Clock Drive 

Symbol  Parameter   Min  Max  Units 

1/tCLCL  Oscillator Frequency  0  24  MHz 

tCLCL  Clock Period  41.6  ns 

Tchcx  High Time  15  ns 

tCLCX  Low Time  15  ns 

Tclch  Rise Time  20  ns Tchcl  Fall Time  20  ns 

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56

APPENDIX-C

IR2110 

HIGH AND LOW SIDE DRIVER  ProductSummary 

 Floating channel designed for bootstrap operation Fully operational to +500V or

+600V Tolerant to negative

transient voltage dV/dt

immune  Gate drive supply range from 10 to 20V Undervoltage lockout for both channels  3.3V logic compatible Separate logic supply range from

3.3V to 20V Logic and power ground

±5V of fset  CMOS Schmitt-triggered inputs with pull-down  Cycle by cycle edge-triggeredshutdown logic  Matched propagation delay for bothchannels  Outputs in phase with inputs 

VOFFSET (IR2110) 500V max.

(IR2113) 600V max. 

IO+/- 2A / 2A VOUT

10 - 20V ton/of f  (typ.) 120 &

94 ns 

Delay Matching (IR2110) 10 ns max.(IR2113) 20ns max. 

Packages

 

Description 

The IR2110/IR2113 are high voltage, high speed

 power MOSFET and IGBT drivers with independent

high and low side referenced output channels. .

Logic inputs are compatible with standard CMOS or

LSTTL

output,down to

3.3V

logic. The

output

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 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF 

57

driver cross-conduction. Propagation delays are matched to simplify use in high

frequency applications. The floating channel can be used to drive an  N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600

volts.

Absolute Maximum Ratings 

Absolute maximum ratings indicate sustained limits beyond which damage to the

device may occur. All voltage  param- eters are absolute voltages referenced to

COM. The thermal resistance and power dissipation ratings are measured under

 board mounted and still air conditions. Additional information is shown in Figures28 through 35. 

Symbol Definition  Min.  Max.  Units VB  High side floating supply voltage  (IR2110)  -0.3  525 

(IR2113)  -0.3  625 VS  High side floating supply offset voltage  VB - 25  VB + 0.3 

VHO  High side floating output voltage  VS - 0.3  VB + 0.3 VCC  Low side fixed supply voltage  -0.3  25 

VLO  Low side output voltage  -0.3  VCC + 0.3 VDD  Logic supply voltage  -0.3  VSS + 25 VSS

 Logic supply offset voltage  VCC - 25  VCC + 0.3 

VIN  Logic input voltage (HIN, LIN & SD)  VSS - 0.3  VDD + 0.3 dVs/dt  Allowable offset supply voltage transient (figure 2)   —   50  V/ns 

PD  Package power dissipation @ TA  +25°C  (14 lead DIP)   —   1.6 W 

(16 lead SOIC)   —   1.25 

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 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF 

58

R THJA  Thermal resistance,  junction to ambient  (14 lead DIP)   —   75 °C/W 

(16 lead SOIC)   —   100 TJ  Junction temperature   —   150 

°C TS  Storage temperature  -55  150 TL  Lead temperature (soldering, 10 seconds)   —   300 

Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operationthe device should be used within the recommended conditions. The VS and VSSoffset ratings are tested with all supplies biased at 15V dif f erential. Typical ratingsat other bias conditions are shown in figures 36 and 37. 

Symbol  Definition  Min.  Max.  Units VB  High side floating supply absolute voltage  VS + 10  VS + 20 

VS  High side floating supply offset voltage  (IR2110)   Note 1  500 

(IR2113)   Note 1  600 VHO  High side floating output voltage  VS  VB VCC  Low side fixed supply voltage  10  20 

VLO  Low side output voltage  0  VCC VDD  Logic supply voltage  VSS + 3  VSS + 20 

VSS  Logic supply offset voltage  -5 (Note 2)  5 VIN  Logic input voltage (HIN, LIN & SD)  VSS  VDD TA  Ambient tem erature  -40  125  °C 

 Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to-VBS. (Please refer to the Design Ti p DT97-3 for moredetails).  Note 2: When VDD < 5V, the minimum VSSoffset is limited to -VDD. 

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 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF 

59

Dynamic Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, CL = 1000 pF, TA = 25°C and VSS = COM unless otherwise specified. The dynamic

electrical characteristics are measured using the test circuit shown in Figure 3. 

Symbol  Definition  Figure  Min.  Typ.  Max.  Units  Test Conditions ton  Turn-on  propagation delay  7   —   120  150 

VS = 0V toff   Turn-of f   propagation delay  8   —   94  125  VS = 500V/600V tsd  Shutdown propagation delay  9   —   110  140  VS = 500V/600V tr   Turn-on rise time  10   —   25  35 tf   Turn-of f  fall time  11   —   17  25 

MT  Delay matching, HS & LS 

turn-on/of f  (IR2110)   —    —    —   10 (IR2113)   —    —    —   20 

Static Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, TA = 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters

are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are

referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol  Definition  Figure  Min.  Typ. Max.  Units  Test Conditions VIH  Logic ―1‖ input voltage  12  9.5   —    —  

V VIL  Logic ―0‖ input voltage  13   —    —   6.0 

VOH  High level output voltage, VBIAS - VO  14   —    —   1.2  IO = 0A VOL  Low level output voltage, VO  15   —    —   0.1  IO = 0A 

ILK   Offset supply leakage current  16   —    —   50  VB=VS = 500V/600V 

µA 

IQBS  Quiescent VBS supply current  17   —   125  230  VIN = 0V or VDD IQCC  Quiescent VCC supply current  18   —   180  340  VIN = 0V or VDD IQDD  Quiescent VDD supply current  19   —   15  30  VIN = 0V or VDD IIN+  Logic ―1‖ input bias current  20   —   20  40  VIN = VDD 

IIN-  Logic ―0‖ input bias current  21   —    —   1.0  VIN = 0V VBSUV+  VBS supply undervoltage  positive going 

Threshold 22  7.5  8.6  9.7 

VBSUV-  VBS supply undervoltage negative going 

Threshold 23  7.0  8.2  9.4 

VCCUV+  VCC supply undervoltage  positive going 

Threshold 24  7.4  8.5  9.6 

VCCUV-  VCC supply undervoltage negative going Threshold 

25  7.0  8.2  9.4 

IO+  Output high short circuit  pulsed current  26  2.0  2.5   —   VO = 0V, VIN = VDD 

PW  10 µs A 

IO-  Output low short circuit  pulsed current  27  2.0  2.5   —   VO = 15V, VIN = 0V

PW  10 µs 

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 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF 

60

Symbo 

Description VDD  Logic supply HIN  Logic input for high side gate driver output (HO), in phase SD  Logic input for shutdown LIN  Logic input for low side gate driver output (LO), in phase VSS  Logic ground 

VB  High side floating supply HO  High side gate drive output VS  High side floating supply return VCC  Low side supply LO  Low side gate drive output COM  Low side return 

Functional Block Diagram

Lead Definitions 

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 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF 

61

7

Vcc =15V HV = 10 to 500V/600V

10 0.1

10KF6

200 + F F

9 3 6

5 10 

7

0.1

F

HO 

H 10KF6100F

11 1 12

OUTPUT 10KF6

dVS >50 V/ns dt

13 2 

MONITOR

IRF820

Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit 

10 0.1 

Vcc =15V

VB# # 

HIN SD

LIN

F F9 3 6

510 CL 

111 

12

CL 

0.1

F

HO

LO

10+ 

F15V 

-V S 

(0 to 500V/600V)

10

F

!  "" " 

$ # $ # 

13 2  % # % # 

Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition 

# # 

'* 

$ # % # 

$ # 

Figure 5. Shutdown Waveform Definitions  Figure 6. Delay Matching Waveform Definitions 

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 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF 

62

Max. 

Max. 

Max. Typ. 

Max. 

Typ. 

ax. 

Typ 

    T   u   r   n  -    O   n    D   e    l   a   y    T    i   m   e    (   n   s    )

   T  u  r  n  -   O  n   D  e   l  a  y   T   i  m  e       (     n     s       )

    T   u   r   n  -    O

    f    f    D   e    l   a   y    T    i   m   e    (   n   s    )

    T   u   r   n  -    O

    f    f    D   e    l   a   y    T    i   m   e    (   n   s    )

    T   u   r   n  -    O   n    D   e    l   a   y    T    i   m   e    (   n   s    )

       T

  u  r  n  -   O   f           f

   D  e   l  a  y   T   i  m  e       (     n     s       )

 

250 250

200 200

150 150 Typ.

100 Typ. 100

50 50 

0

-50 -25 0 25 50 75 100 125

Temperature (°C)

0

10 12 14 16 18 20

VCC/VBS Supply Voltage (V) 

Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. VCC/VBS Supply Voltage 

250

200

150

Max.

Typ. 

250

200

150

100100

5050

 

0

0 2 4 6 8 10 12 14 16 18 20

VDD Supply Voltage (V) 

0-50 -25 0 25 50 75 100 125

Temperature (°C)

Figure 7C. Turn-On Time vs. VDD Supply Voltage  Figure 8A. Turn-Off Time vs. Temperature 

250 250 

200 200

150150

100

50

100

50

0

10 12 14 16 18 20

0

0 2 4 6 8 10 12 14 16 18 20

VCC/VBS Supply Voltage (V)VDD Supply Voltage (V) 

Figure 8B. Turn-Off Time vs. VCC/VBS Supply Voltage  Figure 8C. Turn-Off Time vs. VDD Supply Voltage 

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 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF 

63

Max. 

Typ. Max. Typ. 

Max. 

Typ M ax.

Typ. 

Max. 

Typ. 

Max. 

Typ. 

   S   h  u

   t   d  o  w  n

   D  e

   l  a  y

   T   i  m  e

   (  n  s

   )

    S    h   u    t    d   o   w   n    D   e    l   a   y    T    i   m   e    (   n   s    )

    T   u   r   n  -    O   n    R    i   s   e    T    i   m   e    (   n   s    )

    S    h   u    t    d   o   w   n    D   e    l   a   y    t    i   m   e    (   n   s    )

    T   u   r   n  -    O   n    R    i   s   e    T    i   m   e    (   n   s    )

    T   u   r   n  -    O

    f    f    F   a    l    l    T    i   m   e    (   n   s    )

 

250 250

200 200

150 150

100 100

50 50

0

-50 -25 0 25 50 75 100 125

Temperature (°C)

0

10 12 14 16 18 20

VCC/VBS Supply Voltage (V) 

Figure 9A. Shutdown Time vs. Temperature  Figure 9B. Shutdown Time vs. VCC/VBS Supply Voltage 

250 100

200 80 

150 60 

100 40

50 20

0 0 2 4 6 8 10 12 14 16 18 20 

VDD Supply Voltage (V) 

0

-50 -25 0 25 50 75 100 125

Temperature (°C)

Figure 9C. Shutdown Time vs. VDD Supply Voltage  Figure 10A. Turn-On Rise Time vs. Temperature 

100 50

80 40

60 30

40 20

20 10

0

10 12 14 16 18 20

VBIAS Supply Voltage (V)

0

-50 -25 0 25 50 75 100 125

Temperature (°C)

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SYMBOL  PARAMETER  MAX.  UNIT 

VDS

ID

Ptot

T j 

RDS(ON) 

Drain-source voltageDrain current (DC)

Total power dissipationJunction temperatureDrain-source on-stateresistance VGS = 10 V 

5549

11017522 

V A

W̊C m 

APPENDIX-D

N-channel enhancement mode IRFZ44NTrenchMOSTM transistor  

GENERAL DESCRIPTION QUICK REFERENCE DATA 

N-channel enhancement modestandard level field-effect powertransistor in a plastic envelope using’trench’ technology. The device

features very low on-state resistanceand has integral zener diodes givingESD protection up to 2kV. It isintended for use in switched modepower supplies and general purposeswitching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL 

PIN DESCRIPTIONd 

tab

1 gate 

2 drain

3 source tab

drain

g

1 2 3 s 

LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) 

SYMBOL  PARAMETER  CONDITIONS  MIN.  MAX.  UNIT 

VDS

VDGR

VGSID 

ID 

IDM Ptot

Tstg, T j 

Drain-source voltageDrain-gate voltage

Gate-source voltageDrain current (DC)Drain current (DC)Drain current (pulse peak value)Total power dissipationStorage & operating temperature 

-RGS = 20 k 

-Tmb = 25 ˚CTmb = 100 ˚CTmb = 25 ˚CTmb = 25 ˚C - 

--

-----

- 55 

5555

204935160110175 

V V V A A A

W̊C 

ESD LIMITING VALUE 

SYMBOL  PARAMETER  CONDITIONS  MIN.  MAX.  UNIT 

VC  Electrostatic discharge capacitorvoltage, all pins 

Human body model(100 pF, 1.5 k ) 

-  2  kV 

THERMAL RESISTANCES 

SYMBOL  PARAMETER  CONDITIONS  TYP.  MAX.  UNIT 

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 Rth j-mb

Rth j-a 

Thermal resistance junction tomounting baseThermal resistance junction toambient 

-

in free air  

-

60 

1.4

K/W

K/W 

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N-channel enhancement mode IRFZ44NTrenchMOSTM transistor

STATIC CHARACTERISTICS T j= 25˚C unless otherwise specified 

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 

V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V voltage T j = -55˚C 50 - -

VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V T j = 175˚C 1.0 - - V T j = -55˚C - - 4.4 IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 A 

T j

= 175˚C - - 500 A IGSS Gate source leakage current VGS = 10 V; VDS = 0 V - 0.04 1 A 

T j = 175˚C - - 20 A V(BR)GSS Gate source breakdown voltage IG = 1 mA; 16 - - V 

RDS(ON) Drain-source on-state VGS = 10 V; ID = 25 A - 15 22 m resistance T j = 175˚C - - 42 m

DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified 

SYMBOL  PARAMETER  CONDITIONS  MIN.  TYP.  MAX.  UNIT 

gfs  Forward transconductance  VDS = 25 V; ID = 25 A  6  -  -  S 

Ciss  Input capacitance  VGS = 0 V; VDS = 25 V; f = 1 MHz  -  1350  1800  pF Coss  Output capacitance  -  330  400  pF Crss  Feedback capacitance  -  155  215  pF 

Q   Total gate charge  VDD = 44 V; ID = 50 A; VGS = 10 V  -  -  62  nC Qgs  Gate-cource charge  -  -  15  nC Qgd  Gate-drain (miller) charge  -  -  26  nC 

td on  Turn-on delay time  VDD = 30 V; ID = 25 A;  -  18  26  ns tr   Turn-on rise time  VGS = 10 V; RG = 10  -  50  75  ns td off   Turn-off delay time  Resistive load  -  40  50  ns tf   Turn-off fall time  -  30  40  ns 

Ld  Internal drain inductance  Measured from contact screw ontab to centre of die 

-  3.5  -  nH 

Ld  Internal drain inductance  Measured from drain lead 6 mm

from package to centre of die 

-  4.5  -  nH 

Ls  Internal source inductance  Measured from source lead 6 mmfrom package to source bond pad 

-  7.5  -  nH 

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T j = 25˚C unless otherwise specified 

SYMBOL  PARAMETER  CONDITIONS  MIN.  TYP.  MAX.  UNIT 

IDR  Continuous reverse draincurrent 

-  -  49   A 

IDRM  Pulsed reverse drain current  -  -  160   A VSD  Diode forward voltage  IF = 25 A; VGS = 0 V  -  0.95  1.2  V 

IF = 40 A; VGS = 0 V

 -  1.0  - 

trr   Reverse recovery time  IF = 40 A; -dIF/dt = 100 A/  s;  -  47  -  ns Qrr   Reverse recovery charge  VGS = -10 V; VR = 30 V  -  0.15  -  C 

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N-channel enhancement mode IRFZ44NTrenchMOSTM transistor

AVALANCHE LIMITING VALUE 

SYMBOL  PARAMETER  CONDITIONS  MIN.  TYP.  MAX.  UNIT 

WDSS  Drain-source non-repetitiveunclamped inductive turn-offenergy 

ID = 45 A; VDD 25 V; VGS = 10 V; RGS = 50 ; Tmb = 25 ˚C 

-  -  110  mJ 

120

110100

90

80

70

60

50

40

30

20

10

0

PD% Normalised Power Derating 

0 20 40 60 80 100 120 140 160 180

Tmb / C

1000

ID/A

100

10

1

RDS(ON) =VDS/ID

DC

1 10 VDS/V

tp =

1 us

10us

100 us

1 ms

10ms

100ms

100

Fig.1. Normalised power dissipation.

PD% = 100 PD/PD 25 ˚C = f(Tmb) Fig.3. Safe operating area. Tmb = 25 ˚C 

ID & IDM = f(VDS); IDM single pulse; parameter tp 

120

110

100

90

80

70

60

50

40

30

2010

ID% Normalised Current Derating 10

1

0.1

0.01

Zth/(K/W)

0.5

0.2

0.1

0.05

0.02

0

PD tp 

T

D =tp 

t

0 20 40 60 80 100 120 140 160 180

Tmb / C

Fig.2. Normalised continuous drain current.ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS 10 V

0.0011E-06 0.0001 0.01 1 100t/s

Fig.4. Transient thermal impedance.Zth j-mb = f(t); parameter D = tp/T 

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BUK959-60

BUK759-60

16

10 

8.5 VGS/V = 

VGS/V = 

6.5 7 

8 9 

10 

Tj/C =  175  25 

max  

typ  

N-channel enhancement mode IRFZ44NTrenchMOSTM transistor

100 

ID/A 

80 

60 

40 

20 

0 0 2 4 

VDS/V6 8 10 

8.0

7.5

7.0

6.5

6.0

5.5

5.04.54.0

30

gfs/S 

25

20

15

10

5

0 0 20 40 60 80 100 

ID/A 

Fig.5. Typical output characteristics, T j = 25 ˚C. ID = f(VDS); parameter VGS 

Fig.8. Typical transconductance, T j = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 

RDS(ON)/mOhm 40 2.5

a Rds(on) normlised to 25degC

35

2

30

25 1.5

20

1

15

10 0 10 20 30 40 50 60 70 80 90 

ID/A

0.5-100 -50 0 50 100 150 200

Tmb / degC

Fig.6. Typical on-state resistance, T j = 25 ˚C. RDS(ON) = f(ID); parameter VGS 

Fig.9. Normalised drain-source on-state resistance.a = RDS(ON)/RDS(ON)25 ˚C = f(T j); ID = 25 A; VGS = 10 V

100

ID/A

80

VGS(TO) / V 

5

4

60 3 

40 2 

20 1

0 0  2  4  6  8  10 12 

0 -100 -50  0  50  100  150  200 

VGS/V  Tj / C 

Fig.7. Typical transfer characteristics.ID = f(VGS) ; conditions: VDS = 25 V; parameter T j 

Fig.10. Gate threshold voltage.VGS(TO) = f(T j); conditions: ID = 1 mA; VDS = VGS 

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Tj/C =  175  25 

VDS = 14V 

VDS = 4V 

   T   h  o  u  s  a  n   d

  s

  p   F

+

N-channel enhancement mode IRFZ44NTrenchMOSTM transistor

1E-01Sub-Threshold Conduction 100

IF/A 

80

1E-02

1E-032% typ 98%

60 

40

1E-04

20

1E-05

1E-060 1 2 3 4 5

Fig.11. Sub-threshold drain current. 

0 0 0.2 0.4 0.6 0.8 1 1.2 1.4

VSDS/V 

Fig.14. Typical reverse diode current. ID = f(VGS); conditions: T j = 25 ˚C; VDS = VGS  IF = f(VSDS); conditions: VGS = 0 V; parameter T j 

2.5 

1.5 

.5

0 0.01 0.1 1 VDS/V

Ciss 

Coss 

Crss 

10 100

120

110

100

90

80

7060

50

40

30

20

10

0

WDSS%

20 40 60 80 100 120 140 160 180

Tmb / C

Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 

Fig.15. Normalised avalanche energy rating.WDSS% = f(Tmb); conditions: ID = 49 A 

12

VGS/V

10

8

6

4

VGS

0

L

VDS

T.U.T.

VDD

--ID/100

2 RGSR 01

shunt

0 0 10 20

QG/nC  30 40 50

Fig.13. Typical turn-on gate-charge characteristics.  Fig.16. Avalanche energy test circuit.2

 BV BV V  

VGS = f(QG); conditions: ID = 50 A; parameter VDSW  DSS 0.5  LI  D DSS DSS DD

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N-channel enhancement mode IRFZ44NTrenchMOSTM transistor

MECHANICAL DATA 

Dimensions mm

Net Mass: 2 g

10,3

max

3,7 1,3

4,5max

2,8 5,9min

15,8 max

3,0 max not tinned

1,3 max 

1 2 3

3,0

13,5min

(2x) 

2,54 2,54 

0,9 max (3x)0,6

2,4

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to preventdamage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.3. Epoxy meets UL94 V0 at 1/8".

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