bjt bias 1 - Amazon S3 · PDF fileEmitter-Stabilized Bias Circuit Adding an emitter resistor...
Transcript of bjt bias 1 - Amazon S3 · PDF fileEmitter-Stabilized Bias Circuit Adding an emitter resistor...
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Fixed Bias 1
BJT Fixed Bias
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BJT Biasing 1For Fixed Bias Configuration:• Draw Equivalent Input circuit• Draw Equivalent Output circuit• Write necessary KVL and KCL Equations• Determine the Quiescent Operating Point
– Graphical Solution using Loadlines– Computational Analysis
• Design and test design using a computer simulation
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Fixed Bias 2
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Complete CE Amplifier with Fixed Bias
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Fixed Bias and Equivalent DC Circuit
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Fixed Bias 3
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Fixed-Bias Circuit
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DC Equivalent Circuit
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Fixed Bias 4
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Base-Emitter (Input) Loop
Using Kirchoff’s voltage law: – VCC + IBRB + VBE = 0
Solving for IB:C C BE
B B
V - VI = R
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Collector-Emitter (Output) Loop
Since: IC = β IB
Using Kirchoff’s voltage law: – VCC + IC RC + VCE = 0Because: VCE = VC – VE
Since VE = 0V, then: VC = VCE
And VCE = VCC - IC RC
Also: VBE = VB - VE
with VE = 0V, then: VB = VBE
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BJT Saturation Regions
When the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that:
CC CE Csat
C
CEwhere
V - VI = R
V = 0 .2 V
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Determining Icsat
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Determining ICSAT for the fixed-bias configuration
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Load Line Analysis
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Load Line AnalysisThe end points of the line are : ICsat and VCEcutoffFor load line analysis, use VCE = 0 for ICSAT, and IC = 0 for VCEcutoff
ICsat:
VCEcutoff:
Where IB intersects with the load line we have the Q pointQ-point is the particular operating point: • Value of RB• Sets the value of IB• Where IB and Load Line intersect• Sets the values of VCE and IC.
CE
C
CC Csat V 0V
C
CE CC I 0mA
VI = R
V = V
|
|=
=
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Circuit values effect Q-point
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Circuit values effect Q-point (continued)
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Circuit values effect Q-point (continued)
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Load-line analysis
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DC Fixed Bias Circuit Example
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Fixed Bias 10
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Loadline Example Family of Curves
Emitter Stabilized Bias
ENGI 242ELEC 222
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Fixed Bias 11
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BJT Emitter BiasFor the Emitter Stabilized Bias Configuration:• Draw Equivalent Input circuit• Draw Equivalent Output circuit• Write necessary KVL and KCL Equations• Determine the Quiescent Operating Point
– Graphical Solution using Loadlines– Computational Analysis
• Design and test design using a computer simulation
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Improved Bias StabilityThe addition of RE to the Emitter circuit improves the stability of a transistor output
Stability refers to a bias circuit in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor forward current gain (β)The temperature (TA or ambient temperature) surrounding the transistor circuit is not always constantTherefore, the transistor β is not a constant value
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Fixed Bias 12
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Emitter-Stabilized Bias Circuit
Adding an emitter resistor to the circuit between the emitter lead and ground stabilizes the bias circuit over Fixed Bias
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Base-Emitter Loop
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Equivalent Network
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Reflected Input impedance of RE
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Base-Emitter Loop
Applying Kirchoffs voltage law: - VCC + IB RB + VBE +IE RE = 0 Since: IE = (β + 1) IB
We can write: - VCC + IB RB + VBE + (β + 1) IB RE = 0
Grouping terms and solving for IB:
Or we could solve for IE with:
CC BEB
B E
V - VI = R + (β+1)R
BCC E BE E E
R- V + I + V + I R = 0 ( + 1)
β
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Collector-Emitter Loop
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Collector-Emitter Loop
Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0Assuming that IE ≅ IC and solving for VCE: VCE = VCC – IC (RC + RE) If we can not use IE ≅ IC the IC = αIE and: VCE = VCC – IC (RC + αRE)Solve for VE: VE = IE RE
Solve for VC: VC = VCC - IC RC
or VC = VCE + IE RE
Solve for VB: VB = VCC - IB RB
or VB = VBE + IE RE
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Transistor Saturation
CC CE CSAT
C E
V - VI = R + R
At saturation, VCE is at a minimum
We will find the value VCEsat = 0.2V
For load line analysis, we use VCE = 0
To solve for ICSAT, use the output KVL equation:
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Load Line Analysis
The load line end points can be calculated:
At cutoff:
At saturation:
C CE CC I = 0 mAV V |=
CE
CCC V = 0V
C E
VI = R + R
|
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Emitter Stabilized Bias Circuit Example
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Design of an Emitter Bias CE Amplifier
Where .1VCC ≤ VE ≤ .2VCC
And .4VCC ≤ VC ≤ .6VCC
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Emitter Bias with Dual Supply
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Emitter Bias with Dual Supply
Input Output