BIST for Regular Structures

C. Stroud 11/06 BIST for Regular Structures 1

DFT for Regular Structures

Regular Structure Fault ModelsRAM BIST ArchitecturesROM & PLA BIST ArchitecturesBypassing During BISTBenefits & Limitations


Testing Regular Structures

General model for a regular structure:two-dimensional array of identical cells

densely packed cells

surrounded by dedicated I/O blocksFunctional operations:

Read/Write: RAM, FIFO, Register file, CAM, multi-port RAMsRead only: ROM, PLA

Regular structures require very specific test algorithms

close pack cells sustain non-standard (non-classical) fault models

CellArray

Input Reg

Output Reg

DECODE


Classical & Non-Classical FaultsClassical Faults:

Stuck fault: cell contents sa0 or sa1test each cell with both logic values

Addressing fault: address decoder selects wrong address test all addresses with unique data

Non-Classical FaultsTransition fault: cell doesn’t undergo 0 → 1 or 1 → 0 transition

test both transitionsRetention fault: cell looses its logic value after a certain time

read data after a period of no activity (read or write)Destructive read: read operation changes the contents of a cell

perform back-to-back reads of same cellsPattern-sensitivity: contents of cell affected by contents of other cells

surround cell with opposite logic values in adjacent cells


Example: Pattern Sensitive Faults in RAMsTest by surrounding cell with opposite logic values in adjacent cells

cell adjacency dependent on physical layout and not addressing space

Checker board pattern typically useddoesn’t detect diagonally adjacencyreal checker board at cell & subcell level depends on physical layout

Bit-bari-1 Biti-1 Biti Bit-bari Bit-bari+1 Bit-i+1

Biti-1 Bit-bari-1 Biti Bit-bari Biti+1 Bit-bari+1

Example seen in RAMs at Bell Labs (1985)0 in Cell i lets Cell i+1 to function normally1 in Cell i forces Cell i+1 to 1 (or to 0)

0 0 0 0 1/0 0 0 0 0

1 0 1 0 1 0 1 0 1

1 1 1 0 0 0 1 1 1

1|0

0|1


Example RAM Test Algorithms


Example RAM Test AlgorithmsFault detection capabilities vary with test algorithm

Longer test times for higher fault detectionNew algorithms developed for new faults/defects

Trade-off test time with fault detection capabilities


March LR Test for RAMsDetects

neighborhood pattern sensitivity faultsintra-word coupling faultsbridging faults

Notation↓ = address downward ↑ = address upward ↨ = address either wayw0 = write 0 r1 = read 1

Length of test = 16NN = number of address locations

Word-oriented memories needBackground Data Sequences (BDS)

Number of BDS = ⎡log2(K)+1⎤, where K = data widthMarch Y is simpler algorithm

Length of test = 8N

↨(w0); ↑(r0, w1,r1); ↓(r1,w0,r0); ↑(r0);

March Y w/o BDS

↨(w00); ↓(r00, w11); ↑(r11,w00,r00,r00, w11);

↑(r11,w00); ↑(r00,w11,r11,r11,w00); ↑(r00,w01,w10,r10);↑(r10,w01,r01); ↑(r01);

March LR with

BDS

↨(w0); ↓(r0, w1); ↑(r1,w0,r0,r0, w1); ↑(r1,w0); ↑(r0,w1,r1,r1,w0); ↑(r0);

March LR w/o

BDS


BIST for Regular StructuresClose packed cells prevent additional DFT logic in core

area & performance penalties too great!different physical layouts require different test sequences

Use parameterized generators for regular structuresall structures then have same basic layouttest development effort determines test algorithmstest algorithms reusable for all structures produced by generator

reusable solutions are cheaperdesign & test development cost shared by several projects

implement BIST in I/O dedicated blockspreferably produced by generator

implement full scan in I/O dedicated blocksallows independent test of embedded structure and general logic


Example: BIST for RAMsFrom Lucent TechnologiesLucent TechnologiesIncorporated in RAM generatorParameters:

M address bitsW wordsN bits/word

BIST interface:BIST = start self-testBC = BIST completeBF = BIST flag (pass/fail)BFC = BIST flag check

initiate test to check that BF is not stuck at 0can be controlled by boundary scan using BRIC

RAM

BISTControl

BISTBFC

BCBF

MuxMuxMux

DataTPG

AddressTPG

ORAcomparator

SystemAddress Write Data

SystemData Out


Example: BIST for RAMs (cont)

Notation:W0 = Write 0W1 = Write 1R0 = Read 0R1 = Read 1W0→ = write walking 0W1→ = write walking 1R0→ = read walking 0R1→ = read walking 1N = number of words⇑ = access addresses 0 → N⇓ = access addresses N → 0⇒ = access one address

LucentLucent’’ss Test Algorithm:100% fault coverage for all faults considered13N march test

N = # address locations

1. ⇑ W02. ⇑ (R0, W1, W0, W1)3. ⇑ (R1, W0, R0, W1)4. ⇓ (R1, W0, W1, W0)5. ⇓ (R0, W1, R1, W0)6. ⇒ (W0→ ,R0→)7. ⇒ (W1→ ,R1→)


Example: BIST for RAMs (cont)

Area overhead vs size for static RAM with BIST logic13N march test3N data retention test N = number of words

AreaOverhead

(%)

RAM Size(Kbytes)

20

15

10

5

02 4 8 16 32 64 128 256 512


BIST for ROMs and PLAs

Subset of test for RAMsROMs/PLAs are read only

Test time = 2NReverse the direction of addressing to reduce fault masking in MISR


Bypassing Regular Structures

Embedded regular structure can be bypassed during BIST of general sequential logic

Random type vectors for logic BIST to not test regular structuresRegular structure tend to filter the random type vectors of logic BIST

Two types of bypass techniques similar to test points


Regular Structure BIST SummarySpecific algorithms needed to detect non-classical faults associated with regular structures

TPG for these algorithms typically implemented as FSMBenefits

Good fault coverage without need for fault simulationEliminates the problem of testing embedded structures

Vertical testability for device through system-level testingImplementation can be (and has been) automated in payout generator for regular structure

LimitationsExtra area overhead

Extra BIST functions to controlExtra test sessions

BIST for Regular Structures

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