Binocular Bilateral Controller: A Hardware Fault Tolerant Implementation

Marylène AudetMarch 2001

VLSI Testing

Agenda

• Goals

• The Binocular Controller

• Fault-Tolerant Designs

• Conclusion

Goals

•Implement a binocular controller using eye movements model•Design a fault-tolerant system•Simulate and test the controller

The Binocular Controller

•Conjugate Component (EC) : average direction in which eyes are pointed

•Vergence Component (EV) : angle subtended by two lines of sight

•EC = 1/2 (ER - EL)

•EV = (ER +EL)

+ +- -

R etinal errorseL eR

E C

E R

E V

E L

Target

+

+-

-

The Binocular Controller (2)

E L*

iL

g

d

D L

M (s)

+

++

E R*

iR

g

d

D R

M (s)

+

+ +

The Binocular Controller (3)

E x

Screen

PSDAM P

PSDAM P

Anti-A liasing F ilter

Anti-A liasing F ilter

Ix1,Ix2

Iy1,Iy2

R x

R y

"X" Tendons

E x

T x

T y

2D Target

E y

"Y" Tendons

C om puter

A(s)

kfs+1

E L*

T L

iL = k verg (eR+eL)-k conj(eR-eL)iR = k verg (eR+eL)+k conj(eR-eL)

iL

eL

+k1

5

P(s)

-

+

g

ka

dkbkc

D L

M (s)R L

++

+

S&H

+

+

++

-

+

retina l error

C ontro ller

M echanical Eye and F ilter

A(s)

kfs+1

E R*

T R

iR

eR

+ k1

5

P(s)

-

+

g

ka

d kb kc

D L

M (s)R R

++

+

S&H

+

+

++

-

+

retina l error

fast

fastfast

fast fast

slow fast

slow slow

slowslow

S&H

fast

slow

The Binocular Controller (5)

•Digital Implementation requires delay insertion•Slow Clock (order of KHz)•12-bit digitized Inputs•All parameters shall be programmable via a CPU or switches •Target technology is FPGA (Xilinx)

Ref: “Binocular Coordination Providing Stable Tracking and Rapid Reorientation Using A Bilateral Controller Inspired By Nature”, Ross Wagner,PHD Thesis, McGill University, 1997

FOR MORE INFO...

Fault-Tolerant Designs

• Introduction• MTBF• Triple Modular Redundancy• Self Purging Techniques• Sift-Out Modular Redundancy• Rollback Implementation or Time

Redundancy• Berger and Weight-Based Codes

Fault-Tolerant Designs (2)

• Fault-tolerant Design are used in the Military and Aerospace, Medical, Banking, etc. industries

• Deep-submicron technology: compensates low yields.

• Goal: Very High Reliability measured using MTBF evaluations.

• Uses Concurrent Built-In Self-Test and Redundancy Techniques.

MTBF

• MTBF: Mean-Time Between Failures• For example:

– Processor of 100 Million Instruction Per Seconds (100 MIPS)

– Reliabiltiy Factor R(t) = (0.9)12 -> 1 Failure/1012 Events

– MTBF = (1012) * (10-8) = 10 000 Seconds ~ 2.7 Hours

Triple Modular Redundancy

•As good as its Voter •Voter must be Totally Self-Checking•Redundancy cannot be tested off line -> must have a way of disabling the redundant circuit•High Area Cost•Module Partitioning

M odule 1

M odule 3

M odule 2

Voter

Voter

Z 11

Z 21

Z 12

Z 22

Z 13

Z 23

& &&

+

Z 1

Z 2

Z 11 Z 1

2 Z 13

Z 1

M ajority Voting C ircuit

Self-Purging and Sift-Out

•Self-Purging: Remove Faulty Path by Comparing

– Problem: may require an exterrnal arbiter if there is a tie

– Requires feedback from Voter

•Sift-Out: all decision done by controller but Voter is free from controller.

M odule 1

M odule 3

M odule 2

Z

M odule 4

M odule 5

Voter

C ontro llerO K

Fail

Rollback Implementation

•Basics: Checkpoints exists to fall-back•Must have a state diagram detecting permanent faults•Checker can be any encoder

C hecker

R 1 R 2

D FF

R 0

Lo

gic

e rror

in

out

S0 S2S1 S3 S3xxx S4

S1S0 S2 xxxS3 S3

S0 S1 S3S2 xxx

R 0

clock

R 2

R 1

error

Error Coding Techniques

•Concurrent Checking / on-line.•Checker detects 1->0 and 0-> 1 Transitions Errors.•Checkbits can be positional (Hamming) / non-positional (Berger) within the output vector•Can assign a “weight” to each output.

Function Logic

C heck Sym bol

G enerator

C hecker

O utputsn

Error D etectionk

n

m

mInputs

Conclusion

• Design Partitioning for Modular Redundancy: Adders and Multipliers

• Checking Algorithm for Sift-Out Implementation

• Verify against analog counterpart.