Benefits and Features - Maxim Integrated

General DescriptionThe MAX17823H are data-acquisition systems for the management of high-voltage battery modules. The systems feature a 12-bit SAR ADC that can measure 12 cell voltages and two temperatures in 161µs. There are 12 internal switches for cell balancing and extensive built-in diagnostics. Up to 32 devices can be daisy-chained together to manage 384 cells and monitor 64 temperatures.Cell voltages (0 to 5V) are measured differentially over a 65V common-mode range. Cell measurements have a typical accuracy of 2mV (3.6V cell, +25°C). If oversam-pling is enabled, up to 128 measurements per channel can be averaged internally with 14-bit resolution. The sys-tem can shut itself down in the event of a thermal overload by measuring its own die temperature.The systems use Maxim’s battery-management UART protocol for robust communications and when used in conjunction with the MAX17880 12-channel battery moni-tor, they are ideal for automotive battery-management systems that require a high safety-integrity level.

Applications High-Voltage Battery Stacks Electric Vehicles (EVs) Hybrid Electric Vehicles (HEVs) Electric Bikes Battery-Backup Systems (UPS) Super-Cap Systems Battery-Powered Tools

Benefits and Features AECQ-100 Grade 2 Temperature Range

• -40°C to +105°C Operating Voltage from 9V to 65V Ultra-Low Power Operation

• Standby Mode: 2mA• Shutdown Mode: 2µA

12 Cell-Voltage-Measurement Channels• 2mV Accuracy (3.6V, +25°C)• 5mV Accuracy (0°C to +45°C)• 10mV Accuracy (-40°C to +105°C)

12 Cell-Balancing Switches• Up to 650mA per Switch• Emergency-Discharge Mode

Two Temperature-Measurement Channels Die Temperature Measurement Automatic Thermal Protection 29 Voltage Threshold Alerts

• 12 Overvoltage Faults• 12 Undervoltage Faults• Two Overtemperature Faults• Two Undertemperature Faults• One Cell-Mismatch Alert

(Highest Cell vs. Lowest Cell) Four GPIOs Built-in Diagnostics to Support ASIL D and

FMEA Requirements Battery-Management UART Protocol

• Daisy-Chain Up to 32 Devices• Communication Port Isolation• Up to 2Mbps Baud Rate (Autodetect)• 1.5µs Propagation Delay per Device• Packet-Error Checking (PEC)

Factory-Trimmed Oscillators• No External Crystals Required

10mm x 10mm Package (64-Pin LQFP)

Ordering Information appears at end of data sheet.

19-100391; Rev 0; 8/18

MAX17823H 12-Channel, High-Voltage Data-Acquisition Systems

EVALUATION KIT AVAILABLE

TABLE OF CONTENTS

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Simplified Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Precision Internal Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Measurement Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Cell Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Input Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Block Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Auxiliary Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29THRM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Computing Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Temperature Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Die Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Die Temperature Alert. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Acquisition Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Acquisition Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Measurement Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Double-buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Measurement Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Voltage Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Cell Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Cell Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Temperature Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Cell-Balancing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38


www.maximintegrated.com Maxim Integrated 2

TABLE OF CONTENTS (CONTINUED)

Maximum Cell-Balancing Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Cell-Balancing Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Emergency-Discharge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Low-Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41HV Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Device ID Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Power-On and Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Power-On Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Power-On Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Shutdown Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47UART Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48UART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48UART RX Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49UART Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49External Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Internal Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Baud-Rate Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Battery-Management UART Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Command Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Preamble Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Stop Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52UART Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52UART Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Command Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Command Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Data-Check Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54PEC Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Alive-Counter Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Fill Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54




Battery-Management UART Protocol Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55HELLOALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

WRITEALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55WRITEDEVICE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56READALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56READDEVICE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57ROLLCALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58ALTREF Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60VAA Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60LSAMP Offset Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Zero-Scale ADC Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Full-Scale ADC Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62BALSW Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62BALSW Short Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62BALSW Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Even/Odd Sense-Wire Open Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Diagnostic Test Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Shutdown Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70HVMUX Switch Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71HVMUX Switch Shorted Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72HVMUX Test Source Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Cn Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Cn Shorted to SWn Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Cn Leakage Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Cell Overvoltage Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Cell Undervoltage Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76ALRTHVUV Comparator Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76HVMUX Sequencer Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76ALU Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78AUXINn Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Calibration ROM Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Vehicle Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Battery Management Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Daisy-Chain System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Distributed-Module Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83




Combining MAX17823H and MAX17880 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Acquisition Latency for Daisy-Chain Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Power-Supply Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Connecting Cell Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84External Cell Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84External Cell-Balancing Using FET Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85External Cell Balancing Using BJT Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86External Cell-Balancing Short-Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87High-Z Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88UART Supplemental ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Single-Ended RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89UART Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90UART Transformer Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90UART Optical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Device Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92PEC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Version Register (address 0x00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96ADDRESS Register (address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97STATUS Register (address 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98FMEA1 Register (address 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99ALRTCELL Register (address 0x04). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ALRTOVCELL Register (address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ALRTUVCELL Register (address 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101ALRTBALSW Register (address 0x08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MINMAXCELL Register (address 0x0A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102FMEA2 Register (address 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102ID1 Register (address 0x0D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103ID2 Register (address 0x0E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103DEVCFG1 Register (address 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104GPIO Register (address 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105MEASUREEN Register (address 0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105SCANCTRL Register (address 0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106ALRTOVEN Register (address 0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107




ALRTUVEN Register (address 0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108WATCHDOG Register (address 0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109ACQCFG Register (address 0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110BALSWEN Register (address 0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111DEVCFG2 Register (address 0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112BALDIAGCFG1 Register (address 0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113BALSWDCHG Register (address 0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114TOPCELL Register (address 0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115CELLn Register (addresses 0x20 to 0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115VBLOCK Register (address 0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116AIN1 Register (address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116AIN2 Register (address 0x2E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117TOTAL Register (address 0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117OVTHCLR Register (address 0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118OVTHSET Register (address 0x42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118UVTHCLR Register (address 0x44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119UVTHSET Register (address 0x46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119MSMTCH Register (address 0x48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120AINOT Register (address 0x49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120AINUT Register (address 0x4A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121BALSHRTTHR Register (address 0x4B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121BALLOWTHR Register (address 0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122BALHIGHTHR Register (address 0x4D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122DIAG Register (address 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123DIAGCFG Register (address 0x51). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123CTSTEN Register (address 0x52). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125ADCTEST1A Register (address 0x57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125ADCTEST1B Register (address 0x58) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126ADCTEST2A Register (address 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126ADCTEST2B Register (address 0x5A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127CALx Registers (addresses 0xC0–0xCA, 0xCF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129



LIST OF FIGURES

Figure 1. Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 2. ESD Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 3. Analog Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 4. VBLKP Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 5. Auxiliary Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 6. Auxiliary Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 7. Die Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 8. Acquisition Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 9. Acquisition, OVSAMP[2:0] = 0h and SCANMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 10. Acquisition, OVSAMP[2:0] > 0 and SCANMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 11. Measurement Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 12. Double-Buffer Mode DATAMOVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 13. Double-Buffer Mode Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 14. Cell Voltage Alert Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 15. Internal Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 16. Cell-Balancing Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 17. Low-Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Figure 18. HV Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 19. SHDNL Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 20. Power-On Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 21. Shutdown Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 22. Power-On and Shutdown Timing (UART Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 23. Shutdown Timing (Software Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 24. UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Figure 25. UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Figure 26. UART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Figure 27. Command Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 28. Preamble Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 29. Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 30. Stop Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 31. Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 32. ALTREF Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 33. VAA Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 34. LSAMP Offset Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Figure 35. Zero-Scale ADC Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Figure 36. Full-Scale ADC Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 37. Balancing Switch Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62



LIST OF FIGURES (CONTINUED)

Figure 38. BALSW Short Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 39. BALSW Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 40. Cell Sense-Wire Open Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Figure 41. Sense-Wire Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 42. Test Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Figure 43. Shutdown Diagnostic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 44. HVMUX Switch Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 45. SWn to Cn Short. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Figure 46. SWn-1 to Cn Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Figure 47. Redundant HVMUX Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 48. HVMUX Sequencer Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 49. HVMUX Sequencer Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 50. ALU Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Figure 51. AUXINn Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 52. AUXINn Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 53. Electric Vehicle System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Figure 54. Daisy-Chain System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Figure 55. Distributed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 56. Power-Supply Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 57. External Balancing (FET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 58. External Cell Balancing (BJT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Figure 59. UART Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Figure 60. High-Z Idle Mode Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Figure 61. External ESD Protection for UART TX Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Figure 62. External ESD Protection for UART RX Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Figure 63. Application Circuit for Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Figure 64. UART Transformer Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Figure 65. UART Optical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 66. Device Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 67. CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Figure 68. PEC Calculation Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93



LIST OF TABLES

Table 1. System Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 2. Numeric Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 3. Data Acquisition Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 4. Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 5. THRM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 6. AINTIME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 7. Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Table 8. Acquisition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Table 9. Acquisition Time Examples (with AINCFG[5:0] = 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Table 10. Measurement Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Table 11. Maximum Allowed Balancing Current per Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 12. Cell-Balancing Watchdog Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 13. Emergency-Discharge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Table 14. Low-Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 15. Low-Voltage Regulator Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 16. HV Charge-Pump Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 17. Oscillator Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 18. Shutdown Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 19. UART RX Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 20. Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 21. Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 22. Command-Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 23. Command-Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 24. Data-Check Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 25. HELLOALL Sequencing (z = Total Number of Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Table 26. WRITEALL Sequencing (Unchanged by Daisy-Chain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 27. WRITEDEVICE Sequencing (Unchanged by Daisy-Chain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 28. READALL Command Sequencing (z = no. of devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Table 29. READDEVICE Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 30. Summary of Built-In Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58



Table 31. BALSW Short-Diagnostic Auto Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 32. BALSW Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 33. BALSW Open-Diagnostic Auto Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 34. Odd Sense-Wire Open-Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Table 35. Even Sense-Wire Open-Measurement Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Table 36. Sense-Wire Open-Diagnostic Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table 37. HVMUX Output Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 38. Shutdown Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Table 39. HVMUX Switch Open Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 40. HVMUX Test Source Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Table 41. Cn Pin Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Table 42. CRC Bit Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Table 43. FET Balancing Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Table 44. BJT Balancing Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

LIST OF TABLES (CONTINUED)



Simplified Operating Circuit

CELL1

TO MODULE n+1 MAX17823H

C0

HV

AUXIN2AUXIN1

THRM

VDDL1

VAA

AGND

CPP

CPN

GPIO0GPIO1

TO MODULE n-1

CELL2

CELL3

CELL4

CELL5

CELL6

CELL7

CELL8

CELL9

CELL10

CELL11

CELL12

MODULE n-1 OR HOST

SW0

RXLN

TXUPTXUN

MODULE n+1

RXLPRXLNUART

INTERFACE

SHDNL

RXLP TXUPTXUN

UARTINTERFACE

GNDL1

VBLKP RXUP TXLPTXLNRXUN

TXLNTXLP RXUP

RXUN

C82 0.1µF100V

C814.7µF50V

C83 1.0µF16V

GPIO2GPIO3

C87 1.0nF25V

NOTES: 1. CAPACITOR RATINGS SHOWN IN THIS DATASHEET ARE BASED ON EXPECTED CONDITIONS AND MAY BE MODIFIED BASED ON APPLICATIONS REQUIREMENTS.2. D90, D91 (OPTIONAL) PROVIDE DEVICE POWER THROUGH SENSE WIRES IF ANY VBAT SUPPLY WIRE IS OPEN.3. SEE APPLICATIONS SECTION FOR UART INTERFACE.4. R0 – R13: 1kΩ (APPLICATION DEPENDENT)5. R20 – R32: 12Ω (APPLICATION DEPENDENT)5. C0 – C12, C21 – C32: 100nF (APPLICATION DEPENDENT)6. C13: 470nF (APPLICATION DEPENDENT)

C85 0.47µF16V

VDDL2

GNDL2

C84 0.47µF16V

D82BAV70

C86 0.47µF16V

VDDL3

GNDL3

C802.2µF 100V

AGND

TO / FROM HOST(IF USED)

CTG

R80 10Ω

15-WIRE BATTERY

PACK

D91

D90

VBAT+

VBAT-

R0

R20C0 C21

C1

SW1

R1

R21C1 C22

C2

SW2

R2

R22C2 C23

C3

SW3

R3

R23C3 C24

C4

SW4

R4

R24C4 C25

C5

SW5

R5

R25C5 C26

C6

SW6

R6

R26C6 C27

C7

SW7

R7

R27C7 C28

C8

SW8

R8

R28C8 C29

C9

SW9

R9

R29C9 C30

C10

SW10

R10

R30C10 C31

C11

SW11

R11

R31C11 C32

C12

SW12

R12

R32C12

R13

C201µF

C13

DCIN

R81100Ω

T

R6010k

C62 100pF

C60 100pF

RT110k

T

R6110k

C61100pF

RT110k

AGND

AGND

BUS BAR

BUS BAR



HV to AGND ............................................................ -0.3 to +80VDCIN, SWn, VBLKP,

Cn to AGND ........................... -0.3V to min (VHV + 0.3V, 72V)Cn to Cn-1 ..............................................................-72V to +72VSWn to SWn-1.........................................................-0.3V to +9VVAA to AGND........................................................... -0.3v to +4VVDDL1 to GNDL1 .....................................................-0.3V to +4VVDDL2 to GNDL2 .....................................................-0.3V to +6VVDDL3 to GNDL3 .....................................................-0.3V to +6VVAA to VDDL1, VDDL2, VDDL3 ..............................-0.3V to +0.3VAGND to GNDL1, GNDL2, GNDL3 ......................-0.3V to +0.3VAUXIN1, AUXIN2, THRM to AGND ............. -0.3V to VAA + 0.3VSHDNL to AGND ........................................-0.3 to VDCIN + 0.3VCTG to AGND ..........................................................-0.3V to +6VRXLP, RXLN, RXUP, RXUN to AGND ....................-30V to +30VTXLP, TXLN to GNDL2 ............................................-0.3V to +6VTXUP, TXUN to GNDL3 ..........................................-0.3V to +6V

CPP to AGND ....................................... VDCIN - 1V to VHV + 1VCPN to AGND.......................................... -0.3V to VDCIN + 0.3VGPIO0, GPIO1, GPIO2,

GPIO3 to GNDL1................................. -0.3V to VDDL1 + 0.3VMaximum Continuous Current

into Any Pin (Note 1) ....................................................±20mAMaximum Continuous Current

into SWn Pin (Note 2).................................................±650mAMaximum Average Power for

ESD Diodes (Note 3) ................................................ 14.4W/√τPackage Continuous Power (Note 4) ............................2000mWPackage Junction to Ambient Thermal Resistance, θJA ......40°C/W Operating Temperature Range ......................... -40°C to +105°CStorage Temperature Range ............................ -55°C to +150°CJunction Temperature (continuous) ................................... 150°CSoldering Lead Temperature (10s, max) ........................... 300°C

(VDCIN = +48V, TA = TMIN to TMAX, unless otherwise noted, where TMIN = -40°C and TMAX = +105°C. Typical values are at TA = +25°C. Operation is with the recommended application circuit.) (Note 5)

Note 1: Balancing switches disabled.Note 2: One balancing switch enabled, 60s maximum.Note 3: Average power for time period τ where τ is the time constant (in µs) of the transient diode current during hot-plug event. For,

example, if τ is 330µs, the maximum average power is 0.793W. Peak current must never exceed 2A. Actual average power during hot-plug must be calculated from the diode current waveform for the application circuit and compared to the maximum rating.

Note 4: Multilayer board. For TA > 70ºC derate 25mW/°C.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSPOWER REQUIREMENTSSupply Voltage VDCIN 9 65 V

DCIN Current, Shutdown Mode IDCSHDN VSHDNL= 0V 0.1 2 µA

DCIN Current, Standby Mode (Note 16) IDCSTBY

VSHDNL > 1.8V, UART in idle mode, not in acquisition mode, BALSWEN, CTSTEN = 0000h

1.4 2.0 2.6 mA

DCIN Current, Acquisition Mode (Note 16) IDCMEAS

MEASUREEN = 0FFFh,acquisition mode 3.5 5.4 8.5 mA

Incremental DCIN Current, Communication Mode(Note 16)

IDCCOMM

Baud rate = 2Mb/s (0% idle time preambles mode), 200pF load on TXUP, 200pF on TXUN, TXL not active, not in acquisition mode, BALSWEN, CTSTEN = 0000h

1.5 3 mA

HV Current, Acquisition Mode IHVMEASAcquisition mode, MEASUREEN = 0FFFh, VHV = VDCIN + 5.5V 0.9 1.1 1.3 mA




Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Incremental HV Current, Cell-Balancing Mode IHVBAL

VHV = VDCIN + 5.5V, n balancing switches enabled

(n+1) x 5

(n+1) x 15.5

(n+1) x 26 µA

CELL VOLTAGE INPUTS (Cn, VBLKP)

Differential Input Range(Note 11) VCELLn

Unipolar mode 0.2 4.8 V

Bipolar mode -2.3 +2.3 V

Common-Mode Input Range VCnCM Not connected to SWn inputs 0 65 V

Input Leakage Current ILKG_CnNot in acquisition mode, VCn = 65V -200 ±10 +200 nA

VBLKP Input Resistance RVBLKP VBLKP = VDCIN = 57.6V 4.5 10 20 MΩ

HVMUX Switch Resistance RHVMUX CTSTDAC[3:0] = Fh 1.7 3.3 5 kΩ

CELL-BALANCING INPUTS (SWn)

Leakage Current ILKG_SWVSW0 = 0V, VSWn = 5V, VSWn-1 = 0V -1 +1 µA

Resistance, SWn to SWn-1 RSW BALSWEN[n-1] = 1, ISWn = 100mA 0.2 0.35 0.6 Ω

Maximum Allowed Balancing Current (Note 15) IBAL_MAX

TJ = 105°C, 25% average duty cycle per switch 650 mA

AUXILIARY INPUTS (AUXIN1, AUXIN2)

Input Voltage Range VAUXIN 0 VTHRM V

Input Leakage Current ILKG_AUXNot in acquisition mode, VAUXINn = 1.65V -400 10 +400 nA

THRM OUTPUT

Switch Resistance,VAA to THRM RTHRM 25 70 Ω

Leakage Current ILKG_THRM VTHRM = 3.3V -1 1 µA

MEASUREMENT ACCURACY

Total Measurement Error, HVMUX Inputs(Note 12)

VCELLnERR

Unipolar mode, VCELLn = 3.6V±2

mV

Bipolar mode, VCELLn = 1.1V

Unipolar mode0.2V ≤ VCELLn ≤ 4.3V,0°C ≤ TA ≤ 45°C

-5 ±3.6 +5

Unipolar mode, 0.2V ≤ VCELLn ≤ 4.8V

-10 +10Bipolar mode, -2.3V ≤ VCELLn ≤ 2.3V, SWn inputs not connected






Total Measurement Error, ALTMUX Inputs(Note 12)

VSWnERR

Unipolar mode, VCELL = 3.6V±2

mV

Bipolar mode, VCELLn = 1.1V

Unipolar mode, 0.2V ≤ VCELLn ≤ 4.8V

-10 +10Bipolar mode, 0V ≤ VCELLn ≤ 2.3V

Channel Noise (Note 7) VCELLNOISE No oversampling 1.1 mVRMS

Total Measurement Error, VBLKP Input VBLKPERR

9V ≤ VBLKP ≤ 57.6V, VDCIN = 57.6V, average of 64 acquisitions

-180 +180 mV

Offset Error, AUXINn Inputs VOS_AUX -3 +3 mV

Gain Error, AUXINn Inputs AV_AUX -0.3 -0.3 %

Total Measurement Error, Die Temperature (Note 7) TDIE_ERR

TJ = -40ºC to 105ºC, no oversampling -5 ±3 +5 °C

Differential Nonlinearity(Any Conversion) DNL ±1.0 LSbs

ADC Resolution 12 bits

Level-Shifting Amplifier Offset (Note 14) VOS_LSAMP DIAGSEL[2:0] = 011b -200 -10 +200 mV

SHDNL INPUT AND CHARGE PUMP

Input Low Voltage VIL_SHDNL 0.6 V

Input High Voltage VIH_SHDNL 1.8 V

Regulated Voltage VSHDNLIMITVDCIN ≥ 12V 8 9.5 12 V

VDCIN = 9V 6.7 V

Pulldown Resistance RFORCEPOR FORCEPOR = 1 2.5 4.7 8 kΩ

Input Leakage Current ILKG_SHDNLVSHDNL = 3.3V 1 µA

VSHDNL = 65V 40 75 µA

Charge-Pump Current (Note 10) ISHDNL

VSHDNL < VSHDNLIMIT, baud rate = 2Mbps 15 117 350 µA






GENERAL-PURPOSE I/O (GPIOn)

Input Low Voltage VIL_GPIO 0.8 V

Input High Voltage VIH_GPIO 2.4 V

Pulldown Resistance RGPIO GPIO[15:12] = 0h (input) 0.5 2 7.5 MΩ

Output Low Voltage VOL_GPIO ISINK = 3mA 0.4 V

Output High Voltage VOH_GPIO ISOURCE = 3mA VDDL1 - 0.4 V

REGULATOR

Output Voltage VAA 0 ≤ IAA < 10mA 3.2 3.3 3.4 V

Short-Circuit Current IAASC VAA shorted to AGND 10 20 70 mA

POR ThresholdVPORFALL VAA falling 2.85 2.95 3.02 V

VPORRISE VAA rising 3.0 3.1 V

POR Hysteresis VPORHYS 40 mV

Thermal-Shutdown Temperature (Note 7) TSHDN Temperature rising 145 °C

Thermal-ShutdownHysteresis (Note 7) THYS 15 °C

HV CHARGE PUMP

Output Voltage (VHV–VDCIN)VHV-DCIN

9V ≤ VDCIN ≤ 12V, ILOAD = 1.5mA 5 5.5 6V

12V ≤ VDCIN ≤ 65V, ILOAD = 3mA 5 5.5 6

Charge Pump Efficiency(Note 18) VDCIN = 57.6V 38 %

HV Headroom (VHV–VC12) VHVHDRM ALRTHVHDRM = 0 4.7 V

OSCILLATORS

32kHz Oscillator Frequency fOSC_32K 32.11 32.768 33.42 kHz

16MHz Oscillator Frequency fOSC_16M 15.68 16 16.32 MHz

DIAGNOSTIC TEST SOURCES

Cell Test-Source Current ITSTCn

CTSTDAC[3:0] = Fh, VCn < VAA – 1.4V, VAA = 3.3V 80 100 120

µA

CTSTDAC[3:0] = 6h, VCn < VAA – 1.4V, VAA = 3.3V 36 45 54

CTSTDAC[3:0] = 6h, VCn > VAGND + 1.4V -54 -45 -36

CTSTDAC[3:0] = Fh, VCn > VAGND + 1.4V -120 -100 -80






HVMUX Test-Source Current ITSTMUX

CTSTDAC[3:0] = Fh, VCn < VHV - 1.4V, VHV = 53.5V 40 50 60

µACTSTDAC[3:0] = 6h, VCn < VHV - 1.4V, VHV = 53.5V 18 22.5 27

AUXIN Test-Source Current ITSTAUXIN

CTSTDAC[3:0] = Fh, VAUXINn < VAA - 1.4V, VAA = 3.3V 80 100 120

µA

CTSTDAC[3:0] = 6h, VAUXINn < VAA - 1.4V, VAA = 3.3V 36 45 54

CTSTDAC[3:0] = 6h VAUXINn > VAGND + 1.4V -54 -45 -36

CTSTDAC[3:0] = Fh, VAUXINn > VAGND + 1.4V -120 -100 -80

DIAGNOSTIC REFERENCES

ALTREF Voltage (Note 14) VALTREF DIAGSEL[2:0] = 001b 1.23 1.242 1.254 V

ALTREF Temperature Coefficient (ΔVALTREF/ΔT) (Note 7)

AALTREF ±25 ppm/°C

PTAT Output Voltage (Note 7) VPTAT TJ = 120°C 1.2 V

PTAT Temperature Coefficient (ΔVPTAT/ΔT) (Note 7) AV_PTAT 3.07 mV/°C

PTAT Temperature Offset(Note 7) TOS_PTAT 0 °C

ALERTS

ALRTVDDLn Threshold VVDDL_OC VAA = 3.3V 3 3.15 3.25 V

ALRTGNDLn Threshold VGNDL_OC AGND = 0V 0.05 0.15 0.3 V

ALRTHVUV Threshold VHVUV VHV–VDCIN falling 3.8 4.1 4.25 V

ALRTHVOV Threshold VHVOV VHV–VDCIN rising 7 8.5 10 V

ALRTTEMP Threshold (Note 7) TALRTTEMP 115 120 125 °C

ALRTTEMP Hysteresis (Note 7) TALRTTEMPHYS 2 °C






UART OUTPUTS (TXLP, TXLN, TXUP, TXUN)

Output Low Voltage VOL ISINK = 20mA 0.4 V

Output High Voltage (TXLP, TXLN) VOH ISOURCE = 20mA VDDL2

- 0.4 V

Output High Voltage (TXUP, TXUN) VOH ISOURCE = 20mA VDDL3

- 0.4 V

Leakage Current ILKG_TX VTX = 1.5V -1 +1 µA

UART INPUTS (RXLP, RXLN, RXUP, RXUN)

Input Voltage Range VRX -25 +25 V

Receiver High-Comparator Threshold (Notes 9, 13) VCH

VDDL/2 - 0.4 VDDL/2 VDDL/2

+ 0.4 V

Receiver Zero-Crossing-Comparator Threshold (Note 9) VZC -0.4 0 +0.4 V

Receiver Low-Comparator Threshold (Notes 9, 13) VCL 75 mV

Receiver Comparator Hysteresis (Note 9) VHYS_RX VDDL/3 V

Receiver Common-Mode Voltage Bias (Notes 9, 13) VCM ±1.0 µA

Leakage Current ILKG_RX VRX = 1.5V 4 pF

Input Capacitance (RXLP, RXLN) CRXL 2 pF

Input Capacitance (RXUP, RXUN) CRXU 75 mV

UART TIMING

Bit Period (Note 17) tBIT

Baud rate = 2Mb/s 8

1/fOSC_16MBaud rate = 1Mb/s 16

Baud rate = 0.5Mb/s 32

RX Idle to START Setup Time (Notes 6, 7) tRXSTSU 0 1 tBIT

STOP Hold Time to Idle (Notes 6, 7) tSPHD 0.5 tBIT

RX Minimum Idle Time (STOP Bit to START Bit) (Note 6, 7) tRXIDLESPST 1 tBIT

RX Fall Time (Notes 7, 8) tFALL 0.5 tBIT

RX Rise Time (Notes 7, 8) tRISE 0.5 tBIT



Note 5: Unless otherwise noted, limits are 100% production tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.

Note 6: Maximum limited by application circuit.Note 7: Guaranteed by design and not production tested.Note 8: Fall time measured 90% to 10%; rise time measured 10% to 90%.Note 9: Differential signal (VRXP - VRXN) where VRXP and VRXN do not exceed a common-mode voltage range of ±25V.Note 10: ISHDNL measured with VSHDNL = 0.3V, STOP characters, zero idle time, VRX_PEAK = 3.3VNote 11: VCELLn = VCn - VCn-1, range over which measurement settling time and accuracy is guaranteed.Note 12: VCELLn = VCn - VCn-1, VCELLn = VCELLn-1, and VDCIN = 12 x VCELLn (9V min). No oversampling enabled

(OVSAMPL[2:0] = 0). Average of 64 acquisitions.Note 13: VDDL = VDDL2 for lower port and VDDL = VDDL3 for upper port.Note 14: As measured during specified diagnostic mode.Note 15: Not production tested. See the Cell-Balancing section for details on the maximum allowed balancing current. Duty cycle is

calculated for a 10-year device lifetime.Note 16: Acquisition mode (ADC conversions) is entered when the SCAN bit is set and ends when SCANDONE is set. With the

typical acquisition duty cycle very low, the average current (IDCIN) is much less than IDCMEAS. Total supply current during communication IDCIN = IDCCOMM + IDCSTBY.

Note 17: In daisy-chain applications, the bit time of the second stop bit may be less than specified to account for clock-rate variation and sampling error between devices.

Note 18: Charge-pump efficiency = ΔILOAD/ΔISUPPLY, where ILOAD is applied from HV to AGND, ΔILOAD = 5mA, and ΔISUPPLY = IDCIN (for ILOAD = 5mA) - IDCIN (for ILOAD = 0).



Typical Operating Characteristics

CHARGE PER PREAMBLE BYTEKEEP ALIVE OPERATION

MAX

1782

3A-B

DS

toc0

1

CHAR

GE T

RANS

FERE

D (N

ANO

COUL

OMBS

)

0.200

0.400

0.600

0.800

1.000

1.200

0.000

COMMUNICATIONS VOLTAGE (VOLTS Pk)

UART = 500kbps

UART = 1Mbps

UART = 2Mbps

3.102.60 3.60


Propagation Delay (RX Port to TX Port) tPROP 2.5 3 tBIT

Startup Time from SHNDL High and VAA = 0V, to RXUP/RXUN Valid

tSTARTUP 1 ms



Pin Configuration

49

34

32

TOP VIEW C12

C11

C10

SW12

C9SW11

C8SW10

C7

SW9

C6

SW8

C5

SW7

C3

C4

SW6

SW5

C2

C0

C1

SW4

SW3

SW2

SW1

N.C.

SW0

VBLK

P

AUXI

N2

THRM

AUXI

N1

DCIN

CPN

HVCPP

SHDNL

AGND

33

35

36

37

38

39

40

41

42

43

44

45

46

47

48

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50

GNDL1

VAA

GNDL3

VDDL3

GPIO

0

GPIO1

TXLPN.C.

TXLN

GNDL

2

VDDL

2

TXUP

TXUN

RXLP

RXLN

RXUP

RXUN

AGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

N.C.

AGND

GPIO3

GPIO2

VDDL1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

CTG

N.C.

N.C.

N.C.

MAX17823H

+

LQFP



Pin DescriptionPIN NAME FUNCTION DESCRIPTION

1 N.C. N.C. Not Connected. Connect to ground or leave unconnected.

2 AGND Ground Analog Ground. Connect to negative terminal of cell 1 and ground plane.

3 SHDNL Input

Shutdown Active-Low Input. Drive > 1.8V to enable operation, and drive < 0.6V to reset device and place in shutdown mode. +72V tolerant. If not driven externally, this input can be controlled solely through UART communication and software control. Bypass with a 1nF capacitor to AGND. For single-ended UART, SHDNL must be driven externally.


5 VAA Power 3.3V Regulator Output Used to Supply VDDL1, VDDL2, and VDDL3. Bypass with a 1µF capacitor to ground.

6 TXUN Output Negative Output for Upper-Port Transmitter. Driven between VDDL3 and GNDL3.

7 TXUP Output Positive Output for Upper-Port Transmitter. Driven between VDDL3 and GNDL3.

8 GNDL1 Ground Digital Ground. Connect to ground plane.

9 VDDL1 Power 3.3V Digital Supply. Connect externally to VAA and bypass with 0.47µF capacitor to GNDL1.

10 GNDL3 Ground Ground for Upper-Port Transmitter. Connect to ground plane.

11 VDDL Power 3.3V Supply for Upper-Port Transmitter. Connect externally to VAA and bypass with 0.47µF capacitor to GNDL3.

12 RXUN Input Negative Input for Upper-Port Receiver. Tolerates ±30V.

13 RXUP Input Positive Input for Upper-Port Receiver. Tolerates ±30V. Connect to ground for single-ended operation.

14 GPIO3 I/O General-Purpose I/O 3. Driven between VDDL1 and GNDL1. 2MΩ internal pulldown.






20 TXLP Output Positive output for lower port transmitter. Driven between VDDL2 and GNDL2.

21 TXLN Output Negative Output for Lower-Port Transmitter. Driven between VDDL2 and GNDL2.

22 VDDL2 Power 3.3V Supply for Lower-Port Transmitter. Connect externally to VAA and bypass with 0.47µF capacitor to GNDL2.

23 GNDL2 Ground Ground for Lower-Port Transmitter. Connect to ground plane.

24 RXLP Input Positive Input for Lower-Port Receiver. Tolerates ±30V. Connect to ground for single-ended operation.



Pin Description (continued)PIN NAME FUNCTION DESCRIPTION

25 RXLN Input Negative Input for Lower-Port Receiver. Tolerates ±30V.



28 CTG Input Reserved for Factory Use. Connect to ground.

29 AUXIN2 InputAuxiliary Voltage Input 2 to Measure External Temperature. Connect to a voltage-divider consisting of a 10kΩ pullup to THRM and 10kΩ NTC thermistor to ground. If not used, connect to the pullup only.

30 AUXIN1 InputAuxiliary Voltage Input 1 to Measure External Temperature. Connect to a voltage-divider consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to ground. If not used, connect to the pullup only.


32 THRM Power3.3V Switched Output Used to Supply the Voltage-Dividers for the Auxiliary Inputs. The output is enabled only during measurements, or as configured by THRMMODE[1:0]. This output can source up to 2mA.

33 SW0 Input Balance Input for Cell 1 Negative

34 C0 Input Voltage Input for Cell 1 Negative. Connect to AGND.

35 SW1 Input Balance Input for Cell 1 Positive (Cell 2 Negative)

36 C1 Input Voltage Input for Cell 1 Positive (Cell 2 Negative)
















Pin Description (continued)PIN NAME FUNCTION DESCRIPTION








57 SW12 Input Balance Input for Cell 12 Positive

58 C12 Input Voltage Input for Cell 12 Positive

59 VBLKP Input Block Voltage Positive Input. Internal 10MΩ pulldown during measurement.

60 NC NC Not Connected. Connect to ground or leave unconnected.

61 HV Power Decoupling-Capacitor Connection for the HV Charge Pump. VHV = VDCIN + 5.5V (typ). Bypass with a 50V, 4.7μF capacitor to DCIN.

62 DCIN PowerDC Supply for the Low-Voltage Regulator, HV Charge Pump, and SHDNL Charge Pump. Connect to a voltage source between 9V and 65V through a 100Ω series resistor. Bypass with a 100V, 2.2μF capacitor to ground.

63 CPP Power Positive Capacitor Connection for the HV Charge Pump. Connect a 100V, 0.1µF capacitor from CPP to CPN.

64 CPN Power Negative Capacitor Connection for the HV Charge Pump



Detailed DescriptionThe MAX17823H data-acquisition systems consist of the major blocks shown in Figure 1 and described in Table 1.

Table 1. System BlocksBLOCK DESCRIPTION

ADC Analog-to-digital converter. Uses a 12-bit successive-approximation register (SAR) with a reference voltage of 2.307V and supplied by VAA.

HVMUX 12-channel, high-voltage (65V) differential multiplexer for Cn inputs.

HV CHARGE PUMP High-voltage charge-pump supply (VDCIN + 5.5V) for the HVMUX, ALTMUX, BALSW, and LSAMP circuits, which must switch high-voltage signals. Supplied by DCIN.

LSAMP Level-shifting amplifier with a gain of 6/13. The result is that a 5V differential signal is attenuated to 2.307V, which is the reference voltage for the ADC.

LVMUX Multiplexes various low-voltage signals including the level-shifted signals and temperature signals to the ADC for subsequent A-to-D conversion.

ALTMUX 12-channel, high-voltage differential multiplexer for SWn inputs.

BALSW Cell-balancing switches.

LINREG 3.3V (VAA) linear regulator used to power the ADC and digital logic. Supplied by DCIN (9V to 65V).

REF 2.307V precision reference voltage for ADC and LINREG. Temperature compensated.

ALTREF 1.242V precision reference voltage used for diagnostics.

16MHz OSC 16MHz oscillator with 2% accuracy for clocking state-machines and UART timing.

32kHz OSC 32,768Hz oscillator for driving charge pumps and timers.

LOWER PORT Differential UART for communication with host or downstack devices. Auto-detects baud rates of 0.5Mbps, 1Mbps, or 2Mbps.

UPPER PORT Differential UART for communication with upstack devices.

CONTROL AND STATUS ALUs, control logic, and data registers

DIE TEMP A proportional-to-absolute-temperature (PTAT) voltage source used to measure the die temperature.



Figure 1. Functional Block Diagram

ADC+

-

LSAMP

CPPCPN

CONTROL AND

STATUS

LINREG

DCIN

+3.3VPOR

VAA

REF2.307V

16MHz OSC

32kHz OSC

+9V TO +65V

GPIO

1

GPIO

0

HV CHARGE

PUMP

HV

BALSW

SW2

ALTREF

AUXIN1AUXIN2

C12C11C10

C9C8C7C6C5C4C3C2C1C0

AGND

SW12

SW11

SW10

SW9

SW8

SW7

SW6

SW5

SW4

SW3

SW1

SW0

AGND

FAULT- DETECTION SUPPORT

CIRCUITRY

MAX17823HTHRM

HVVBLKP

ALTMUXHV

UPPER PORT

LOWER PORT

SHDNL

TXLPTXLN

RXUPRXUN

RXLPRXLN

TXUPTXUN

VAA

GPIO

3

GPIO

2

DIE TEMP

GNDL

V DDL

HVMUX

LVMUX



Figure 2. ESD Diodes

DCIN

HV

AGND

CPP

VDDL1

THRM, AUXINn

SW0

GNDL1

VAA

NOTES: 1. ALL DIODES ARE RATED FOR ESD CLAMPING CONDITIONS. THEY ARE NOT INTENDED TO ACCURATELY CLAMP DC VOLTAGE. 2. ALL DIODES HAVE A PARASITIC DIODE, FROM AGND TO THEIR CATHODE, THAT IS OMITTED FOR CLARITY. THESE PARASITIC DIODES HAVE THEIR ANODE AT AGND.

SHDNL, CPN

Cn, VBLKP

SWn VDDL2

TXLP, TXLN

GNDL2

VDDL3

TXUP, TXUN

GNDL3

RXUP, RXUN,RXLP, RXLN

GPIOn

CTG

SW12

SW11

SW1

HV VAA

MAX17823H



Figure 3. Analog Front-End

C10

C11

C12

C7

C6

C5

C9

C8

C4

C3

C2

C1

C0

-

+

AUXIN2

AUXIN1

AGND

ALTREF

LVMUX

HVMUX

12-BITADC

REFTHRM

HVMUX TEST SOURCES

INPUT TEST SOURCES

SOURCE C12

SOURCE C11

SOURCE C10

SOURCE C9

SOURCE C8

SOURCE C7

SOURCE C6

SOURCE C5

SOURCE C4

SOURCE C3

SOURCE C2

SOURCE C1

SOURCE C0

VBLKP

+

-

LSAMP

REF

VAA

DIE TEMPERATURE

EVEN

ODD

SOURCE AUX2

SOURCE AUX1

VBLKP/26



Data ConventionsRepresentation of data follows the conventions shown in Table 2. All registers are 16-bit words.

Data AcquisitionA data acquisition is composed of the distinct processes defined in Table 3 and controlled by various configuration registers described in this section. Configuration changes should be made prior to the acquisition in which the changes are to be effected.

Precision Internal Voltage ReferencesThe measurement system uses two precision, temper-ature-compensated voltage references. The references are completely internal to the device and do not require any external components. The primary voltage refer-

ence, or REF, is used to derive the linear regulator output voltage and to supply the ADC reference. An alternate, independent reference, ALTREF, can be used to verify the primary reference voltage as described in the Diagnostics section.

Measurement CalibrationThe acquisition system is calibrated at the factory and cannot be changed afterwards. The calibration param-eters are stored in a ROM consisting of 12 read-only registers, CAL0–CAL10 and CAL15. ROMCRC[8:0] is an 8-bit CRC value based on the calibration ROM and is stored in ID2[15:8] at the factory. ROMCRC[8:0] can be used to check the integrity of the calibration as described in the Diagnostics section.

Table 2. Numeric Conventions

Table 3. Data Acquisition Processes

DESCRIPTION CONVENTION EXAMPLE

Binary number 0b prefix 0b01100001 = 61h

Hexadecimal address 0x prefix 0x61

Hexadecimal data h suffix 61h

Register bit Register name [x] STATUS[15] = 1

Register field Field name [x:y] DA[4:0] = 0b01100 = 0Ch

Concatenated numbers xxxx, yyyy DA[4:0], 0b001 = 61h

PROCESS DESCRIPTION

Conversion The ADC samples a single input channel, converts it into a 12-bit binary value, and stores it in an ALU register.

Scan The ADC sequentially performs conversions on all enabled cell input channels.

Measurement cycle or Sample

The ADC performs two scans for the purpose of minimizing error. The conversions (two for each input channel) are averaged together to form a single 14-bit binary value called a measurement. Note: The auxiliary inputs are only scanned once to create the auxiliary measurements.

Acquisition or Acquisition mode

If oversampling is enabled, the ADC takes sequential measurements and averages them together to form one 14-bit binary value for each input channel sampled. If there is no oversampling, the acquisition is essentially a single measurement cycle. Note: The auxiliary inputs are never oversampled and are stored as 12-bit values.



Cell InputsUp to 12 voltage measurements can be sampled dif-ferentially from the 13 cell inputs. The differential signal VCELLn is defined as VCn - VCn-1 for n = 1 to 12. The cells to be measured are selected by MEASUREEN[11:0]. During the scan, each selected signal is multiplexed into the level-shifting amplifier (LSAMP) as shown in Figure 3. Since the common-mode range of the input signals is 0V to 65V, the signal must be level-shifted to the common-mode range of the amplifier. The amplifier has a gain of 6/13 so that a 5V differential signal will be attenuated to 2.307V, which is the ADC reference voltage.Once the signal is properly conditioned the ADC can start the conversion. The 12-bit conversion is stored in an ALU register where it can be averaged with subsequent con-versions. The ALU output is a 14-bit value and is ultimately stored in a 16-bit register with the two least-significant bits zero. Disabled channels result in a measurement value of 0000h. Unless stated otherwise, measurement values are assumed to be 14-bit values. The 16-bit register values can be converted to 14-bit values by dividing by 4 (and

vice-versa). To convert the measurement value in regis-ter CELLn to a voltage, convert the 14-bit hexadecimal value to a decimal value and then convert to voltage as follows: VCELLn = CELLn[15:2] x 5V/16384 = CELLn[15:2] x 305.176µV.

Input RangeThe input range in unipolar mode is nominally 0V to 5V. However, the ADC has reduced linearity at its range extents and so accuracy is specified for the input range 0.2V to 4.8V. Some applications may require specified accuracy below 0.2V or even below 0V. To this end, the bipolar mode (POLARITY = 1) has a nominal input range of -2.5V to 2.5V as shown in Table 4 with accuracy specified from -2.3V to 2.3V.The input range can effectively be extended from -2.5V to 5V by taking one bipolar measurement and one unipo-lar measurement. Any bipolar measurements over 2.3V should be replaced with the unipolar measurement.Note: Conversions for some diagnostic modes automati-cally use either bipolar or unipolar mode regardless of the POLARITY bit value.

Table 4. Input Range

Figure 4. VBLKP Measurement

-

+LV

MUX ADC

VREFVTHRMVBLKP

AGND

R2 = 384.5kΩ

R1 = 10MΩ - R2

VBLKP/26

CELL INPUT VOLTAGE CELLn[15:2] (14 BITS) CELLn[15:0] (16 BITS)BIPOLAR MODE UNIPOLAR MODE HEXADECIMAL DECIMAL

-2.5V 0V 0000h 0d 0000h

0V 2.5V 2000h 8192d 8000h

2.5V 5V 3FFFh 16383d FFFCh



Block Voltage InputThe VBLKP input (total module voltage) is selected for measurement by MEASUREEN[14]. The measurement is stored in the VBLOCK register with a full-scale value of 60V (3.662mV/bit). It can be compared to the sum of the cell voltages as a diagnostic. To pre-condition VBLKP for conversion it is voltage-divided by a factor of 26. The divid-er is disconnected by default to minimize power consump-tion. The divider is connected by setting MEASUREEN[15] (BLKCONNECT = 1) with sufficient settling time prior to the acquisition. For high acquisition rates, BLKCONNECT can remain enabled to reduce cycle time.

Auxiliary InputsThe AUXIN1 and AUXIN2 inputs can be used to measure external temperatures by enabling MEASUREEN[13:12]. These inputs have a common-mode input range of 0V to VAA. For these measurements, the ADC reference voltage is VTHRM which is switched from VAA as shown in Figure 5. The auxiliary inputs are not oversampled even if oversampling is enabled; they are measured only once and stored as 12-bit values in the AIN1 and AIN2 registers.To measure external temperature the auxiliary input is connected to a voltage divider consisting of a 10KΩ pullup to THRM and a 10KΩ NTC thermistor to ground as shown in Figure 6.

Figure 5. Auxiliary Measurement

Figure 6. Auxiliary Application Circuit

-

+

LVMUX ADC

VREF

THRM

CONVERSIONS IN PROGRESS

VAA

AUXIN1

AUXIN2

AGND

t t

AUXIN2

AUXIN1

AGND

THRM

R6110kΩ

R6010kΩ

RTH110kΩ

RTH210kΩ

C61100pF

C60100pF

C62100pF

THERMISTOR WIRE HARNESS



THRM OutputThe THRM output has 2 modes of operation, automatic and manual as shown in Table 5.The automatic mode minimizes power consumption, but after the THRM output is enabled, the AUXIN voltages must be allowed to settle before the conversion. Since the auxiliary inputs are the last inputs measured, the duration of the measurement cycle itself may provide sufficient settling time depending on what measurements are enabled and the time constants for the auxiliary input circuit. Up to 384µs of additional settling time, if required, can be configured by ACQCFG[5:0] as shown in Table 6 or by utilizing the manual mode. The ability to configure the settling time allows for a range of time constants to be considered in designing the auxiliary application circuit.

Computing TemperatureIn Figure 6, VAUXINn = VTHRM x RTH/(10KΩ+RTH) and this measurement is stored in the AINn register. The thermistor resistance can then be solved for as follows:

RTH = (VTHRM x 10KΩ)/(VTHRM - VAUXINn) where VTHRM = 3.3V nominally

The resistance of an NTC thermistor increases as the temperature decreases and is typically specified by its resistance R0 at T0 = +25°C = 298.15K and a mate-rial constant β (3400K typical). To the first order, the resistance RTH is at a temperature T in Kelvin can be computed as follows:

R = R0e(β(1/T-1/T0))

The temperature T of the thermistor (in °C) can then be calculated as follows:T (in °C) = (β/ln((RTH/10KΩ) + (β/298.15K)) – 273.15K

Temperature AlertsAuxiliary voltage measurements can be directly com-pared to pre-calculated voltages in the AINUT and AINOT registers that correspond to specific over- and under-temperature thresholds. When a measurement exceeds the AINUT or AINOT threshold level, the ALRTCOLD or ALRTHOT bits respectively are set in the STATUS regis-ter. An alert is cleared only by a new measurement that is within threshold.

Die Temperature MeasurementThe die temperature measurement allows the host to compute the device temperature (TDIE) as it relates to the acquisition accuracy and allows the device to auto-matically shut itself down when TDIE>145°C. The mea-surement employs a source whose voltage, VPTAT, is proportional to absolute temperature (PTAT) as shown in Figure 7. The VPTAT measurement is enabled by setting DIAGSEL[2:0] to 0b110 and the 14-bit measurement is stored in DIAG[15:2]. The die temperature measurement requires a settling time of 50us from the start of the mea-surement cycle until the diagnostic conversion. As long as 2 or more cell measurements are enabled, there will be sufficient settling time for this measurement. Refer to Figure 9 and Table 8 for a detailed view of this timing.The PTAT voltage is computed as follows:

VPTAT = (DIAG[15:2] / 16384d) x VREF Where VREF = 2.307V. The measured voltage can be converted into °C as follows:

TDIE (in °C) = (VPTAT/AV_PTAT) + TOS_PTAT - 273°CRefer to the Electrical Characteristics table for AV_PTAT and TOS_PTAT values.

Table 5. THRM Output Table 6. AINTIMEMODE ACQCFG[9:8] DESCRIPTION

Automatic00b THRM output enabled at the

beginning of the acquisition and disabled at the end of the acquisition.01b

Manual10b THRM output is enabled

11b THRM output is disabled

ACQCFG[5:0](AINTIME)

ADDITIONAL SETTLING TIME PER ENABLED AUXILIARY

CHANNEL = 6µs + (AINTIME x 6µs)

00h 6μs

01h 12μs

02h 18μs

… …

1Fh 384 μs



Die Temperature AlertThe ALRTTEMP bit is updated at the end of each mea-surement cycle for which DIAGSEL[2:0] = 0b110. If ALRTTEMP is set, it signifies that TDIE > TALRTTEMP or that the diagnostic measurement did not have sufficient settling time (< 50µs) and therefore may not be accurate. If ALRTTEMP is set, the host should consider the pos-sibility that the acquisition does not meet the expected accuracy specification, or that the die temperature mea-surement itself may be inaccurate due to insufficient set-tling time (< 2 cell measurements enabled).

Acquisition ModeThe host enters the acquisition mode by writing a logic-one to the SCAN bit in the SCANCTRL register. This write is actually an automatic strobe of the bit since SCAN always reads logic-zero. In daisy-chained devices, acqui-sitions in upstack devices are delayed by the propaga-tion delay, tPROP, of the command packet through each device. The acquisition is complete when the device sets the SCANDONE bit. The basic acquisition process is out-lined below with a detailed flowchart in Figure 8.1) Disable HV charge pump2) VBLKP conversion, if enabled3) All enabled cell conversions (first)

a. ascending order (1 through 12) if pyramid mode orb. descending order (12 through 1) if top-down mode

4) All enabled cell conversions (second)a. descending order (12 through 1)

5) VBLKP conversion (second), if enabled6) Diagnostic conversion (first), if enabled7) Diagnostic conversion (second) if enabled8) Enable HV charge pump for recovery period unless

a. OVSAMP[2:0] = 0 (no oversampling) orb. all oversample measurements are complete

9) Repeat steps 1 through 8 until all oversamples are done

10) All enabled auxiliary conversions, ascending order (AUXIN1, AUXIN2)

11) Set SCANDONE bit

OversamplingOversampling mode performs multiple measurement cycles in a single acquisition and averages the samples in the ALU to reduce the measurement noise and effectively increase the resolution of each measurement result. In oversampling mode, acquisition times are proportional to the number of oversamples as shown in Table 8. The number of overs-amples can be configured from 4 to 128 by OVSAMPL[2:0] as shown in Table 7. The AUXIN measurements are never oversampled, even in oversampling mode.To add n bits of measurement resolution requires at least 22n oversamples. Since the ADC resolution is 12 bits, 13-bit resolution requires at least 4 oversamples and to achieve the maximum 14-bit resolution requires at least 16 oversamples. Therefore with no oversampling, only the higher 12-bits of the measurement are statistically significant and with 4 or 8 oversamples, only the higher 13 bits are statistically significant. Taking more than 16 oversamples further reduces the measurement variation.Of course with no oversampling, measurements can be averaged externally to achieve increased resolution but at a higher computational cost for the host.

Acquisition Watchdog TimeoutIf the acquisition does not finish within a predetermined time interval, the SCANTIMEOUT bit is set, the ADC logic is reset, the ALU registers are cleared, and the measure-ment data registers are also cleared. In double-buffer mode (DBLBUF = 1), the data registers are not cleared, however, once data is moved from the ALU registers to the data registers, either automatically or manually (with the DATAMOVE bit), then data registers are cleared as a consequence of the ALU register having been cleared. The acquisition watchdog timeout interval depends on the oversampling configuration as shown in Table 7.

Figure 7. Die Temperature Measurement

-

+LVMUX ADC

VREFVTHRM

+

-

AGND

ALRTTEMP

VPTAT

1.230V



Table 7. Oversampling

Figure 8. Acquisition Mode Flowchart

STANDBY MODE

SCAN BIT SET?NO

ENABLE HV CHARGE PUMP

FOR 100.3µs

PERFORM MEASUREMENT SCANS FOR VBLKP, CELLn,

DIAG PER MEASUREEN

DBLBUF SET?

YES

CLEAR ALL ALU REGISTERS

MOVE ALU DATA TO DATA REGISTERS;

SET DATARDY = 1

YES

NO

ALL SAMPLES DONE? NO

YES

COMPARE MEASUREMENTS TO THRESHOLDS AND

UPDATE ALERTS

DISABLE DATAMOVE

DBLBUF SET?YES

NO

MOVE ALU DATA TO DATA REGISTERS; SET DATARDY = 1

SET SCANDONE, UNBLOCK DATAMOVE

STANDBY MODE

ENABLE HV CHARGE PUMP

SET ADC STATE-MACHINE TIMEOUT PERIOD

LATCH-ACQUISITION CONFIGURATION; DISABLE

HV CHARGE PUMP

CONVERT AUXINn INPUTS IF ENABLED; USE AINCFG

SETTLING TIME

COMPARE AUXINn MEASUREMENT TO

THRESHOLDS, UPDATE ALERTS

OVSAMPL[2:0] OVERSAMPLES THEORETICAL RESOLUTION ACQUISITION WATCHDOG TIMEOUT000b (default) 0 12 bits 1.10ms

001b 4 13 bits 2.08ms010b 8 13 bits 3.36ms011b 16 14 bits 5.92ms100b 32 14 bits 10.99ms101b 64 14 bits 21.18ms110b 128 14 bits 41.56ms111b 128 14 bits 41.56ms



Scan ModesThe cell, block, and diagnostic measurement cycle con-sists of two conversion phases. In each phase, the ADC scans through the enabled input channels. There are two scan modes configured by the SCANMODE bit. If SCANMODE = 0, the mode is pyramid mode as shown in Figure 9. If SCANMODE = 1, the mode is top-down mode. In pyramid mode, the ADC scans first ascending and then descending. In top-down mode, the ADC scans descend-ing in both phases. In the second scan, the amplifier inputs are inverted to effectively chop out any offset and

reference-induced errors. The two conversions are then offset corrected and averaged in the ALU.After the cell and block scans are complete, the diag-nostic conversions are made, if enabled, and finally, the auxiliary inputs, if enabled, are converted. The auxiliary inputs are measured using a single conversion and stored in the AIN1 and AIN2 registers. Any extra settling time, if configured by AINCFG[5:0], is implemented just before the conversion for each AUXIN channel and so if both inputs are enabled, the extra settling time occurs twice.

Figure 9. Acquisition, OVSAMP[2:0] = 0h and SCANMODE = 0

Figure 10. Acquisition, OVSAMP[2:0] > 0 and SCANMODE = 0

C1+

C2+

C3+

C4+

C5+

C6+

C7+

C8+

C9+

C10+

C11+

C12+

C1-

C2-

C3-

C4-

C5-

C6-

C7-

C8-

C9-

C10-

C11-

C12-

SAMPLING POINTDELAY TIME TO SWITCH

REF AMP TO CHOP

SAMPLE 1

BLK+

BLK-

DIA

G+

DIA

G- C1+

C2+

C3+

C4+

C5+

C6+

C7+

C8+

C9+

C10+

C11+

C12+

C1-

C2-

C3-

C4-

C5-

C6-

C7-

C8-

C9-

C10-

C11-

C12-

SAMPLING POINT

BLK+

BLK-

DIA

G+

DIA

G-

DELAY TIME TO SWITCH REF AMP TO CHOP

PUMP TO REFRESH HV

SAMPLE 2

SAMPLE n

100.3µs



Acquisition TimeThe total acquisition time can calculated by summing all the required processes as shown in Table 8 and Table 9. There is one measurement cycle per oversample.

Measurement Data TransferBy default, all ALU data is automatically transferred to the data registers (CELLn, VBLOCK, AIN1, AIN2, DIAG,

MINMAXCELL and TOTAL) at the end of each acquisi-tion. The transfer occurs in parallel, that is, all data regis-ters are loaded at the same time. When this occurs, the DATARDY bit is set and the host can read out the data. In the simplest, sequential approach, the host will initiate the acquisition by setting SCAN, wait for the acquisition to complete (SCANDONE = 1), read the data registers, and then repeat the cycle.

Table 8. Acquisition Time

Table 9. Acquisition Time Examples (with AINCFG[5:0] = 00h)

PROCESS TIME (ΜS) CONDITION FREQUENCY

Initialization 13 Always Once per acquisition

VBLKP measurement 27 If VBLKP is enabled

Every measurement cycle

Cell scan setup12.5 If cell input(s) enabled & VBLKP enabled

20 If cell input(s) enabled & VBLKP disabled

Cell scans 9 x n For n = # of enabled cell inputs

Diagnostic measurement(if enabled)

11.4 If zero-scale ADC output diagnostic enabled

11.4 If full-scale ADC output diagnostic enabled

86.2 If VALTREF diagnostic enabled

22.9 If any other diagnostic mode enabled

AUXIN measurement(if enabled)

10If AUXIN1 is enabled

Once per acquisition6µs x AINCFG[5:0]

10If AUXIN2 is enabled

6µs x AINCFG[5:0]

HV recovery (if oversampling enabled)

100.3 x m For m = # of oversamples After every measurement cycle except last

ENABLED MEASUREMENTS NO OVERSAMPLING 4 OVERSAMPLES 8 OVERSAMPLES

12 cells 141.0µs 825.9µs 1739.1µs

12 cells, VBLKP 160.5µs 903.9µs 1895.1µs

12 cells, AUXIN1&2 161.0µs 845.9µs 1759.1µs

12 cells, VBLKP, AUXIN1&2 180.5µs 923.9µs 1915.1µs

12 cells, VBLKP, die temperature, AUXIN1&2 203.4µs 1015.5µs 2098.3µs



Double-buffer ModeThe double-buffer mode (DBLBUFEN = 1) enables reduced cycle times by allowing the host to read out data registers during the acquisition mode. In this mode, the automatic transfer of measurement results from the ALU to the data registers is delayed until the start of the next acquisition. This delay allows the host to start reading out the first acquisition data while the second acquisition is taking place and to finish reading out the first acquisi-tion even as the second acquisition completes. The host can then start a new acquisition and repeat the cycle.

If the first acquisition data is needed before starting the second acquisition, the host can perform a manual data transfer by setting DATAMOVE. The manual transfer can-not occur in acquisition mode so the host may first verify that SCANDONE = 1. Flowcharts for operation of double-buffer mode are shown in Figure 12 and Figure 13. Note: An alternate double-buffer mode may be enabled (DBLBUFSEL = 1) that offers an even higher degree of pipelining but at the cost of increased complexity in the application code. Contact Maxim Applications for details regarding the alternate double-buffer mode.

Figure 11. Measurement Data Flow

ADC

BLOCK ALU

ALU1

ALUn

ALU12

ALU REGISTERS

VBLOCK REGISTER

CELL1 REGISTER

CELLn REGISTER

CELL12 REGISTER

DATA REGISTERS

DATAMOVE TRIGGER

-

+

12

12

ADCTSTEN

12

14

14

14

14

RESET

LOADADCTEST1A[11:0]12

ADCTEST1B[11:0]12

12

ADC_CHOP

ADCTEST2A[11:0]12

ADCTEST2B[11:0]12

OVSAMP_EVEN_ODD

UART COMMUNICATION

AIN2 REGISTER

AIN1 REGISTER

12

12

DIAG ALU DIAG REGISTER14



Figure 12. Double-Buffer Mode DATAMOVE

Figure 13. Double-Buffer Mode Register Read

MAX178xx COMMIDLE; DBLBUF=1

READSCANDONE

SET?

DATARDY = 0

WRITESCANDONE = 0DATAMOVE = 1

READDATARDY = 1

DATAMOVE = 0?

WRITEDATARDY = 0

READ ALL USERMEASUREMENT

REGISTERS

DATARDY = 0?

MAX178xx COMMIDLE

PROCESS EXISTINGUSER REGISTER DATA

FIRST

FAULT CONDITION;RETRY; POSSIBLE

SCAN IN PROGRESS

FAULT CONDITION;NEW DATA SHOULDNOT BE AVAILBLE

NO

YES

YES

YES

NO

NO

NO

YES

MAX178xx COMMIDLE; DBLBUF = 1

READSCANDONE

SET?

DATARDY = 0

WRITESCANDONE = 0

READ ALL USERMEASUREMENT

REGISTERS

MAX178xx COMMIDLE

PROCESS EXISTINGUSER REGISTER DATA

FIRST

FAULT CONDITION;NEW DATA SHOULDNOT BE AVAILABLE

FAULT CONDITION;DATA SHOULD BE

AVAILBLENO

YES

YES

NO

NO

NO

YES

WRITE SCAN = 1 TOSTART SCAN

DATARDY = 1?

WRITEDATARDY = 0

DATARDY = 0?

YES



Measurement AlertsAfter the measurement cycle, the ALU compares the enabled measurements to the various configured thresh-olds (see Table 10), and sets the alert bits before the ALU data is transferred to the data registers. In oversampling mode, the alert status is updated after the last over-sample. The alerts are updated whether or not the data is moved from the ALU registers to the data registers and are only updated for those measurements enabled in the MEASUREEN register.

Voltage AlertsUse the ALRTOVEN and ALRTUVEN registers to enable voltage alerts for the cell and auxiliary inputs. If a cell voltage alert is enabled, the cell input voltage is compared against the programmable overvoltage and undervoltage thresholds after every acquisition as shown in Figure 14. Separate thresholds for setting the alert and for clearing the alert provide hysteresis. Configure the set thresholds for cell undervoltage (VUVTHSET) and over-voltage (VOVTHSET) using the OVTHSET and UVTHSET registers. Configure the clear thresholds for cell undervolt-age (VUVTHCLR) and cell overvoltage (VOVTHCLR) using the OVTHCLR and UVTHCLR registers.Alert flags in the ALRTOVCELL register are set, if enabled, when the acquired cell voltage is over VOVTHSET. Alerts in the ALRTUVCELL register are set, if enabled, when the acquired cell voltage is under VUVTHSET. The alerts are cleared when the cell voltage moves in the opposite direction and crosses the clear threshold. The voltage

must cross the threshold; if it is equal to a threshold, the alert flag does not change. Therefore, setting the overvoltage-set threshold to full scale, or setting the undervoltage-set threshold to zero scale, effectively disables voltage alerts.The ALRTOV and ALRTUV bits in the STATUS register are set when any alert flag is set in the ALRTOVCELL or ALRTUVCELL registers, respectively. ALRTCELLn is the logical OR of ALROVCELLn and ALRTUVCELLn.

Cell MismatchEnable the mismatch alert to signal when the minimum and maximum cell voltages differ by more than a specified voltage. The MSMTCH register sets the 14-bit threshold (VMSMTCH) for the mismatch alert (ALRTMSMTCH). Whenever VMAX - VMIN > VMSMTCH, then ALRTMSMTCH = 1. The alert bit is cleared when a new acquisition does not exceed the threshold condition. To disable the alert, write FFCH to the MSMTCH register (default value).

Cell StatisticsThe cell numbers with the lowest and highest voltages are stored in the MINMAXCELL register. When multiple cells have the same minimum or same maximum volt-age, only the highest cell position having that voltage is reported. The sum of all enabled cell voltages is stored in the TOTAL register as a 16-bit value. For acquisitions with no enabled cell inputs, the MINMAXCELL and TOTAL registers are not updated.

Table 10. Measurement AlertsDESCRIPTION CONDITION OR RESULT ALERT BIT LOCATION

Cell overvoltage (OV) VCn - VCn-1 > VVOVTHSET ALRTOV, ALRTOVn STATUS, ALRTOVCELL

Cell undervoltage (UV) VCn - VCn-1 < VUVTHSET ALRTUV, ALRTUVn STATUS, ALRTUVCELL

Cell Mismatch VMAX - VMIN > VMSMTCH ALRTMSMTCH STATUS

Cell with minimum voltage n where VCELLn = VMIN None MINMAXCELL

Cell with maximum voltage n where VCELLn = VMAX None MINMAXCELL

Total of all cell voltages Σ VCELLn for n = 1 to 12 None TOTAL

AUXINx overvoltage (undertemperature) VAUXINx > VAINUT ALTRTCOLD, ALRTOVAINx STATUS, ALRTOVCELL

AUXINx undervoltage (overtemperature) VAUXINx < VAINOT ALRTHOT, ALRTUVAINx STATUS, ALRTUVCELL



Temperature AlertsTemperature alerts, if enabled, occur when the acquired AUXINn input voltages fall outside the thresholds configured by the AINOT and AINUT registers. Unlike the cell-voltage alerts, the temperature thresholds do not have the hysteresis afforded by separate set and clear thresholds.

Cell BalancingCell-Balancing SwitchesCell balancing can be performed using any of the 12 internal cell-balancing switches to discharge cells. The cell-balancing current is limited by the external balancing resistors and the internal balancing-switch resistance (RSW). Enabling adjacent balancing switch-es simultaneously may increase the balancing current significantly, so care must be taken to not exceed the device’s maximum operating conditions. Fault detection is described in the Diagnostics section.

Figure 14. Cell Voltage Alert Thresholds

Figure 15. Internal Cell Balancing

OVERVOLTAGE SET AND CLEAR THRESHOLDSPOR DEFAULT VALUE (+5.0V)

OVERVOLTAGE SET THRESHOLD (OVTHRSET)

OVERVOLTAGE CLEAR THRESHOLD (OVTHRCLR)

UNDERVOLTAGE SET THRESHOLD (UVTHRSET)

UNDERVOLTAGE CLEAR THRESHOLD (UVTHCLR)

UNDERVOLTAGE SET AND CLEAR THRESHOLDSPOR DEFAULT VALUE (+0.0V)

CELLn VOLTAGE

OVERVOLTAGE ALERT SET

OVERVOLTAGE ALERT CLEARED

UNDERVOLTAGE ALERT SET

UNDERVOLTAGE ALERT CLEARED

t

V

BALANCING SWITCH (n)

SWn

SWn-1

Cn

AGND

Cn-1RFILTER

RBALANCE

CFILTER

CELLn

RFILTER

RBALANCE

CFILTER

RBALANCEFILTER

TO CELLn+1

SENSE WIRE

SENSE WIRE

HV

TO ALTMUX

TO ALTMUX

BALSWEN

TO HVMUX

TO HVMUX

TO CELLn+1



Maximum Cell-Balancing CurrentThe maximum balancing current is limited by package power dissipation, average die temperature, average duty cycle of the switch, and the number of switches conduct-ing current at any one time.The power dissipation must not exceed the absolute maximum rating of the package, nor should the die tem-perature go outside the range specified for the desired level of measurement accuracy. Higher die temperatures and higher average duty cycles increase the probability of internal electromigration, so the maximum balancing current is lowered accordingly for an assumed 10-year device lifetime, as shown in Table 11.

Cell-Balancing WatchdogEven if the host fails to disable the cell-balancing mode, the cell-balancing watchdog can automatically disable the cell-balancing switches, regardless of the BALSWEN configu-ration. The cell-balancing watchdog does not modify the

contents of the BALSWEN register. Use the WATCHDOG register to configure the timeout value from 1s to 3840s (64min), as shown in Table 12. The pre-divider configura-tion, CBPDIV[2:0], effectively sets the rate at which the CBTIMER[3:0] counts down (see Figure 16).The host should periodically update CBTIMER to ensure that it does not count down to zero. If the countdown timer is allowed to reach zero, the cell-balancing switches are disabled until the timer is either disabled or refreshed by writing a non-zero value.To allow timed balancing with no host interaction, the GPIO3 pin is configured to output a logic-high level while the timer is counting using the GPIO3TMR configuration bit of the GPIO register. An external diode is connected from GPIO3 to SHDNL to prevent shutdown while the timer is counting. Once the timer expires, the device shuts down. The host may intervene prior to the timer expiring to keep the device active and to reconfigure the device.

Table 11. Maximum Allowed Balancing Current per Switch

Table 12. Cell-Balancing Watchdog Configuration

Figure 16. Cell-Balancing Watchdog

CBPDIV32.768kHz CBTIMER

TIMER ZERO FLAG

BIT 0BIT 1BIT 2BIT 3CBPDIV1 CBPDIV0

BALSWEN

CELL BALANCING SWITCH ENABLECBTIMER ENABLE

CBPDIV2

AVERAGE LIFETIME DUTY CYCLE (10 YEARS) TDIE = 85°C TDIE = 105°C TDIE = 125°C

15% 650mA 650mA 650mA20% 650mA 650mA 650mA25% 650mA 650mA 650mA

CBPDIV[2:0] TIMER LSB PERIODRANGE OF CBTIMER[3:0]

MINIMUM MAXIMUM000b Timer Disabled Timer Disabled001b 1s 1s 15s010b 4s 4s 60s011b 16s 16s 240s100b 64s 64s 960s101b 128s 128s 1920s110b 256s 256s 3840s



Emergency-Discharge ModeThe emergency-discharge mode performs cell balanc-ing in a controlled manner so that the cells can be dis-charged to a safe level in the event of an emergency. The BALSWDCHG and DEVCFG2 registers provide control for this mode. A timeout value for the mode is configured by DISCHGTIME[7:0] as shown in Table 13.The emergency-discharge mode is activated by setting the EMGCYDCHG bit with DCHGTIME[7:0] ≠ 00h. In emergency-discharge mode the following occurs:1) The CBTIMER[3:0] is cleared to prevent the cell-

balancing watchdog from disabling the cell-balancing.2) Cell-balancing switches are controlled by BALSWD-

CHG, not BALSWEN.3) The discharge timer starts to countdown.4) The read-only counter DCHGCNTR[3:0] increments

at a 2Hz rate with periodic roll-over at Fh. The host can read this counter periodically to confirm that the mode is active.

5) The GPIO3 pin is driven high while the countdown is active.

The emergency-discharge mode alternates between a 1-minute discharge cycle for odd cells and a 1-minute discharge cycle for even cells. There is a 62.5ms minimum off time at the end of each discharge cycle to ensure no overlap between even and odd discharge cycles. The duty cycle of each discharge cycle can be configured by DCHGWIN[2:0], as shown in Table 13. By clearing EMGCYDCHG, the emergency-discharge mode terminates and the following occurs:1) The discharge timer is reset.2) Control of the cell-balancing switches reverts to the

BALSWEN register.3) Control of GPIO3 reverts to the GPIO register.The emergency-discharge mode also terminates if DCHGTIME[7:0] = 0h, or the discharge time has reached the configured timeout.To prevent the emergency-discharge mode from terminat-ing prematurely due to a device shutdown (which could occur due to an extended lapse in host communications), connect an external diode from GPIO3 to SHDNL to keep SHDNL high while the timer is counting.

Table 13. Emergency-Discharge ModeFUNCTION REGISTER FIELD CONFIGURATION BEHAVIOR

Duty cycle DCHGWIN[2:0]7.5s/bit

0h Switches on for 7.5s, off for 52.5s

1h Switches on for 15s, off for 45s

… …

7h Switches on for 59.94s, off for 62.5ms

Timeout DCHGTIME[7:0]2 hours/bit

00h Discharge mode disabled

01h Discharge mode disabled after 4 hours

02h Discharge mode disabled after 6 hours

… …

FFh Discharge mode disabled after 512 hours



Low-Voltage RegulatorAn internal linear regulator supplies low-voltage power (VAA) for the ADC and digital logic. The regulator is disabled when SHDNL is active-low or when the die tem-perature (TDIE) exceeds 145°C, as shown in Table 14. Once VAA decays below 2.95V (typ), an internal power-on reset (POR) is generated (see Figure 22). This event can

be detected with the ALRTRST bit, as shown in Table 15. After a thermal shutdown, the regulator is not enabled until TDIE < 130°C due to hysteresis.The low-voltage regulator is continuously monitored for undervoltage, as described in Table 15.

Figure 17. Low-Voltage Regulator

Table 14. Low-Voltage Regulator Table 15. Low-Voltage Regulator Diagnostic

REGULATOR ENABLE

DCIN

SHDNL

AGND

CDCIN

+

RDCIN

LINEAR REGULATOR

VAA

CVAA CSHDNL

TO SHDNL CHARGE PUMP

THERMAL SHUTDOWN

+-

INTERNAL POR

+-

3.0V

INPUT: DCIN

INPUT VOLTAGE: 9V to 65V

OUTPUT: VAA

OUTPUT VOLTAGE: 3.3V

DISABLE: VSHNDL < 0.6V or TDIE > 145°C

FAULT CONDITION ALERT LOCATION

VAA undervoltage VAA < 2.95V ALRTRST STATUS15



HV Charge PumpThe high-voltage multiplexers must be powered by a sup-ply higher than any monitored voltage. To this end, an internal charge pump draws power from the DCIN input to provide a high-voltage supply (VHV), which is regulated to VDCIN + 5.5V (nominal). When the charge pump achieves regulation, charge pumping stops until the voltage drops by 20mV. The charge pump is automatically disabled during shutdown and during the measurement cycle to eliminate charge-pump noise. The charge pump can also be disabled manually by setting the HVCPDIS bit in the DEVCFG2 register.If VHV - VDCIN drops below VHVUV, the HV undervoltage flag (ALRTHVUV) is set. If VHV drops too low relative to

the C12 input, there is insufficient headroom to guarantee that the HVMUX switch resistance is sufficiently low for an accurate acquisition of the channel. To properly identify this fault condition, if VHV - VC12 is too low during the acquisition, the HV headroom alert flag (ALRTHVHDRM) is set in the FMEA2 register. The HV undervoltage and HV headroom alert functions can be verified by dis-abling the HV charge pump (HVCPDIS = 1) and allowing VHV to decay while in acquisition mode. An overvoltage comparator disables the charge pump in the case where VHV - VDCIN exceeds 8.5V. This condition is indicated by the ALRTHVOV bit in the FMEA2 register. The ALRTHVOV alert does not necessarily indicate a condition that affects measurement accuracy. HV charge-pump diagnostics are summarized in Table 16.

Figure 18. HV Charge Pump

Table 16. HV Charge-Pump Diagnostics

DCIN

CPN

AGND

CPP

HV

CDCIN

CCP

15mA

+

CHV

SWITCH LOGIC+

-

5.5V

RDCIN

20mV HYSTERESIS

INTERNAL POR

+-

TO ALRTHVUV

+-

4.1V

32kHz

MEASURING DISABLE

DEVCFG2.HVCPDIS

DISABLE

HVOV

+- TO ALRTHVOV

HVOV

+-

8.5V

RHV

FAULT CONDITION ALERT BIT LOCATION

VHV undervoltage VHV - VDCIN < VHVUV ALRTHVUV FMEA1[3]

VHV overvoltage VHV - VDCIN > VHVOV ALRTHVOV FMEA2[0]

VHV low headroom VHV - VC12 < VHVHDRM (min.) ALRTHVHDRM FMEA2[2]



OscillatorsTwo factory-trimmed oscillators provide all timing require-ments: a 16MHz oscillator for the UART and control logic, and a 32.768kHz oscillator for HV charge pump and timers. A special diagnostic counter clocked by the 16MHz signal is employed to check the 32kHz oscilla-tor. Every two periods of the 32kHz clock, the counter is sampled. If the count varies more than 5% from the expected value the ALRTOSC1 bit is set, as shown in Table 17. A redundant alert bit (ALRTOSC2) increases the integrity level. If the 16MHz oscillator varies by more than 5%, communication errors will be indicated

Device ID NumberThe ID1[15:0] register together with ID2[7:0] contain a 24-bit manufacturing identification number, DEVID[23:0]. The ID combined with the manufacturing date provides a means of uniquely identifying each device. A device ID of zero is invalid.

Power-On and ShutdownApplications that remain connected continuously to the power source rely on the SHDNL input to shut down and reset the device. When VSHDNL < 0.6V, the regulator is disabled, the POR signal asserted, and the device goes into an ultra-low-power shutdown mode. When VSHDNL > 1.8V, POR is deasserted, the regulator enabled, and the device becomes fully operational in the standby mode.

Power-On MethodThe SHNDL input can be driven externally or it can be controlled using UART communication only. In differential mode, the signaling on the lower-port receiver drives an internal charge pump that charges up the external 1nF capacitor connected to the SHDNL input (see Figure 19). VSHDNL reaches 1.8V in 200µs (typ). The charge pump then self-regulates to VSHDNLIMIT and can maintain VSHDNL at a logic-one, even with the UART idle 98% of the time.

Table 17. Oscillator Diagnostics

Figure 19. SHDNL Charge Pump

RXLN

RXLP

C422nF 600V

C432nF 600V

C4015pF

C4115pF

R404.7kΩ

R42100kΩ

R43100kΩ

R414.7kΩ

GNDL

FROM DEVICE (n-1) TRANSMITTER CIRCUIT

SHDNLC441nF

(CSHDNL)

DCIN

10MΩFORCEPOR

TO RECEIVER

TO RECEIVER

FAULT CONDITION ALERT BIT LOCATION

32.768kHz oscillator 31.129kHz > fosc_32k > 34.406kHz ALRTOSC1 FMEA1[15]

32.768kHz oscillator 31.129kHz > fosc_32k > 34.406kHz ALRTOSC2 FMEA1[14]

16MHz oscillator 15MHz > fosc_32k > 17MHz ALRTMAN or ALRTPAR STATUS[4], or STATUS[2]



Power-On SequenceOnce VSHNDL > 1.8V, the regulator is enabled. After VAA reaches 3V (typ), the POR signal is deasserted, the oscillators enabled, and the HV charge pump enabled. Once the HV charge pump is stable, the logic is enabled. The device is fully operational (standby mode) within 1ms from the time communication is first received in the shutdown mode. The power-on sequence is shown in Figure 20.

Figure 20. Power-On Sequence

VOLTAGE APPLIED TO DCIN

DIE TEMP > 145°C

VAA < VPOR_RISING

REGULATOR DISABLED

32kHz OSCILLATOR ENABLED

CHECK DIE TEMPERATURE

CHECK VAA

CHARGE PUMP AND DIGITAL LOGIC

ENABLED

CHARGE PUMP SETTLED

470µsec DELAY

3ms DELAY

REGULATOR ENABLED

ALRTRST BIT SET

CHECK SHDN\

SHDN\ ACTIVE

POR CLEARED

REGULATOR DISABLED

DIE TEMP > 145°C SHDN\ ACTIVE

SHUTDOWNMODE

STANDBYMODE

YES YES



Shutdown ModeShutdown is performed by bringing VSHDNL < 0.6V. Table 18 summarizes the methods by which this can be achieved. The quickest shutdown can be achieved by driving SHDNL externally with a driver pulldown impedance not exceeding 1kΩ. If SHDNL is not driven externally, the host can discharge CSHDNL under software control by setting the FORCEPOR bit. This will enable a pulldown (4.7kΩ nominal) to discharge the capacitor with a 4.7µs time constant. The slowest method is for the host to simply cease communication. With the UART idle, there is no charge pumping and the capacitor discharges through an internal 10MΩ resistor with a 10ms time constant. If shutdown fast-er than 10ms is desired when power is disconnected from the device, a 200kΩ resistor can be connected externally from SHDNL to AGND to create a 200µs time constant.

If only a reset is required, the host can issue a soft-reset by setting the SPOR bit. This resets the device registers and disables high-voltage operation, but low-voltage operation remains enabled (the regulator is not disabled).Note: For single-ended communication, SHDNL must be driven externally since the charge-pump operation requires a differential signal.

Shutdown SequenceThe shutdown sequence and timing is shown in Figure 21, Figure 22, and Figure 23. The ALRTSHDNL status bit is set and the low-voltage regulator disabled as soon as VSHDNL < 0.6V. When the VAA and VDDL decoupling capacitors discharge below the POR thresh-old (2.95V typ), the device registers are reset and the HV charge pump is disabled. The device is then in an ultra-low-power state until VSHDNL > 1.8V.

Table 18. Shutdown Timing

Figure 21. Shutdown Sequence

POR ACTIVE

VAA > VPOR_RISING

POR INACTIVE

OSCILLATOR, CHARGE PUMP, DIGITAL LOGIC DISABLED

VAA < VPOR_FALLING

CHECK VAA

SHUTDOWN METHOD RPULLDOWN CSHDNL RC

1. Host drives SHDNL pin low 1kΩ External

1nF

1µs2. Host sets FORCEPOR bit 5kΩ Internal 5µs3. Disconnect DCIN 200kΩ External 200µs4. Host places UART in idle mode 10MΩ Internal 10,000µs



Figure 22. Power-On and Shutdown Timing (UART Control)

Figure 23. Shutdown Timing (Software Control)

RXLPRXLN

VSHDNL

VAA

POR

TXUPTXUN

VSHDNLIMIT

VIH

tRXRU-VAA

tVAARU-POR

tPORUP-TX

tVAAFD-POR

tRXFD-VAA

VIL

VPORRISEVPORFALL

VSHDNL

VAA

POR

tVAAFD-POR

tRXFD-VAA

VIL

FORCEPOR tFRPOR

RXLPRXLN

VPORFALL

VIH



UART InterfaceThe battery-management UART protocol allows up to 32 devices to be connected in daisy-chain fashion (see Figure 24). The host initiates all communication with the daisy-chain devices through a UART interface such as the MAX17841B. The data flow is always unidirectional from the host, up the daisy-chain (upstack) and then loops back down the daisy-chain (downstack) to the host (see Figure 24).

Each device first receives data at its lower RX port and immediately retransmits data from its upper TX port to the lower RX port of the next upstack device. The last device transmits data from its upper TX port directly into its upper RX port and then immediately retransmits the data from its lower TX port to the upper RX port of the next down-stack device. The protocol supports fixed baud rates of 2Mb/s, 1Mb/s, or 0.5Mb/s. The baud rate is set by the host and is automatically detected by the device.

Figure 24. UART Interface



UART PortsTwo UART ports are utilized, a lower port (RXL/TXL) and an upper port (RXU/TXU). Each port consists of a differ-ential line driver and differential line receiver. DC-blocking capacitors or transformers can be used to isolate daisy-chained devices that are operating at different common-mode voltages. During communication, the character encoding provides a balanced signal (50% duty cycle) that ensures charge neutrality on the isolation capacitors.

UART TransmitterWhen no data is being transmitted by the UART, the differential outputs must be driven to a common level to maintain a neutral charge difference between the AC-coupling capacitors or to avoid saturation of the isolation transformers. In the default idle mode (low-Z), the transmitter drives both outputs to a logic-low level to balance the charge on the capacitors; this also works well with transformer coupling. The high-Z idle mode (TXLHIZIDLE, TXUHIZIDLE = 1) places the TX pins in a high-Z state in idle mode, which may be desirable to mini-mize the effects of charging and discharging the isolation capacitors. The idle mode for the upper and lower ports can be controlled independently through the TXLHIZIDLE and TXUHIZIDLE configuration bits.

UART ReceiverThe UART receiver has a wide common-mode input range to tolerate harsh EMC conditions. It can be operated in differential mode or single-ended mode per Table 19. By default, the UART receivers are configured for differential mode. In single-ended mode, the RXP input is grounded and the RXN input receives inverse data as described in the Applications Information section (see Figure 64). In single-ended mode, the receiver input threshold is nega-tive so that a zero differential voltage (VRXP, VRXN = 0V) is considered to be a logic-one and a negative differential voltage (VRXN high) is a logic-zero.Figure 25. UART Transmitter

Figure 26. UART Receiver

TX[U,L][P,N]

VDDL[2,3]

TX[U,L]IDLEHIZ

DRIVE LOW

DRIVE HIGH

GNDL[2,3]

ESD CLAMP

(UARTSTATE=IDLE?)

ZERO CROSSING COMPARATOR

HIGH COMPARATOR

LOW COMPARATOR

1.18MΩ

41.6kΩ

41.6kΩ

+-

RXP

RXN

VCM = VDDL/3

1.18MΩ

DIGITAL CORE

+-+-

VDDL/60

VDDL/604pF

4pF

30kΩ

30kΩ

GNDL



UART RX ModesDuring the first preamble received after a reset, the receiver automatically detects if the received signal is single-ended and if so, places the receiver in single-ended mode; therefore, the device must be reset for any change in the RX-mode hardware configuration to be detected.The receiver mode is indicated by the ALRTCOMMSEL bit (for lower port) and ALRTCOMMSEU bit (for upper port) of the FMEA1 register, as shown in Table 19. If the RXP input is open circuit, the RX-mode detection places the UART in single-ended mode so the port can still oper-ate, albeit with reduced noise immunity. The host can diagnose this condition by checking ALRTCOMMSEL and ALRTCOMMSEU after any POR event. Any other faults result in communication errors.

UART LoopbackFor the last device in the stack, the data must be looped back from the upper transmitter to the upper receiver. This is known as loopback and can be configured externally (default) or internally.

External Loopback ModeExternal loopback mode (default) uses a two-wire cable to connect the upper transmitter (TXU) to the upper receiver (RXU). The external loopback has two advantages:1) It is quicker to determine device count for applications

where the host does not assume what the device count is.

2) It helps to match the supply current of the last device to that of the other daisy-chained devices (because the hardware configuration is identical).

Internal Loopback ModeInternal loopback mode (LASTLOOP = 1) routes the upper-port transmit data internally to the upper-port receiver. Any signal present on the upper-port receiver input pins is ignored in the internal loopback mode; therefore, when LASTLOOP is set, the write command that was forwarded to any upstack devices is interrupted in the downstack direction. The host should expect this and read the LASTLOOP bit to verify that the write was successful. If the MAX17841B interface is used, its receive buffer should be cleared before changing LASTLOOP, and cleared again after changing the loopback configuration because the communication was interrupted.Internal loopback mode is useful to diagnose the loca-tion of a daisy-chain signal break by enabling the internal loopback mode on the first device, checking communica-tion, then moving the loopback mode to the next device, and continuing up the stack until communication is lost.

Baud-Rate DetectionThe UART can operate at a baud rate of 2Mb/s (default), 1Mb/s, or 0.5Mb/s. The baud rate is controlled by the host and is automatically detected by the device when the first preamble character is received after reset. If the host changes the baud rate after reset, it must issue another reset (which can be done by setting the SPOR bit) and resend a minimum of 2 x n preambles (where n is the number of devices). The 2 x n preambles are necessary since the transmitter for the upper port will not transmit data until the lower-port receiver has detected the baud rate and likewise, the transmitter on the lower port will not transmit data until the upper-port receiver has detected the baud rate. A simple way to do this is for the host to start transmitting preambles and stop when a preamble has been received back at the host RX port.

Table 19. UART RX ModesRXP RXN ALRTCOMMSEn RX MODE

Connected to data Connected to inverse data 0 Differential mode (normal)

Grounded Connected to inverse data 1 Single-ended mode (normal)

Open circuit (fault) Connected to inverse data 1 Single-ended mode (low noise immunity)

Connected to data Open circuit (fault) 0 Differential mode (communication errors)



Battery-Management UART ProtocolThe battery-management UART protocol uses the following features to maximize the integrity of the communications:

All transmitted data bytes are Manchester-encoded, where each data bit is transmitted twice, with the second bit inverted (G.E. Thomas convention).

Every transmitted character contains 12 bits that include a start bit, a parity bit, and two stop bits.

Read/write packets contain a CRC-8 packet-error checking (PEC) byte

Each packet is framed by a preamble character and stop character.

Read packets contain a data-check byte for verifying the integrity of the transmission.

The protocol is also designed to minimize power-con-sumption by allowing slave devices to shut down if the

UART is idle for a specified period of time. The host must periodically transmit data to prevent shutdown unless the SHDNL input is driven externally.

Command PacketA command packet is defined as a sequence of UART characters originating at the host. Each packet starts with a preamble character, followed by data characters, and ending with a stop character (see Figure 27). After send-ing a packet, the host either goes into idle mode or sends another packet.

Preamble CharacterThe preamble is a framing character that signals the beginning of a command packet. It is transmitted as an unencoded 15h with a logic-one parity bit and a balanced duty cycle. If any bit(s) other than the stop bits deviate from the unique preamble sequence, the character is not interpreted as a valid preamble, but rather as a data character.

Figure 27. Command Packet

Figure 28. Preamble Character

PREAMBLE MESSAGE STOPIDLETXP-TXN IDLE

S 1 10 0 1 0 0 0 E=1 P POPTIONAL

IDLEOPTIONAL

IDLE

IDLE DISABLE

IDLE ENABLE



Data CharactersEach data character contains a single-nibble (4-bit) pay-load, so two characters must be transmitted for each byte of data. All data is transmitted least-significant bit, least-significant nibble, and least-significant byte first (see Figure 29). The data itself is Manchester-encoded, which means that each data bit is followed by its complement. If the UART detects a Manchester-encoding error in any received data character, it sets the ALRTMAN bit in the STATUS register.

The parity is even, which means that the parity bit’s value should always result in an even number of logic-one bits in the character. Given that the data is Manchester-encoded and there are two stop bits, the parity bit for data characters is always transmitted as a logic-zero. If the UART detects a parity error in any received data character, it sets the ALRTPAR bit in the STATUS register. Table 20 provides a list of data character descriptions.

Table 20. Data Characters

Figure 29. Data Characters

S 0 01 1 0 1 0 1 E=0 P POPTIONAL

IDLEOPTIONAL

IDLE

IDLE DISABLE

IDLE ENABLE

0 0 0 0

DATA NIBBLE = 0h

S 0 11 0 0 1 1 0 E=0 P POPTIONAL

IDLEOPTIONAL

IDLE

IDLE DISABLE

IDLE ENABLE

0 1 0 1

DATA NIBBLE = Ah

BIT NAME SYMBOL DESCRIPTION1 Start S First bit in character, always logic-zero2 Data0 Least-significant bit of data nibble (true)3 Data0/ Least-significant bit of data nibble (inverted)4 Data1 Data bit 1 (true)5 Data1/ Data bit 1 (inverted)6 Data2 Data bit 2 (true)7 Data2/ Data bit 2 (inverted)8 Data3 Most-significant bit of data nibble (true)9 Data3/ Most-significant bit of data nibble (inverted)

10 Parity E Always logic-zero (even parity)11 Stop P Always logic-one12 Stop P Last bit in character, always logic-one



Stop CharacterThe stop character is a framing character that signals the end of a command packet (see Figure 30). It is transmitted as an unencoded 54h with a logic-one parity bit and a balanced duty cycle.

UART Idle ModeIn the low-Z (default) idle mode, the transmitter outputs are both driven to 0V (see Figure 31). In the high-Z idle mode, the transmitter outputs are not driven by the UART. The MAX17841B interface automatically places its transmitter in idle mode immediately after each command packet and remains in idle mode until either the next

command packet is sent or it goes into keep-alive mode, sending periodic stop characters to prevent the daisy-chained device(s) from going into shutdown.

UART Communication ModeWhen transitioning from idle mode to communication mode, the TXP pin must be pulled high (logic-one) prior to signaling the start bit (logic-zero) (see Figure 31). The duration of the logic-one is minimized to maintain a balanced duty cycle while still meeting the timing speci-fication. When transitioning from the stop bit back to idle mode, the delay, if any, is also minimized.

Figure 30. Stop Character

Figure 31. Communication Mode

S 0 10 0 1 0 1 0 E=1 P POPTIONAL

IDLEOPTIONAL

IDLE

IDLE DISABLE

IDLE ENABLE

TXnP

TXnN

IDLE IDLEPREAMBLE

tSTSU

TXnP-TXnN



Data TypesThe battery-management UART protocol employs several different data types, as described in Table 21.

Command BytesThe battery-management UART protocol supports six command types, which are summarized in Table 22.

Command Byte EncodingCommand bytes encoding is described in Table 23. For READDEVICE and WRITEDEVICE commands, the device address is encoded in the command byte. The device ignores those commands containing a device address other than its own.

Table 21. Data Types

Table 22. Command-Packet Types

Table 23. Command-Byte Encoding

Note: z = Total number of devices, ALIVECNTEN = 1, packet size includes framing characters.

*Assumes DA[4:0] = 0x00, where DA[4:0] is the device address in the ADDRESS register.

DATA TYPE DESCRIPTION

Command byte A byte defining the command-packet type, generally either a read or a write.

Register address A byte defining the register address to be read or written.

Register data Register data bytes being read or written.

Data-check byte An error and alert status byte sent and returned with all reads.

PEC byte A packet-error checking byte sent and returned with every packet except HELLOALL.

Alive counter A byte functioning as a device counter on all reads and writes, if ALIVECNTEN = 1.

Fill byte Bytes transmitted in READALL command packets for clocking purposes only.

COMMAND DESCRIPTION DATA CHECK PEC ALIVE

COUNTERPACKET SIZE

(CHARACTERS)

HELLOALLWrites a unique device address to each device in the daisy-chain. Required for system initialization. No No No 8

WRITEALL Writes a specified register in all devices. No Yes Yes 14

WRITEDEVICE Writes a specified register in a single device. No Yes Yes 14

READALL Reads a specific register from all devices. Yes Yes Yes 12 + (4z)

READDEVICE Reads a specified register from a single device. Yes Yes Yes 16

ROLLCALL Reads the ADDRESS register for 32 devices. Yes Yes Yes 138

COMMAND BYTE* 7 6 5 4 3 2 1 0

HELLOALL 57h 0 1 0 1 0 1 1 1

ROLLCALL 01h 0 0 0 0 0 0 0 1

WRITEDEVICE 04h DA4 3 DA2 DA1 DA0 1 0 0

WRITEALL 02h 0 0 0 0 0 0 1 0

READDEVICE 05h DA4 DA3 DA2 DA1 DA0 1 0 1

READALL 03h 0 0 0 0 0 0 1 1



Register AddressesAll register addresses are single-byte quantities and are defined in the Register Map. In general, if the register or device address in a received command is not a valid address for the device, the device will ignore the read or write and simply pass through the packet to the next device.

Register DataAll registers are 16-bit words (two data bytes) and are defined in the Register Map.

Data-Check ByteThe host uses the returned data-check byte to promptly determine if any communication errors occurred during the packet transmission and to check if alert flags are set in any devices, as shown in Table 24. The data-check byte is returned by the READALL and READDEVICE commands. For READDEVICE, the data-check byte is updated only by the addressed device.The data-check byte sent by the host is a seed value normally set to 00h, although non-zero values can be used as a diagnostic. Each device logically ORs the received data-check byte with its own status and trans-mits it to the next device. A PEC error detected by any device will set the ALRTPEC bit in the STATUS register, and by extension, the ALRTPEC and ALRTSTATUS bits in the data-check byte.

PEC ByteThe PEC byte is a CRC-8 packet-error check sent by the host with all read and write commands. If any device receives an invalid PEC byte, it sets the ALRTPEC bit in the STATUS register. During any write transaction, a device does not execute the write command internally unless the received PEC matches the expected calculat-ed value. For read commands, the device must return its own calculated PEC byte based on the returned data. The host should verify that the received PEC byte matches the calculated value; if an error is indicated, the data should

be discarded. See the Applications Information section for details on the PEC calculation.

Alive-Counter ByteThe alive-counter byte is the last data byte of the com-mand packets (except HELLOALL) if the ALIVECNTEN bit is set in the DEVCFG1 register. The host typically trans-mits the alive-counter seed value as 00h, but any value is permitted. For WRITEALL or READALL commands, each device retransmits the alive counter incremented by one. For WRITEDEVICE or READDEVICE commands, only the addressed device increments it. The alive counter is not used in the HELLOALL command. If the alive counter reaches FFh, the next device increments it to 00h.Since the alive counter comes after the PEC byte, an incorrect PEC value will not affect the incrementing of the alive-counter byte. Also, the PEC calculation does not include the alive-counter byte. The host should verify that the alive counter equals the original seed value + the number of devices, considering that if the alive counter reaches FFh, the next device increments it to 00h.

Fill BytesIn the READALL command, the host sends two fill bytes for each device in the daisy-chain. The fill bytes are the locations within the packet and are used by the device to place the read data. The fill-byte values transmitted by the MAX17841B interface alternates between C2h and D3h. As the command packet propagates through the device, the device overwrites the appropriate fill bytes with the register data. The device uses the ADDRESS register to determine which specific fill bytes in the packet should be overwritten. For a READDEVICE command, only two fill bytes are required since only one device responds (returning two data bytes). Also, fill bytes are not required for write com-mands because the data received is exactly the same as the data retransmitted.

Table 24. Data-Check ByteBIT NAME DESCRIPTION

7 ALRTPEC ALRTPEC is set.6 ALRTFMEA ALRTFMEA1 or ALRTFMEA2 is set.5 ALRTSTATUS STATUS bit other than ALRTFMEA1, ALRTFMEA2, ALRTOV, and ALRTUV is set.4 CHECK Check bit. Value that is received is forwarded.3 CHECK Check bit. Value that is received is forwarded.2 ALRTOV ALRTOV is set.1 ALRTUV ALRTUV is set.0 CHECK Check bit. Value that is received is forwarded.



Battery-Management UART Protocol CommandsHELLOALL CommandThe purpose of the HELLOALL command is to initialize the device addresses of all daisy-chained devices. The device address is stored in the DA[4:0] bits of the ADDRESS reg-ister. The highest address possible is 0x1F, so a maximum of 32 devices can be addressed. The command must be issued after POR to reinitialize all device addresses.When the HELLOALL command is first sent by the host, the address specified in the HELLOALL command is stored to the DA[4:0] bits of the ADDRESS register in the first daisy-chained device. The command is then forward-ed to the next device in the chain with the DA[4:0] bits of the address byte incremented by 1, as shown in Table 25. This continues in the upstack direction for each device. The downstack communication path does not increment the address. The advantage of the host choosing a first address of 0x00 is that it is not necessary to write the first address (FA[4:0]) to all the devices since the default value of FA[4:0] is 0x00. Note: The host should set the first address so no assigned device address increments from 0x1F to 0x00 during the HELLOALL.The DA[4:0] value returned to the host is one greater than the address assigned to the last device. Once this last address is known, the host can determine how many devices are in the daisy-chain, which is required for sub-sequent READALL commands. A READALL command should be used to verify the ADDRESS registers.Special considerations exist if the host wants to use internal loopback instead of external loopback. The first HELLOALL command is not returned to the host because the internal loopback bit for the top device has not yet been written. If the number of devices is known to the

host, the host can use a WRITEDEVICE to set the inter-nal loopback bit on the last device and then verify with a READALL. If the number of devices is unknown, the internal loopback bit must be set on the first device, veri-fied and then cleared. It can then be set on the second device and verified, and so on incrementally until there is no response (end of stack). With the number of devices known, the loopback bit can be reset on the last device and all ADDRESS registers verified.When a device receives a valid HELLOALL command, it clears the ADDRUNLOCK bit of the DEVCFG1 reg-ister. When this bit is 0, HELLOALL commands are ignored to prevent inadvertently changing any device address. In order to reconfigure the device address, the ADDRUNLOCK bit must first be set to ‘1’ or a POR event must occur. After configuring the device addresses, they should be verified using the READALL or ROLLCALL commands.

WRITEALL CommandThe WRITEALL command writes a 16-bit value to a speci-fied register in all daisy-chained devices. Since most con-figuration information is common to all the devices, this command allows faster setup than writing to each device individually. If the register address is not valid for the device, the command is ignored. The command sequence is shown in Table 26. The register value is written immediately after the valid PEC byte is received or, if NOPEC is set, after the last byte is received. If the received PEC byte does not match the internal calculation, the command is not executed, but is still forwarded to the next device. The PEC is calculated from the first 4 bytes of the command starting after the preamble. A PEC error will generate a PEC alert in the device STATUS register.

Table 25. HELLOALL Sequencing (z = Total Number of Devices)HOST TX DEVICE (n) RXL DEVICE (n) TXU HOST RX

Preamble Preamble Preamble Preamble57h 57h 57h 57h00h 00h 00h 00h

0b000,ADDR[4:0] 0b000,ADDR[4:0]+n-1 0b000,ADDR[4:0]+n 0b000,ADDR[4:0]+zStop Stop Stop Stop



WRITEDEVICE CommandThe WRITEDEVICE command writes a 16-bit value to the specified register in the addressed device only. If the register address is not valid for the device, the command is ignored. The command sequence is shown in Table 27.The register value is written immediately after the valid PEC byte is received or, if NOPEC is set, after the last byte is received. If the received PEC byte does not match the internal calculation, the command is not executed, but is still forwarded to the next device. The PEC is cal-culated from the first 4 bytes of the command starting after the preamble. A PEC error sets the ALRTPEC bit in the STATUS register. A PEC error can only occur in the addressed device.

READALL CommandThe READALL command returns register data from the specified register for all daisy-chained devices. The data

for the first device (connected to the host) is returned last. The command sequence is shown in Table 28. If the received PEC byte does not match the calculated value, the ALRTPEC bit of the data-check byte and ALRTPEC bit of the STATUS register are set, but the command proceeds. A Manchester error immediately switches the data propagation from read mode to write (pass-through) mode, ensuring that the Manchester error is propagated through the daisy-chain and back to the host.The fill byte values transmitted by the MAX17841B interface alternate between C2h and D3h as shown. As the packet propagates through the device, the device retransmits it in the order shown in the sequencing table (device TXU column). The device knows which bytes to overwrite since its ADDRESS register contains the first device address and its own device address; therefore, it knows where in the data stream it belongs.

Table 26. WRITEALL Sequencing (Unchanged by Daisy-Chain)

Table 27. WRITEDEVICE Sequencing (Unchanged by Daisy-Chain)

*If alive-counter mode is enabled.


HOST TX DEVICE (n) RXL DEVICE (n) TXU HOST RX

Preamble Preamble Preamble Preamble

02h 02h 02h 02h

[REG ADDR] [REG ADDR] [REG ADDR] [REG ADDR]

[DATA LSB] [DATA LSB] [DATA LSB] [DATA LSB]

[DATA MSB] [DATA MSB] [DATA MSB] [DATA MSB]

[PEC] [PEC] [PEC] [PEC]

[ALIVE]* [ALIVE]* [ALIVE]* [ALIVE]*

Stop Stop Stop Stop

HOST TX DEVICE(n) RXL DEVICE(n) TXU HOST RX


(DA[4:0]),0b100 (DA[4:0]),0b100 (DA[4:0]),0b100 (DA[4:0]),0b100


[DATA LSB] [DATA LSB] [DATA LSB] [DATA LSB]

[DATA MSB] [DATA MSB] [DATA MSB] [DATA MSB]

[PEC] [PEC] [PEC] [PEC]

[ALIVE]* [ALIVE]* [ALIVE]* [ALIVE]*

Stop Stop Stop Stop



READDEVICE CommandThe READDEVICE command returns a 16-bit word read from the specified register in the addressed device only. If the register address is not valid for the device, the com-mand is ignored. The command sequence is shown in Table 29.The command packet is forwarded up the daisy-chain until it reaches the addressed device. The addressed device overwrites the received fill bytes with the 2 bytes of regis-ter data and forwards the packet to the next device. The alive-counter byte is only incremented by the addressed device. A Manchester error immediately switches the data propagation from read mode to write (pass-through)

mode, ensuring that the Manchester error is propagated through the daisy-chain and back to the host.

ROLLCALL CommandWhile not required for system initialization, the ROLLCALL command (01h) can be used to verify that all devices are responding, regardless of the value of FA[4:0]. The response of each device is identical to that of a READALL command of the ADDRESS register, where the first device address (FA[4:0]) is 00h, and there are 32 devices; therefore, the ROLLCALL command is sent with 64 fill bytes and each device places the data-check and PEC bytes after the 32nd register data word. This ensures that each device can return its ADDRESS register data.

Table 28. READALL Command Sequencing (z = no. of devices)


HOST TX DEVICE(n) RXL DEVICE(n) TXU HOST RX


03h 03h 03h 03h

[REG ADDR] [REG ADDR] [DATA ADDR] [REG ADDR]

[DC] = 0x00 [DATA LSB(n-1)] [DATA LSB(n)] [DATA LSB(z)]

[PEC] [DATA MSB(n-1)] [DATA MSB(n)] [DATA MSB(z)]

[ALIVE]* … … [DATA LSB(z-1)]

[FD(1) C2h] … … [DATA MSB(z-1)]

[FD(1) D3h] [DATA LSB(1)] [DATA LSB(1)] …

[FD(2) C2h] [DATA MSB(1)] [DATA MSB(1)] …

[FD(2) D3h] [DC] [DC] …

… [PEC] [PEC] …

… [ALIVE]* [ALIVE]* …

… [FD(1) C2h] [FD(1) C2h] …

… [FD(1) D3h] [FD(1) D3h] [DATA LSB(1)]… … … [DATA MSB(1)]… … … [DC]

[FD(z) C2h] [FD(z-n) C2h] [FD(z-n-1) C2h] [PEC]

[FD(z) D3h] [FD(z-n) D3h] [FD(z-n-1) D3h] [ALIVE]*

Stop Stop Stop Stop

12 + (4 x z) characters 12 + (4 x z) characters 12 + (4 x z) characters 12 + (4 x z) characters



DiagnosticsBuilt-in diagnostics support ISO 26262 (ASIL) require-ments by detecting specific fault conditions, as shown in Table 30. The device automatically performs some of the diagnostics while the host performs others during initial-ization (e.g., at key-on), or periodically during operation,

as required by the application. Diagnostics performed automatically by the device are previously described in the relevant functional sections. A description of the diag-nostics requiring specific configurations are provided in this section.

Table 30. Summary of Built-In Diagnostics

Table 29. READDEVICE Sequencing


DIAGNOSTICS PERFORMED AUTOMATICALLY BY DEVICE WITH NO HOST INTERVENTION

FAULT DIAGNOSTIC PROCEDURE OUTPUT

VAA undervoltage Continuous voltage comparison ALRTRSTVHV undervoltage Continuous voltage comparison ALRTHVUVVHV overvoltage Continuous voltage comparison ALRTHVOV

VHV low headroom Voltage comparison (updated during measurement) ALRTHVHDRM

32kHz oscillator fault Continuous frequency comparison ALRTOSC1, ALRTOSC2

16MHz oscillator fault Communication error checking ALRTMAN, ALRTPAR

Communication fault Communication error checking ALRTPEC, ALRTMAN, ALRTPAR

RX pin open/short Verify RX mode after POR ALRTCOMMSEUn/ALRTCOMMSELn

VDDLn pin open/short Continuous voltage comparison ALRTVDDLx

GNDLn pin open/short Continuous voltage comparison ALRTGNDLx

Die overtemperature Temperature comparison (updated after measurement) ALRTTEMP

HOST TX DEVICE RXL DEVICE TXU HOST RX


DA[4:0], 0b101 DA[4:0], 0b101 DA[4:0], 0b101 DA[4:0], 0b101


[DC] [DC] [DATA LSB] [DATA LSB]

[PEC] [PEC] [DATA MSB] [DATA MSB]

[ALIVE]* [ALIVE]* [DC] [DC]

[FD(1) C2h] [FD(1) C2h] [PEC] [PEC]

[FD(1) D3h] [FD(1) D3h] [ALIVE]* [ALIVE]*

Stop Stop Stop Stop

16 characters 16 characters 16 characters 16 characters



Table 30. Summary of Built-In Diagnostics (continued)

Note: Pin faults such as an open pin or adjacent pins shorted to each other must be detectable. Pin faults do not result in device dam-age but have a specific device response such as a communication error, or are detectable through a built-in diagnostic. Analyzing the effect of pin faults is referred to as a pin FMEA. Contact Maxim Applications to obtain pin FMEA results.

DIAGNOSTICS PERFORMED DURING ACQUISITION MODE AS SELECTED BY DIAGSEL OR BALSWDIAG

FAULT DIAGNOSTIC PROCEDURE DIAGSEL[2:0] OUTPUT

Reference voltage fault ALTREF diagnostic DIAGSEL = 1h DIAG[15:0] (ALTREF voltage)VAA voltage fault VAA diagnostic DIAGSEL = 2h DIAG[15:0] (VAA voltage)

LSAMP Offset too high LSAMP offset diagnostic DIAGSEL = 3h DIAG[15:0] (LSAMP offset voltage)

ADC bit stuck high Zero-Scale ADC diagnostic DIAGSEL = 4h DIAG[15:0] (Zero scale)

ADC bit stuck low Full-Scale ADC diagnostic DIAGSEL = 5h DIAG[15:0] (Full scale)VPTAT or

ALRTTEMP fault Die Temperature diagnostic DIAGSEL = 6h DIAG[15:0] (VPTAT voltage), ALRTTEMP

Balancing switch short BALSW diagnostic mode BALSWDIAG = 1h ALRTBALSW

Balancing switch open BALSW diagnostic mode BALSWDIAG = 2h ALRTBALSW

Odd sense-wire open BALSW diagnostic mode BALSWDIAG = 5h ALRTBALSW

Even sense-wire open BALSW diagnostic mode BALSWDIAG = 6h ALRTBALSWPROCEDURAL DIAGNOSTICS

FAULT DIAGNOSTIC PROCEDURE OUTPUT

SHDNL stuck high Idle mode ALRTSHDNL

HVMUX switch open Acquisition with HVMUX test sources ALRTOV, ALRTUV

HVMUX switch short ALTREF diagnostic DIAG[15:0]

HVMUX test sources Acquisition with HVMUX test sources CELLn

Cn pin open Acquisition with cell test sources ALRTOV, ALRTUV

Cn short to SWn Acquisition with balancing switches CELLn

Cn pin leakage ALTMUX vs. HVMUX acquisition CELLn

Voltage comparator fault ALTMUX acquisition with balancing switches CELLn

Voltage comparator fault ALTMUX acquisition with balancing switches CELLn

ALRTHVUV comparator Acquisition with HV charge pump disabled ALRTHVUV

HVMUX sequencer Acquisition with cell test sources CELLn

ALU Data Path Acquisition with ADCTEST = 1 CELLn, VBLKP, DIAG, and AUXINn

AUXINn Pin Open Acquisition with AUXIN test sources AUXINn

Calibration corruption Read CALx, IDx, perform CRC ID2



ALTREF Diagnostic MeasurementThe ALTREF diagnostic measurement (DIAGSEL[2:0] = 0b001) checks the primary voltage reference of the ADC by measuring the alternate reference voltage (VALTREF). The result is available in the DIAG register after a normal acquisition. See Figure 32.The ALTREF voltage is computed from the result in the DIAG register as follows:

VALTREF = (DIAG[15:2]/16384d ) x 5VSince 1.23V < VALTREF < 1.254V and VALTREF = 1.242V nominally, the expected range for DIAG[15:2] is (1.23V/5V) x 16384d = 4030d to (1.254V/5V) x 16384 = 4109d; therefore, 0FBEh ≤ DIAG[15:2] ≤ 100Dh. To use the 16-bit register value, the 14-bit values must be shifted or multiplied by 4 so that 3EF8h ≤ DIAG[15:0] ≤ 4034h.

VAA Diagnostic MeasurementThe VAA diagnostic measurement (DIAGSEL[2:0] = 0b010) verifies that VAA is within specification. This diagnostic measures VREF, but using VTHRM as the ADC reference. See Figure 33.The voltage into the ADC is computed from the result in the DIAG register as follows:

(6/13) x VREF = (DIAG[15:2]/16384d ) x VTHRMAssuming VTHRM = VAA, then VAA is given by:

VAA = (6/13) x VREF x 16384d/DIAG[15:2], where VREF = 2.307V

The result for VAA should fall within the range provided in the Electrical Characteristics table for VAA.

Figure 32. ALTREF Diagnostic

Figure 33. VAA Diagnostic

ADC IN -

ADC IN +

ALTREF

LVMUX ADC

REFTHRM

+

-

LSAMP

HVMUX BUS

AGND

G = 6/13

ADC AUTOMATICALLY IN UNIPOLAR MODE

ADC IN -

ADC IN +

REF

LVMUX ADC

VREF

VTHRM

+

-

LSAMP

AGND

G = 6/13

ADC AUTOMATICALLY IN UNIPOLAR MODE

HVMUXBUS



LSAMP Offset Diagnostic MeasurementThe LSAMP diagnostic measurement (DIAGSEL[2:0] = 0b011) measures the level-shift amplifier offset by short-ing the LSAMP inputs during the diagnostic portion of the acquisition. The result is available in the DIAG register after a normal acquisition. For this measurement, the ADC polarity is automatically set to bipolar mode to allow accurate measurement of voltages near zero. This mea-surement eliminates the chopping phase to preserve the offset error. If the diagnostic measurement exceeds the valid range for VOS_LSAMP, as specified in the Electrical Characteristics table, the chopping function may not be able to cancel out all the offset error, and acquisition accuracy could be degraded accordingly. See Figure 34.

The LSAMP offset is computed from the result in the DIAG register as follows:

LSAMP Offset = (|DIAG[15:2] - 2000h |/16384d ) x 5VThe validity of measurements through LSAMP is further confirmed by the ALTREF and VAA diagnostics, and com-parison of the VBLKP measurement to the sum of the cell measurements.

Zero-Scale ADC Diagnostic MeasurementStuck ADC output bits can be verified with a combination of the zero-scale and full-scale diagnostics. The zero-scale ADC diagnostic measurement (DIAGSEL[2:0] = 0b100) verifies that the ADC conversion results in 000h when its input is at -VAA in bipolar mode (since for an input ≤ -2.5V, DIAG[15:0] = 0000h). For this measure-ment, the ADC is automatically set to bipolar mode. See Figure 35.

Figure 34. LSAMP Offset Diagnostic

Figure 35. Zero-Scale ADC Diagnostic

+

-

LSAMP HVMUXBUS

ADC IN -

ADC IN +

LVMUX ADC

ADC AUTOMATICALLY IN BIPOLAR MODE

G = 6/13

ADC IN -

ADC IN +VAA

LVMUX ADC

REFTHRM


AGND

AGND



Full-Scale ADC Diagnostic MeasurementStuck ADC output bits can be verified with a combination of the zero-scale and full-scale diagnostics. The full-scale ADC diagnostic measurement (DIAGSEL[2:0] = 0b101) verifies that the ADC conversion results in FFFh when its input is at VAA in bipolar mode (since for an input ≥ 2.5V, DIAG[15:0] = FFF0h). For this measurement, the ADC is automatically set to bipolar mode. See Figure 36.

BALSW DiagnosticsFour balancing switch-diagnostic modes are available to facilitate the following diagnostics:

Balancing switch shorted (BALSWDIAG[2:0] = 0b001) Balancing switch open (BALSWDIAG[2:0] = 0b010) Odd sense wire open (BALSWDIAG[2:0] = 0b101) Even sense wire open (BALSWDIAG[2:0] = 0b110)

Enabling any of these modes automatically preconfigures the acquisition (e.g., enables the ALTMUX measurement path). The host must initiate the acquisition, but the diag-nostic mode automatically compares the measurements to the specific thresholds and sets any corresponding alerts. The host presets the thresholds, as determined by the minimum and maximum resistance of the switch (RSW) specified in the Electrical Characteristics table and the intended cell-balancing current.During any balancing switch-diagnostic mode, ALRTOV, ALRTUV, and ALRTMSMTCH comparisons are disabled.

After BALSWDIAG[2:0] is cleared, the modified configura-tions automatically return to their prior setting. The same configurations and comparisons could be implemented manually but at the expense of more host operations.

BALSW Short DiagnosticA short-circuit fault in the balancing path could be a short between SWn and SWn-1 (see Figure 37) or that the balancing FET is stuck in the conducting state. In the short-circuit state, the voltage between SWn and SWn-1 (switch voltage) is less than the voltage between Cn and Cn-1 (cell voltage).When enabled, the balancing switch short-diagnostic mode (BALSWDIAG[2:0] = 0b001) functions as follows:

Disables the balancing switches automatically Configures the acquisition using ALTMUX path

automatically Host initiates the acquisition Compares the measurement to the BALSHRTTHR

threshold value automatically (Table 32) If outside the threshold, sets the corresponding flag in

ALRTBALSW automaticallyFor the best sensitivity to leakage current, set the threshold value based on the minimum cell voltage minus a small noise margin (100mV), then update the threshold value periodically or every time a measurement is taken, depend-ing on how fast the cell voltages are expected to change.

Figure 36. Full-Scale ADC Diagnostic Figure 37. Balancing Switch Short

ADC IN -

ADC IN +VAA

LVMUX ADC

REFTHRM


AGND

AGND

HVBALANCING SWITCH (n)

TO ALTMUX

TO ALTMUX

SWn

SWn-1

CN

AGND

Cn-1

BALSWEN

TO HVMUX

TO HVMUX

SHORT CIRCUIT



Figure 38. BALSW Short Diagnostic

Table 31. BALSW Short-Diagnostic Auto Configuration

SET BALSWDIAG[2:0] TO 0b001

START ADC MEASUREMENT

WAIT 100µs

MAX178xx FULLY FUNCTIONAL AND

INITIALIZED

SCANDONE = 1

NO

YES

BALSW SHORT CIRCUIT CHECK

INVALID

ENSURE BALSHRTTHR SET TO DESIRED

VALUE

ALRTFMEA DATACHECK BIT SHOWS RESULT

CLEAR BALSWDIAG[2:0] AND SCANDONE

BALSW SHORT CIRCUIT CHECK

DONE

CHECK ALRTBALSW OR CELLn REGISTERS FOR

DETAILED RESULT

CONFIGURATION BITS AUTOMATIC SETTING PURPOSE

MEASUREEN[14:12] 0b000 Disable AUXIN and VBLKP measurements

BALSWEN[11:0] 000h Disable all balancing switches

DIAGCFG.ALTMUXSEL 1 Enable ALTMUX measurement path



BALSW Open DiagnosticThe BALSW open diagnostic (BALSWDIAG[2:0] = 0b010) verifies that each enabled balancing switch is conducting (not open) as follows:

Automatically configures acquisition for bipolar mode (for measuring voltages near zero)

Automatically configures acquisition for ALTMUX path Automatically configures acquisition to measure switch

voltages for those switches enabled by BALSWEN

Host initiates acquisition Automatically compares measurement to the thresh-

old value BALLOWTHR and BALHIGHTHR (Table 32) If outside the threshold, automatically sets the corre-

sponding flag in ALRTBALSWSet the thresholds by taking into account the minimum and maximum RSW of the switch itself, as specified in the Electrical Characteristics table and the balancing current for the application. See Figure 39 and Table 33.

Table 33. BALSW Open-Diagnostic Auto Configuration

Table 32. BALSW Diagnostics

CONFIGURATION BITS AUTOMATIC SETTING PURPOSE

MEASUREEN[14:12] 0b000 Disable AUXINn and VBLKP measurements

MEASUREEN[11:0] BALSWEN[11:0] Measure only active switch positions


SCANCTRL.POLARITY 1 Enable bipolar mode

BALSW VSWn FAULT INDICATED? POSSIBLE FAULT CONDITION

On

> V(BALHIGHTHR) Yes Switch open circuit, or overcurrent> V(BALLOWTHR)

No None< V(BALHIGHTHR)< V(BALLOWTHR) Yes Path open circuit or short circuit

Off> V(BALSHRTTHR) No None< V(BALSHRTTHR) Yes Short circuit or leakage current



Figure 39. BALSW Open Diagnostic

SET BALSWDIAG[2:0] TO 0b010



INITIALIZED

SCANDONE= 1?

NO

YES

BALSW OPEN CHECK INVALID

ENSURE BALLOWTHR AND BALHIGHTHR SET

TO DESIRED VALUE


BALSW OPEN CHECK DONE

CHECK ALRTBALSW OR CELLn REGISTERS FOR

DETAILED RESULT




Even/Odd Sense-Wire Open DiagnosticsIf enabled, the sense-wire open-diagnostic modes detect if a cell-sense wire is disconnected as follows:

Automatically closes nonadjacent switches (even or odd)

Automatically configures acquisition to use the ALTMUX path

Host waits 100μs for settling and then initiates the acquisition

Automatically compares result to the BALHIGHTHR and BALLOWTHR register

If outside thresholds, automatically sets flags in ALRTBALSW

See Figure 40, Figure 41, Table 34, Table 35, and Table 36.

Figure 40. Cell Sense-Wire Open Diagnostics


TO ALTMUX

TO ALTMUXSWn

SWn-1

Cn

AGND

Cn-1

BALSWEN

RFILTER

RBALANCE

CFILTER

CELL n

RFILTER

RBALANCECFILTER

RBALFILTER

TO HVMUX

TO HVMUX

TO CELL n-1

TO CELL n+1

SENSE WIRE

SENSE WIRE

DETECT BREAK IN DASHED-LINE PATH



Table 34. Odd Sense-Wire Open-Measurement Result

Table 35. Even Sense-Wire Open-Measurement Result

Note: NC = No Change; UD = Undefined; Maximum result is 5V.

Note: NC = No Change; UD = Undefined; Maximum result is 5V.

SENSE WIRE OPEN FAULT LOCATIONC0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

CEL

L M

EASU

REM

ENT

CH

AN

GE

Cell1 0V 0V NC NC NC NC NC NC NC NC NC NC NC

Cell2 NC cell1+ cell2

cell2+ cell3 NC NC NC NC NC NC NC NC NC NC

Cell3 NC NC 0V 0V NC NC NC NC NC NC NC NC NC

Cell4 NC NC NC cell3+ cell4

cell4+ cell5 NC NC NC NC NC NC NC NC

Cell5 NC NC NC NC 0V 0V NC NC NC NC NC NC NC

Cell6 NC NC NC NC NC cell5+ cell6

cell6+ cell7 NC NC NC NC NC NC

Cell7 NC NC NC NC NC NC 0V 0V NC NC NC NC NC

Cell8 NC NC NC NC NC NC NC cell7+ cell8

cell8+ cell9 NC NC NC NC

Cell9 NC NC NC NC NC NC NC NC 0V 0V NC NC NC

Cell10 NC NC NC NC NC NC NC NC NC cell9+ cell10

cell10+ cell11 NC NC

Cell11 NC NC NC NC NC NC NC NC NC NC 0V 0V NC

Cell12 NC NC NC NC NC NC NC NC NC NC NC cell11+ cell12 UD

SENSE WIRE OPEN FAULT LOCATIONC0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

CEL

L M

EASU

REM

ENT

CH

AN

GE

Cell1 UD cell1+ cell2 NC NC NC NC NC NC NC NC NC NC NC

Cell2 NC 0V 0V NC NC NC NC NC NC NC NC NC NC

Cell3 NC NC Cell2+ cell3

cell3+ cell4 NC NC NC NC NC NC NC NC NC

Cell4 NC NC NC 0V 0V NC NC NC NC NC NC NC NC

Cell5 NC NC NC NC cell4+ cell5

cell5+ cell6 NC NC NC NC NC NC NC

Cell6 NC NC NC NC NC 0V 0V NC NC NC NC NC NC

Cell7 NC NC NC NC NC NC cell6+ cell7

cell7+ cell8 NC NC NC NC NC

Cell8 NC NC NC NC NC NC NC 0V 0V NC NC NC NC

Cell9 NC NC NC NC NC NC NC NC cell8+ cell9

cell9+ cell10 NC NC NC

Cell10 NC NC NC NC NC NC NC NC NC 0V 0V NC NC

Cell11 NC NC NC NC NC NC NC NC NC NC cell10+ cell11

cell11+ cell12 NC

Cell12 NC NC NC NC NC NC NC NC NC NC NC 0V 0V



Figure 41. Sense-Wire Open Diagnostic

Table 36. Sense-Wire Open-Diagnostic Configurations

SET BALSWDIAG[2:0]


INITIALIZED

ENSURE BALLOWTHR AND BALHIGHTHR SET

TO DESIRED VALUE

0b101 FOR ODD SWITCHES0b110 FOR EVEN SWITCHES


SCANDONE= 1?

NO

YES

BALSW CONDUCTING CHECK

INVALID


BALSW CONDUCTING CHECK DONE

CHECK ALRTBALSW OR CELLn REGISTERS FOR DETAILED

RESULT


WAIT 100µs

CONFIGURATION BIT(S) CONFIGURATION STATE TASK

BALSWEN[11:0]555h (BALSWDIAG = 0b101) or Enable odd switches

AAAh (BALSWDIAG = 0b110) Enable even switches

MEASUREEN[14:12] 0b000 Disable AUXINn and VBLKP measurements

MEASUREEN[11:0] BALSWEN[11:0] Measure only active switch positions


SCANCTRL.POLARITY 1 Enable bipolar mode



Diagnostic Test SourcesDiagnostic test current sources (see Figure 42) can be enabled prior to the acquisition mode for detecting both internal and external hardware faults in the measurement path. One set of test sources is connected to the HVMUX input side and another set is connected to the HVMUX output side. The basic premise in these diagnostics is for a symmetrical measurement channel with no faults, the test currents can be applied symmetrically to the differential channel and there should only be almost no change in the channel measurement. On the other hand, if an asymmet-ric fault exists on the channel, the resulting change will indi-cate the nature of the fault (e.g., an open or shorted pin). For the 15 test current sources on the input channels (13 Cn and 2 AUXINn):

The test currents are individually enabled per CTSTEN[12:0] and AUXINTSTEN[2:1]

The test current ranges from 6.25µA up to 100µA per CTSTDAC[3:0] (applies to all enabled sources)

The test current sources from VAA or sinks to AGND per the CTSTSRC bit (applies to all enabled sources)

For the two test current sources on the HVMUX output side:

The test currents are enabled by the MUXDIAGEN bit The test current always sources from the HV supply

The test current ranges from 3.125µA up to 50µA per CTSTDAC[3:0] (applies to all enabled sources)

The test current, by default, is applied to both HVMUX outputs (even and odd outputs); however, if MUXDIAGPAIR is set, the test current is applied to only one of the output lines per MUXDIAGBUS. This mode is used to test the test sources themselves (see Table 37 for HVMUX output assignments)

Table 37. HVMUX Output Assignment

Figure 42. Test Current Sources

Cn-1

CnRFILTER

RFILTER

RHVMUXX

CELL n

+

-

LSAMPTO

ADC

X

X

VAA

AGND

CELL TEST CURRENT SOURCE

VAA

AGND

CELL TEST CURRENT SOURCE

AGND

AGND

X

HV HV

HVMUX TEST SOURCES CONTROLLED BY:MUXDIAGENMUXDIAGPAIRMUXDIAGBUSCTSTDAC

CELL TEST SOURCES CONTROLLED BY:CTSTENnCTSTSRCCTSTDAC

RHVMUX

INPUT SIGNAL HVMUX OUTPUTC12 Even busC11 Odd busC10 Even busC9 Odd busC8 Even busC7 Odd busC6 Even busC5 Odd busC4 Even busC3 Odd busC2 Even busC1 Odd busC0 Even bus

REF Odd busALTREF Odd busAGND Even bus



Shutdown DiagnosticThe shutdown diagnostic, as shown in Table 38, verifies that no hardware fault is preventing the device from shutting down, such as the SHDNL input being stuck at logic-one. To perform the diagnostic, the host attempts a shutdown. The timing shown in Figure 43 is for a UART idle-mode shutdown. Once VSHNDL < 0.6V, the ALRTSHDNL bit is set in the STATUS register and the regulator is disabled;

however, the STATUS register may still be read as long as VAA has not decayed below 2.95V (typ), which takes about 1ms. The host should verify that ALRTSHDNL is set. By reading the bit, the charge pump drives VSHDNL > 1.8V in about 200µs and enables the regulator. The host must clear the ALRTSHDNL bit to complete the diagnostic. The ALRTSHDNLRT bit is a real-time version of ALRTSHDNL, which automatically clears when VSHDNL > 1.8V.

Figure 43. Shutdown Diagnostic Timing

Table 38. Shutdown DiagnosticFAULT COMPARISON ALERT BIT LOCATION

SHDNL input stuck VSHDNL < 0.6V? ALRTSHDNL STATUS[12]

SHDNL input stuck VSHDNL < 0.6V? ALRTSHNDRT STATUS[11]



HVMUX Switch Open DiagnosticSince an open HVMUX switch causes the measured voltage to go to either zero or full scale, it is possible to execute the test by looking for an overvoltage or under-voltage alert following the diagnostic measurement, with-out analyzing the measurement data. It is possible to read all voltage measurements and let the host compare the results by splitting the test into several segments.

The procedure in Figure 44 is quick and efficient. For higher sensitivity to faults, each cell-voltage measurement in the diagnostic mode can be compared to a threshold of 100mV by the host to determine if the HVMUX path is working correctly. The threshold is derived from the worst- case HVMUX resistance mismatch and the worst-case diagnostic current-source value variation. See Table 39 for the HVMUX switch open-fault locations

Figure 44. HVMUX Switch Open Diagnostic

Table 39. HVMUX Switch Open Diagnostic

Note: NC = No change.

MAX178xx FULLY FUNCTIONAL AND INITIALIZED;

MUXDIAGPAIR = 0 DBLBUF = 0

ENABLE VALID CELLS FOR MEASUREMENT


NO

YES

MUX SWITCH PAIRIS MALFUNCTIONING


ALRTOV OR ALRTUV?

STORE MEASUREMENT VALUES IN HOST

SET TEST CURRENT SOURCE VALUE CTSTDAC[3:0] = 0xF

MUXDIAGEN = 1

ALL MUX SWITCHES AND PATHS FUNCTIONING

ENABLE MUX TEST CURRENT SOURCE

HVMUX SWITCH OPEN-FAULT LOCATIONC0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

CEL

L M

EASU

REM

ENT

Cell1 0V 5V NC NC NC NC NC NC NC NC NC NC NC

Cell2 NC 0V 5V NC NC NC NC NC NC NC NC NC NC

Cell3 NC NC 0V 5V NC NC NC NC NC NC NC NC NC

Cell4 NC NC NC 0V 5V NC NC NC NC NC NC NC NC

Cell5 NC NC NC NC 0V 5V NC NC NC NC NC NC NC

Cell6 NC NC NC NC NC 0V 5V NC NC NC NC NC NC

Cell7 NC NC NC NC NC NC 0V 5V NC NC NC NC NC

Cell8 NC NC NC NC NC NC NC 0V 5V NC NC NC NC

Cell9 NC NC NC NC NC NC NC NC 0V 5V NC NC NC

Cell10 NC NC NC NC NC NC NC NC NC 0V 5V NC NC

Cell11 NC NC NC NC NC NC NC NC NC NC 0V 5V NC

Cell12 NC NC NC NC NC NC NC NC NC NC NC 0V 5V



HVMUX Switch Shorted DiagnosticA shorted mux switch is detectable in two ways based on corrupted measurement values. First, the ALTREF diagnostic will report a large error. Also, during normal cell measurements, a shorted HVMUX switch will cause the LSAMP to saturate, which is also easily detectable.

HVMUX Test Source DiagnosticThe two current sources attached to the HVMUX even bus and the HVMUX odd bus can be enabled indepen-dently instead of as a pair setting the MUXDIAGPAIR bit. MUXDIAGBUS controls which source is enabled (MUXDIAGBUS = 1 for odd bus source). This causes every measurement to have a definable change as the sources are enabled and disabled. By taking measure-ments while alternating which current source is enabled, it is possible to verify that each current source is working (see Table 40).

Table 40. HVMUX Test Source Diagnostic

Note: I = Test source current, R = HVMUX resistance.

HVMUX TEST SOURCE FAULT:

EVEN TEST SOURCE SHORTED TO HV

EVEN TEST SOURCE OPEN CIRCUIT

ODD TEST SOURCE SHORTED TO HV

ODD TEST SOURCE OPEN CIRCUIT

CEL

L M

EASU

REM

ENT

CH

AN

GE

Cell1: 0V -I x R 5V I x R

Cell2: 5V I x R 0V -I x R













Cn Open DiagnosticIf the cell is disconnected from the input, the corresponding cell test source (sinking to AGND) will pull the cell input voltage toward 0V (except for C0, where source to VAA current source will pull the cell input voltage to VAA) A new mea-surement is taken with the current sources enabled, and a change in measurement value is detected. If no open circuit exists, then the measurement value will change by only the value of the test current across the application circuit series resistor to the Cn pin. See Table 41.

Table 41. Cn Pin Open Diagnostic

Note: NC = no change.

Cn PIN OPEN FAULT LOCATION

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

CEL

L M

EASU

REM

ENT

Cell1 Cell1- 3.3V 0V NC NC NC NC NC NC NC NC NC NC NC

Cell2 NC Cell2+ Cell1 0V NC NC NC NC NC NC NC NC NC NC

Cell3 NC NC Cell3+ Cell2 0V NC NC NC NC NC NC NC NC NC

Cell4 NC NC NC Cell4+ Cell3 0V NC NC NC NC NC NC NC NC

Cell5 NC NC NC NC Cell5+ Cell4 0V NC NC NC NC NC NC NC

Cell6 NC NC NC NC NC Cell6+ Cell5 0V NC NC NC NC NC NC

Cell7 NC NC NC NC NC NC Cell7+ Cell6 0V NC NC NC NC NC

Cell8 NC NC NC NC NC NC NC Cell8+ Cell7 0V NC NC NC NC

Cell9 NC NC NC NC NC NC NC NC Cell9+ Cell8 0V NC NC NC

Cell10 NC NC NC NC NC NC NC NC NC Cell10+ Cell9 0V NC NC

Cell11 NC NC NC NC NC NC NC NC NC NC Cell11+ Cell10 0V NC

Cell12 NC NC NC NC NC NC NC NC NC NC NC Cell12+ Cell11 0V



Cn Shorted to SWn DiagnosticShort circuits between the SWn pins and the cell input pins are detectable. A shorted SWn pin can be detected by an acquisition with the relevant cell balancing switch off and then again with it on. If the SWn pin is not shorted to an adjacent cell input pin, no change in the measured value should be observed for the two cases. If the SWn

pin is shorted to the Cn pin, then the measured value will change by approximately 40-50% when the balancing switch is turned on based on the values of RBALANCE, and the balancing switch resistance. A short circuit from SWn to Cn-1 produces the same effect. By comparing both the VCELLn measurement value along with the VCELLn+1 and VCELLn-1 values, it is possible to deter-mine exactly where the short circuit is located.

Figure 45. SWn to Cn Short

Figure 46. SWn-1 to Cn Short

Cn-1

Cn

SWn-1

CELL #n

RFILTER

RFILTER

HVSWnRBALANCE

RBALANCE

TEST FOR SWn TO Cn SHORT CIRCUIT

CONDITION

CONTROLLED BYBALSWEN[n-1]

Cn-1

Cn

SWn-1

CELL #n

HVSWn

CONTROLLED BYBALSWEN[n-1]

TEST FOR SWn TO Cn SHORT CIRCUIT

CONDITIONRFILTER

RFILTER

RBALANCE

RBALANCE



Cn Leakage DiagnosticLeakage at the Cn inputs can cause the voltage seen by the ADC to be different than that at the voltage source due to the resistance of the external filter circuit. By utilizing an alternate measurement path, any voltage errors as a result of Cn pin leakage may be detected. The SWn pins are connected to the cell sources through an alternate path. Implementing an HVMUX connection from the SWn pins to the LSAMP completes the redundant measurement path. This alternate measurement path for the cell measure-ments can be enabled by setting the ALTMUXSEL bit of the DIAGCFG register. When this bit is set and a measurement cycle is started, all cell measurements are taken using the alternate path instead of the Cn pin HVMUX connections. Measurements taken with the normal and alternate paths can be compared and should be nearly identical for a system with no faults. Since the SWn pins typically have a smaller external filter time constant than the Cn pins, increasing the oversampling setting for this diagnostic measurement may be beneficial for reducing measurement noise when the measurement is taken while the cells are exposed to transient loads.

Cell Overvoltage DiagnosticEnabling balancing switches can be used to generate a voltage up to 2 x VCELL at the ALTMUX inputs to test the input range capability, assuming the cell is sufficiently charged.A cell-position input voltage is elevated by approximately 1.5 x VCELLn turning on either BALSWn+1 or BALSWn-1. When the adjacent switch is turned on, the SWn pin shared with the switch is moved by 0.5 x VCELL, which causes VCELLn to increase by that amount when mea-sured with the ALTMUX path. For the topmost cell posi-tion, BALSWn-1 must be used, and for the bottom cell position, BALSWn+1 must be used. By turning on two adjacent switches instead of one, such as BALSWn+1 and BALSWn+2, the measured voltage is approximately 2 x VCELL, assuming all cells are at approximately the same voltage. This technique can create an input voltage that exceeds the overvoltage threshold to verify the higher end of the input range and the overvoltage alert function. Input range can also be verified by using the cell-test sources to induce a higher cell channel voltage. If the change is as expected, it shows that the system can mea-sure voltages above the present nominal input voltage.

Figure 47. Redundant HVMUX Paths

SWn

SWn-1

Cn

AGND

Cn-1

RFILTER

RBALANCE

CFILTER

CELL n

RFILTER

RBALANCECFILTER

RBALFILTER

TO CELL n-1

TO CELL n+1

SENSE WIRE

SENSE WIRE

+

-

LSAMPTO ADC

HVMUXBUS

HVMUX BUS

ALTMUX BUS

ALTMUX BUS



Cell Undervoltage DiagnosticTurning on the balancing switch can be used to generate a near-zero voltage at any input channel to the ALTMUX path. By successfully measuring this near-zero voltage, the diagnostic verifies the lower-end of the input range and the undervoltage alert function. Input range can also be verified by using the cell-test sources to induce a lower-cell channel voltage. If the change is as expected, it shows that the system can mea-sure voltages below the present nominal input voltage.

ALRTHVUV Comparator DiagnosticThe ALRTHVUV comparator functionality can be verified by setting the CPEN bit (to disable the HV charge pump) and then discharging the external HV capacitor by performing an acquisition for 5ms (such as 12 cells, 32 oversamples), or by enabling using one or more of the cell-test current sources for an appropriate amount of time. The ALRTHVUV bit should be set after the voltage has decayed.

HVMUX Sequencer DiagnosticThe HVMUX control sequence can be checked using the sources attached to the Cn pins. The sources are con-trolled by the CTSTEN bits of the CTSTCFG register. The basic test method is as follows:

1) Perform an acquisition.2) Turn on a cell-test source.3) Wait for sufficient settling time.4) Perform an acquisition.5) Check that the cell(s) sharing the pin whose current

source was turned on had the expected measure-ment change and other cells had no changes.

6) Repeat steps 1–5 for other pins to confirm there are no logic errors in the HVMUX control sequencer.

The cell-test sources can be turned on for individual pins to create a detectable measurement variation that is deter-mined by the current source value and the series resis-tance of the cell input filter circuit. The settling time needed for a certain change in measurement value depends on the size of the external filter capacitors and the amplitude of the test-current source. A longer settling time gives the full-voltage change, while a shorter settling time saves test time and should still produce an easily detectable voltage difference. By detecting the expected measurement varia-tion for a given cell input pair and running a sequence of tests to cover all cases, the HVMUX sequencer operation is verified.

Figure 48. HVMUX Sequencer Diagnostic

Cn-1

CnRFILTER RHVMUX

CELL n

+

-

LSAMPTO ADC

VAA

AGND

TEST SOURCE

VAA

AGND

TEST SOURCE

AGND

AGND

TEST SOURCES CONTROLLED BY:CTSTENnCTSTSRCCTSTDAC

RFILTER RHVMUX



Figure 49. HVMUX Sequencer Diagnostic

STANDBY MODE; DBLBUF = 0

ENABLE VALID CELLS FOR MEASUREMENT

INITIATE ACQUISITION

STORE MEASUREMENT VALUES

SET TEST SOURCE CURRENT CTSTDAC[3:0] = 0xF

CTSTSRC = 0 FOR AGNDSET TEST SOURCE POLARITY

n = 12

WAIT FOR SETTLING TIME

CTSTENn = 0

NO

YES

FAIL

NO CHANGE EXCEPT VCELLn,

VCELLn-1

COMPARE ALL CELL MEASUREMENTS TO

SAVED VALUES

n = n-1

n = 1?

NO

YESPASS

INITIATE ACQUISITION

ENABLE CELL TEST CURRENT SOURCE n CTSTENn = 1

DISABLE CELL TEST CURRENT SOURCE

ONE APPS CIRCUIT R*C TIME



ALU DiagnosticThe ALU diagnostic utilizes the ADC test mode (ADCTSTEN = 1) to feed data from specific test registers directly into the ALU instead of from the ADC conversion. The host can write different data combinations to the test registers in this mode to provide test coverage for all ALU and data registers (CELLn, VBLKP, DIAG, and AUXINn) as well as all alerts that are based on the measurement data and the corresponding thresholds (e.g., overvoltage alerts).

The ADCTEST1x registers are used for all odd-numbered samples in oversampling mode as well as in single-sample acquisitions. The ADCTEST2x registers are used for all even-numbered samples (in oversampling mode). The A registers are used in lieu of the first conversion of each measurement and the B registers are used in lieu of the second conversion. After the acquisition, the host can read the measurement data registers and the alert regis-ters and compare the data to expected values to verify the ALU functionality.

Figure 50. ALU Diagnostic

ADC

BLOCK ALU

ALU1

ALUn

ALU12

ALU REGISTERS

VBLOCK REGISTER

CELL1 REGISTER

CELLn REGISTER

CELL12 REGISTER

USER REGISTER MAP

DATAMOVE TRIGGER

ADC IN -

ADC IN +

12

12

ADCTSTEN

12

14

14

14

14

RESET

LOADADCTEST1A[11:0]12

ADCTEST1B[11:0]12

12

ADC_CHOP

ADCTEST2A[11:0]12

ADCTEST2B[11:0]12

OVSAMP_EVEN_ODD

UART COMMUNICATION

AIN2 REGISTER

AIN1 REGISTER

12

12

DIAG ALU DIAG REGISTER14



AUXINn Open DiagnosticThe AUXINn open diagnostic can be used to detect if the AUXINn pin is open circuit. The diagnostic procedure is shown in Figure 51 and Figure 52.

Figure 51. AUXINn Open Diagnostic

Figure 52. AUXINn Open Diagnostic

AGND

AUXINn

THERMISTOR

RFILTER

CONTROLLED BY AUXINNTSTEN AND CTSTSRC

SET BY CTSTDAC[3:0]

VAA

AGND

TEST THIS NODE FOR AN OPEN CIRCUIT

TO LVMUX

t CFILTER

RRATIO

VTHRM


INITIALIZED

ENABLE APPROPRIATE INPUTS FOR

MEASUREMENT


SAVE ADC MEASUREMENT

RESULT

SET CTSTDAC[3:0] CURRENT SOURCE

VALUE

NO

YES

COMPARE ADC MEASUREMENT TO

SAVED VALUE

ALLVOLTAGES WITHIN

THRESHOLD?

OUT OF TOLERANCE INPUT HAS OPEN

CIRCUIT

TESTED INPUTS OK; REPEAT PROCEDURE FOR OTHER INPUTS

DETERMINE VOLTAGE CHANGE THRESHOLD BASED ON CURRENT

AND INPUT FILTER

SET AUXINNTSTEN TO ENABLE SOURCE


SELECT CTSTSRC TO SOURCE OR SINK

CURRENT



Calibration ROM DiagnosticThe CRC for the calibration ROM can be independently computed by the host. Any mismatch between the calcu-lated CRC and the factory CRC indicates that the mea-surement accuracy may be compromised. The factory CRC, ROMCRC[7:0], is stored in the ID2 register.

The CRC for the calibration ROM uses the same poly-nomial as the CRC-8 PEC byte and is performed on addresses C0h to CAh, CFh, ID1, and ID2 and processed in the order shown in Table 42, least-significant bit first. Registers CAL11, CAL12, CAL13, and CAL14 are exclud-ed from the calculation. Also, certain ROM bits must be zeroed prior to performing the calculation using the bit-wise AND masks in Table 42.

Table 42. CRC Bit MaskORDER ADDRESS NAME BIT-WISE AND MASK

1 0xC0 CAL0 0x003F

2 0xC1 CAL1 0x007F

3 0xC2 CAL2 0x3FFF

4 0xC3 CAL3 0xFFFF

5 0xC4 CAL4 0xFFFF

6 0xC5 CAL5 0xFFFF

7 0xC6 CAL6 0xFFFF

8 0xC7 CAL7 0x3F3F

9 0xC8 CAL8 0x003F

10 0xC9 CAL9 0x3FFF

11 0xCA CAL10 0x0003

12 0xCF CAL15 0x007F

13 0x0D ID1 0xFFFF

14 0x0E ID2 0x00FF



Applications InformationVehicle ApplicationsBattery cells can use various chemistries such as NiMH, Li-ion, SuperCap, or Lead-Acid. SuperCap cells are used in fast-charge applications such as energy storage for regenerative braking. An electric vehicle system may require a high-voltage battery pack containing up to 200 Li-ion cells or up to 500 NiMH cells.

A battery module is a number of cells connected in series that can be connected with other modules to build a high-voltage battery pack (see Figure 53). The modularity allows for economy, configurability, quick assembly, and serviceability. The minimum number of cells connected to any one device is limited by the device’s minimum operat-ing voltage. The 9V minimum for VDCIN usually requires at least two Li-ion, six NiMH, or six SuperCap cells per module.

Figure 53. Electric Vehicle System

VEHICLE 12V PWR

CELL STACK

BATTERY MANAGEMENT

SYSTEM(BMS)

VEHICLE CONTROLSYSTEM

(VCS)

VEHICLE GND

COMM BUS

COMM BUS

BATTERY PACK

PHASE 1

INVERTER

MAIN HV+ CONTACTORPLUG

PLUG MAIN HV- CONTACTOR

PHASE 2

PHASE 3

CHASSIS GROUND

M



Battery Management SystemsDaisy-Chain SystemA daisy-chain system employs a single data link between the host and all the battery modules. The daisy-chain method reduces cost and requires only a single isolator between the lowest module and the host.

Figure 54. Daisy-Chain System

SLAVEMONITOR

ANDCONTROL

BATTERY MODULE

TEMP

SLAVEMONITOR

ANDCONTROL

BATTERY MODULE

TEMP

SLAVEMONITOR

ANDCONTROL

BATTERY MODULE

TEMP

MICRO-ΩSHUNT

INVERTER-

VEHICLE COMM BUS

CHASSIS GROUND

MAIN HV- CONTACTOR

GROUND FAULT CHECK

MASTERCONTROLLER

BATTERY PACK HVAC

COMMUNICATION ISOLATION

INVERTER+MAIN HV+

CONTACTOR



Distributed-Module CommunicationA distributed-module system employs a separate data link and isolator between each battery module and the host with an associated increase in cost.

Figure 55. Distributed System

ISOLATOR

CURRENTSENSE

PACK SWITCHESINVERTER-

FAULT CHECK

MASTERCONTROLLER

VEHICLE GNDCOMM BUS

PACK SWITCHESINVERTER+

SLAVEMONITOR

ANDCONTROL

BATTERY MODULE

TEMP

ISOLATOR

SLAVEMONITOR

ANDCONTROL

BATTERY MODULE

TEMP

ISOLATOR

SLAVEMONITOR

ANDCONTROL

BATTERY MODULE

TEMP

ISOLATOR

SLAVEMONITOR

ANDCONTROL

BATTERY MODULE

TEMP



Combining MAX17823H and MAX17880 DevicesThe MAX17823H can be used stand-alone or in conjunc-tion with the MAX17880. For systems containing both types of devices, the simplest implementation is to segre-gate them into two separate daisy chains. The separate daisy-chains increase the reliability and simplify device addressing. However, if the system employs only a single daisy-chain, the companion devices must coexist in the same daisy-chain. To mitigate any potential addressing conflicts, the battery-management UART protocol allows the host to create a separate address space for each type of device. The host creates the separate address spaces during initialization of the daisy-chain. The host issues separate HELLOALL commands for each type of device using 57h for MAX17823H and A7h for MAX17880. Each type of device will ignore the HELLOALL command intended for the other type. While it does not matter which HELLOALL command is issued first, the host must ascertain the address returned from the first HELLOALL command, which is the last device address incremented by one. That value can then be used as the first address sent with the second HELLOALL command. In this manner, separate address spaces are created for each type of device.

Acquisition Latency for Daisy-Chain SystemsA maximum 3-bit delay (1.5µs at 2Mbps) is incurred as any command propagates through each daisy-chained device. For example, for an 8-device stack, a maximum 12µs delay is incurred. This allows all eight acquisitions to occur within 12µs of each other.

Power-Supply ConnectionBoth internal and external protection circuits permit the device to derive its supply directly from the battery module voltage. The circuits protect against transients such as those that occur when the battery voltage is first connect-ed to the device, when the vehicle inverter is connected to the battery stack, or during charge/discharge transitions such as regenerative braking. The internal circuits include 72V-tolerant battery inputs and a high noise rejection ratio (PSRR) for the internal low-voltage regulator.

The external protection circuit shown in Figure 56 filters and clamps the DCIN input. During negative voltage tran-sients, the filter capacitor maintains power to the device through the transient.For maximum measurement accuracy, dedicated wires separate from the cell-sense wires should be used for the power-supply connection (Kelvin sense). This is to elimi-nate voltage drops in the sense wires induced by supply current. If the application can tolerate the induced error, the supply wires can serve as the sense wires to reduce the wire count.

Connecting Cell InputsIf the battery stack contains less than 12 cells, the lowest-order inputs (e.g., C1 and C0) should be utilized first and connected to the lowest common-mode signals. Any unused cell inputs should be shorted together and any unused switch inputs should be shorted together. The TOPCELL register must also be configured for stacks with less than 12 cells to mask out any false alerts correspond-ing to the unused channels.

External Cell BalancingThe cell-balancing current can be switched by external transistors if more power dissipation is required. The internal switches can be used to switch the external tran-sistors; the power is limited by external current-limiting resistors.

Figure 56. Power-Supply Connection

DCIN

MODULE+

D80SMCJ58A

C802.2µF 100V

R80100Ω



External Cell-Balancing Using FET SwitchesAn application circuit for cell-balancing that employs FET switches is shown in Figure 57. QBALANCE is selected for low VT that meets the minimum VCELLn requirements of the application during balancing. DGATE protects QBALANCE from reverse VGS voltage during a hot-plug event. RGATE protects the device by limiting the hot-plug inrush current. CGATE can be added to attenuate transient noise coupled from the drain to the gate to maintain the transistor bias. The cell-balancing current is limited by RBALANCE. A list of FET balancing components is shown in Table 43.

Figure 57. External Balancing (FET)

Table 43. FET Balancing Components


TO ALTMUX

TO ALTMUXSWn

SWn-1

Cn

AGND

Cn-1

BALSWn

RFILTER

RBIAS

CFILTER

CELL n

RFILTER

RBALANCE

CFILTER

CBALFILTER

TO HVMUX

TO HVMUX

TO CELL n-1

TO CELL n+1

SENSE WIRE

SENSE WIRE

RBIAS

RGATE

DGATEQBALANCE

CGATE

COMPONENT NAME TYPICAL VALUE OR PART FUNCTION

RBIAS 1kΩ Voltage-divider for transistor bias

RGATE 100Ω Hot-plug current-limiting resistor

DGATE S1B Reverse-voltage gate protection

CGATE 1nF Transient VGS suppression

RBALANCE per application Balancing current-limiting resistor

QBALANCE SQ2310ES External switch



External Cell Balancing Using BJT SwitchesAn application circuit for cell balancing that employs BJT switches is shown in Figure 58. QBALANCE is selected for power dissipation based on the IB drive current available and the cell-balancing current. DBASE protects QBALANCE from negative VGS during hot-plug events. RBASE protects the device by limiting the hot-plug inrush current. The cell-balanc-ing current is limited by RBALANCE. A list of BJT balancing components is shown in Table 44.

Figure 58. External Cell Balancing (BJT)

Table 44. BJT Balancing Components


TO ALTMUX

TO ALTMUXSWn

SWn-1

Cn

AGND

Cn-1

BALSWn

RFILTER

RBIAS

CFILTER

CELL n

RFILTER

RBALANCE

CFILTER

CBALFILTER

TO HVMUX

TO HVMUX

TO CELL n-1

TO CELL n+1

SENSE WIRE

SENSE WIRE

RBIAS

RBASE

DBASE

QBALANCE

CBASE

COMPONENT NAME TYPICAL VALUE OR PART FUNCTION

RBIAS 22Ω Voltage-divider for transistor bias

RBASE 15Ω Hot-plug current-limiting resistor

DBASE S1B Reverse emitter-base voltage protection

CBASE 1nF Transient VBE suppression

RBALANCE per balancing current requirements Balancing current-limiting resistor

QBALANCE NST489AMT1 External switch



External Cell-Balancing Short-Circuit DetectionA short-circuit fault in the external balancing path results in continuous current flow through RBALANCE and QBALANCE. To detect this fault, the voltage drop across the sense-wire parasitic resistance must be measurable. A very small series resistor can added for this purpose.

UART InterfaceThe UART pins also employ both internal and external cir-cuits to protect against noise. The recommended external filters are shown in Figure 59. ESD protection is shown in Figure 59 and Figure 60.

Figure 59. UART Connection

TXLN

TXLP

R4447Ω

R4547Ω

RXUN

RXUP

GNDL

C502.2nF 600V

C512.2nF 600V

C5215pF

C5315pF

R52100kΩ

R53100kΩ

DAISY-CHAIN DEVICE (n) DAISY-CHAIN

DEVICE (n-1)

SIGNAL TRACES OR WIRE HARNESS

TXUN

TXUP

R5047Ω

R5147Ω

RXLN

RXLP

C422.2nF 600V

C432.2nF 600V

C4015pF

C4115pF R42

100kΩR43100kΩ SIGNAL TRACES OR

WIRE HARNESS

R541.5kΩ

R551.5kΩ

R401.5kΩ

R411.5kΩ

GNDL



High-Z Idle ModeThe high-Z idle mode lowers radiated emissions from wire harnesses by minimizing the charging and discharging of the AC-coupling capacitors when entering and exiting the idle mode. The application circuit shown in Figure 61 uses a weak resistor-divider to bias the TX lines to VDDL during the high-Z idle period and pnp transistor clamps to limit the maximum voltage at the TX pins during high noise injection. The resistor-divider and pnp clamps are not needed for applications utilizing only the low-Z mode. The low-Z and high-Z idle modes both exhibit a similar immunity to noise injection. Low-Z mode may be pre-

ferred for ports driving inductive loads to minimize ringing. See Figure 60 for a high-Z idle mode application circuit.

UART Supplemental ESD ProtectionThe UART ports may require supplemental protection to meet IEC 61000-4-2 requirements for contact discharge. The recommended circuits to meet ±8kV protection levels are shown in Figure 61 and Figure 62. The protection components should be placed as near as possible to the signal’s entry point on the PCB.

Figure 60. High-Z Idle Mode Application Circuit

Figure 61. External ESD Protection for UART TX Ports

TX[U,L]N

TX[U,L]P

GNDL[2,3]

VAAFMB3906

TO REST OF TX CIRCUIT OR RX CIRCUIT

R4447Ω

R4547Ω

R4710kΩ

R4910kΩ

R4610kΩ

R4810kΩ

VDDL[2,3]

TXN

TXP47Ω

47Ω

GNDL

TO RECEIVER

PESD1CAN



Single-Ended RX ModeTo configure the lower port for single-ended RX mode, the RXLP input is connected to digital ground and the RXLN input receives the inverted signal, just as it does for differential mode. If the host cannot transmit inverted data then the signal must be inverted as shown in Figure 63. Transmitter operation is not affected. If the upstack device is single-ended then only the TXUN signal is required. Note: In single-ended mode, SHDNL must be driven externally.

Figure 62. External ESD Protection for UART RX Ports

Figure 63. Application Circuit for Single-Ended Mode

RXN

RXP

GNDL

2.2nF 600V

2.2nF 600V

15pF50V

15pF50V

100Ω

100kΩ 100kΩ

100Ω

PESD1CAN

FROM TRANSMITTER

1.5kΩ

1.5kΩ

RXLP

RXLN

GNDL

Cf15pF

Rf1.5kΩ

UART DATA

ISOLATED OR NON-ISOLATED INVERTING LOGIC DRIVER



UART IsolationThe UART is expected to communicate reliably in noisy high-power battery environments where both high dV/dt supply noise and common-mode current injection induced by electromagnetic fields are prevalent. Common-mode currents can also be induced by parasitic coupling of the system to a reference node such as a battery or vehicle chassis. The daisy-chain physical layer is designed for maximum noise immunity.The AC-coupled differential communication architecture has a ±30V common-mode range and +6V differential swing. This range is in addition to the static common-mode voltage across the AC-coupling capacitors between modules. Transmitter drivers have low internal imped-ance and are source-terminated by the application circuit so that impedances are well-matched in the high- and low-driver states. This architecture minimizes differential noise induced by common-mode current injection. The receiver inputs are filtered above the fundamental com-munication frequency to prevent high-frequency noise from entering the device. The system is designed for use with isolation transformers or optocouplers to provide an even higher degree of common-mode noise rejection in

circuit locations where extremely large common-mode noise is present, such as between vehicle chassis and the high-voltage battery pack terminals.Since a mid-pack service-disconnect safety switch is present in many battery packs, the device is designed to communicate with the entire daisy-chain whether the service-disconnect switch is engaged or open. This is possible with daisy-chains that employ capacitor isolation.

UART Transformer IsolationThe UART ports can be transformer-coupled because of their DC-balanced differential design (see Figure 64). Transformer coupling between the MAX17841B inter-face and the MAX17823H provide excellent isolation and common-mode noise rejection. The center-tap of a signal transformer can be used to enhance common-mode rejection by AC-coupling the node to local ground. Common-mode currents that are able to pass through the parasitic coupling of the primary and secondary are shunted to ground to make a very effective common-mode noise filter.

Figure 64. UART Transformer Isolation

15pF

15pF

1.5kΩ

1.5kΩ

RXLP

RXLN

GNDL

TXN

TXP47Ω

47Ω

MAX17841 DAISY-CHAIN DEVICE 1

GNDL

1nF

SIGNAL TRACES OR WIRE HARNESS



UART Optical IsolationThe daisy-chain can use optical isolation instead of transformer or capacitor isolation (see Figure 65).

Device Initialization SequenceImmediately after reset, all device addresses are set to 0x00 and the UART baud rate and receive modes have not been auto-detected; therefore, the following initialization sequence is recommended after every reset or after any change to the hardware configuration (see Figure 66):

Figure 65. UART Optical Isolation

Figure 66. Device Initialization Sequence

RXLP

RXLN

GNDL

CFILTER15pF

RFILTER4.7kΩ

VAA

FROM UART DATA SOURCE

ACPL-M72T

3.3V

TO UART DATA SOURCE

ACPL-M72T

TXLNROPTO

DEVICE(s) IN SHUTDOWN MODE

ADDRESSES AS EXPECTED?

YES

PEC ERRORS?

NO

DEVICE COMMUNICATION

INITIALIZED

ADDRESSING ERROR

COMMUNICATION FAULT OR ADDRESSING

ERROR

YESNO

HOST SENDS PREAMBLES FOR 2ms PER DEVICE TO WAKE

UP DAISY-CHAIN

HOST SELECTS FIRST ADDRESS AND SENDS

HELLOALL

HOST RECEIVED PREAMBLE?

YES

FAULT OR NOT ENOUGH PREAMBLES

SENT

WRITEALL FA[4:0] (IF FIRST ADDRESS

USED ≠ 0)NORETURN ADDRESS

AS EXPECTED?

YES

FAULT OR DEVICE COUNT ERROR

READALL ADDRESS REGISTERS

NO



After the daisy-chain is initialized, each device should be configured for operation as follows:1) Perform a READALL of the status registers.

• The ALRTRST bit should be set in all devices to sig-nify that a reset occurred.

• Check for other unexpected alerts.2) Clear the ALRTRST bit on each device so that future

unintended resets can be detected.3) Change configuration registers as necessary with

WRITEALL commands:• Configure the alert enables and alert thresholds as

required by the application.• Configure the acquisition mode.

4) Perform all necessary key-on diagnostics.5) Start the acquisition cycle.6) Continuously monitor diagnostic and alert status bits.7) Periodically perform additional diagnostics, as

required by the application.

Error Checking Data integrity is provided by Manchester encoding, par-ity, character framing, and packet-error checking (PEC). The combination of these features verify stage-to-stage communication both in the write and read directions with a hamming distance(HD) value of 6 for commands with a length up to 247 bits (counted prior to Manchester encoding and character framing). This is equivalent to the longest possible command packet for a daisy-chain of up to 13 devices. The data-check byte is present in the READALL and READDEVICE commands to verify the entire command propagated without errors. Using the

data-check and PEC bytes, complete transaction integrity for READALL and READDEVICE command packets can be verified.

PEC ErrorsIf the device receiver receives an invalid PEC byte, the ALRTPEC bit is set in the STATUS register. A device does not execute any write command unless the received PEC matches the calculated PEC, so to verify the write com-mand execution, the host should perform a READALL to verify the contents of the written register.For returned read packets, the host should store the received data, perform the PEC calculation, and compare the results to the received PEC byte before consider-ing the data to be valid. To support PEC, the host must implement a CRC-8 (8-bit cyclic redundancy check) encoding and decoding algorithm based on the following polynomial:

P(x) = x8 + x6 + x3 + x2 + 1The host uses the algorithm to process all bytes received in the command packet prior to the PEC byte itself. Neither the PEC nor the alive-counter bytes are part of the calculation. The bits are processed in the order they are received, LSB first. A byte-wise pseudocode algorithm is shown in Figure 68, but lookup table solutions are also possible to reduce host calculation time. For commonly issued command packets, the host can pre-calculate (hard-code) the PEC byte. For commonly used partial packets, the CRC value of a partial calcula-tion can be used as the initial value for a subsequent run-time calculation (see Figure 67).

Figure 67. CRC Calculation

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

INPUT DATA BITSTREAM (LSB FIRST)



Figure 68. PEC Calculation Pseudocode

Function PEC_Calculation(ByteList(), NumberOfBytes, CRCByte) // CRCByte is initialized to 0 for each ByteList in this implementation, where // ByteList contains all bytes of a single command. It is passed into the // function in case a partial ByteList calculation is needed.

// Data is transmitted and calculated in LSb first format // Polynomial = x^8+x^6+x^3+x^2+1 POLY = &HB2 // 10110010b for LSb first

//Loop once for each byte in the ByteList For ByteCounter = 0 to (NumberOfBytes – 1) ( //Bitwise XOR the current CRC value with the ByteList byte CRCByte = CRCByte XOR ByteList(Counter1)

//Process each of the 8 CRCByte remainder bits For BitCounter = 1 To 8 ( // The LSb should be shifted toward the highest order polynomial // coefficient. This is a right shift for data stored LSb to the right // and POLY having high order coefficients stored to the right.

// Determine if LSb = 1 prior to right shift If (CRCByte AND &H01) = 1 Then // When LSb = 1, right shift and XOR CRCByte value with 8 LSbs // of the polynomial coefficient constant. “/ 2” must be a true right

// shift in the target CPU to avoid rounding problems. CRCByte = ((CRCByte / 2) XOR POLY) Else //When LSb = 0, right shift by 1 bit. “/ 2” must be a true right

// shift in the target CPU to avoid rounding problems. CRCByte = (CRCByte / 2) End If

//Truncate the CRC value to 8 bits if necessary CRCByte = CRCByte AND &HFF

//Proceed to the next bit Next BitCounter )

//Operate on the next data byte in the ByteList Next ByteCounter )

// All calculations done; CRCByte value is the CRC byte for ByteList() and // the initial CRCByte value Return CRCByte



Register MapADDRESS POR NAME DESCRIPTION

0x00 8236h VERSION Device model and version

0x01 0000h ADDRESS Device addresses

0x02 8000h STATUS Status flags

0x03 0000h FMEA1 Failure mode flags 1

0x04 0000h ALRTCELL Voltage-fault alert flags

0x05 0000h ALRTOVCELL Overvoltage alert flags

0x07 0000h ALRTUVCELL Undervoltage alert flags

0x08 0000h ALRTBALSW Balancing switch alert flags

0x0A 0F0Fh MINMAXCELL Cell number for the highest and lowest voltages measured

0x0B 0000h FMEA2 Failure mode flags 2

0x0D XXXXh ID1 Device ID 1

0x0E XXXXh ID2 Device ID 2

0x10 0002h DEVCFG1 Device configuration 1

0x11 0000h GPIO GPIO status and configuration

0x12 0000h MEASUREEN Measurement enables

0x13 0000h SCANCTRL Acquisition control and status

0x14 0000h ALRTOVEN Overvoltage-alert enables

0x15 0000h ALRTUVEN Undervoltage-alert enables

0x18 0000h TIMERCFG Timer configuration

0x19 0000h ACQCFG Acquisition configuration

0x1A 0000h BALSWEN Balancing-switch enables

0x1B 0000h DEVCFG2 Device configuration 2

0x1C 0000h BALDIAGCFG Balancing diagnostic configuration

0x1D 0000h BALSWDCHG Balancing-switch discharge configuration

0x1E 000Ch TOPCELL Top-cell configuration

0x20 0000h CELL1 Cell 1 measurement result









Register Map (continued)ADDRESS POR NAME DESCRIPTION




0x2A 0000h CELL11 Cell 11 measurement result

0x2B 0000h CELL12 Cell 12 measurement result

0x2C 0000h BLOCK Block-measurement result

0x2D 0000h AIN1 AUXIN1 measurement result

0x2E 0000h AIN2 AUXIN2 measurement result

0x2F 0000h TOTAL Sum of all cell measurements

0x40 FFFCh OVTHCLR Cell overvoltage-clear threshold

0x42 FFFCh OVTHSET Cell overvoltage-set threshold

0x44 0000h UVTHCLR Cell undervoltage-clear threshold

0x46 0000h UVTHSET Cell undervoltage-set threshold

0x48 FFFCh MSMTCH Cell-mismatch threshold

0x49 0000h AINOT AUXIN overtemperature threshold

0x4A FFF0h AINUT AUXIN undertemperature threshold

0x4B 0000h BALSHRTTHR Balancing switch diagnostic, short-circuit threshold

0x4C 0000h BALLOWTHR Balancing switch diagnostic, on-state low threshold

0x4D 0000h BALHIGHTHR Balancing switch diagnostic, on-state high threshold

0x50 0000h DIAG Diagnostic measurement result

0x51 0000h DIAGCFG Diagnostic configuration

0x52 0000h CTSTCFG Test-source configuration

0x57 0000h ADCTEST1A User-specified data for ALU diagnostic

0x58 0000h ADCTEST1B User-specified data for ALU diagnostic

0x59 0000h ADCTEST2A User-specified data for ALU diagnostic

0x5A 0000h ADCTEST2B User-specified data for ALU diagnostic



Version Register (address 0x00)

BIT POR NAME DESCRIPTION

D15

823h MOD[11:0] Model number. Always reads 823h.

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

7h VER[3:0]

Die version per table below:

D2 VERSION VER[3:0]

D1 MAX17823H 7h

D0

MAX17823B 6h

MAX17823A 5h

MAX17823A 4h

MAX17823 3h

MAX17823 2h

MAX17823 1h



ADDRESS Register (address 0x01)


D15

0 Reserved Always reads logic-zero.D14

D13

D12

0 FA[4:0]

Address of the device connected to the host (first address). If the host uses a first address other than 0x00 in the HELLOALL command, then the host must write that first address to all devices in the daisy-chain with a WRITEALL command. READALL commands require that FA[4:0] and DA[4:0] be correct in order for the data check and PEC features to function as intended.

D11

D10

D9

D8

D7


D5

D4

0 DA[4:0]

Device address written by the HELLOALL command as it propagates up the daisy-chain and is automatically incremented for each device. The host must choose a first address so that the last device address will not exceed the maximum address of 0x1F during the HELLOALL command. Writing has no effect except with a HELLOALL command while ADDRUNLOCK = 1.

D3

D2

D1

D0



STATUS Register (address 0x02)BIT POR NAME DESCRIPTION

D15 1 ALRTRST Indicates a power-on-reset event occurred. Clear after power-on and after a successful HELLOALL to detect future resets. Writing to a logic-one has no effect.

D14 0 ALRTOV Bit-wise logical OR of ALRTOVCELL[15:0]. Read-only.

D13 0 ALRTUV Bit-wise logical OR of ALRTUVCELL[15:0]. Read-only.

D12 0 ALRTSHDNL Indicates VSHDNL < VIL. Read during shutdown diagnostic when VAA > VPORFALL. Cleared by writing to logic-zero or POR. Writing to a logic-one has no effect.

D11 0 ALRTSHDNLRT Indicates VSHDNL < VIL. Read during shutdown diagnostic when VAA > VPORFALL.Read-only.

D10 0 ALRTMSMTCH Indicates VMAX - VMIN > VMSMTCH. Cleared at next acquisition if the condition is false. Read-only.

D9 0 ALRTTCOLD Logical OR of ALRTOVAIN0 and ALRTOVAIN1. Read-only.

D8 0 ALRTTHOT Logical OR of ALRTUVAIN0 and ALRTUVAIN1. Read-only.

D7 0 ALRTPEC Indicates a received character contained a PEC error. Cleared only by writing to logic-zero. Writing to a logic-one has no effect.

D60 Reserved Always reads logic-zero.

D5

D4 0 ALRTMAN Indicates that a character received by the lower UART contained a Manchester error. Cleared only by writing to logic-zero. Writing to a logic-one has no effect.

D3 0 0 Write ignored, Read back ‘0’.

D2 0 ALRTPAR Indicates that a character received by the lower UART contained a parity error. Cleared only by writing to logic-zero. Writing to logic-one has no effect.

D1 0 ALRTFMEA2 Bit-wise logical OR of FMEA2[15:0]. Read-only.

D0 0 ALRTFMEA1 Bit-wise logical OR of FMEA1[15:0]. Read-only.



FMEA1 Register (address 0x03)


D15 0 ALRTOSC1Indicates that the 32kHz oscillator frequency is not within ±5% of its expected value. The status is updated every two cycles (32kHz). Cleared only by writing to logic-zero. Writing to a logic-one has no effect.

D14 0 ALRTOSC2 Same as ALRTOSC1 (redundant alert). Cleared only by writing to logic-zero. Writing to a logic-one has no effect.

D13 0 0 Always reads logic-zero.

D12 0 ALRTCOMMSEU1Indicates that the UART has placed the upper-port receiver in single-ended mode based on the first preamble received after POR. This bit is not set until the ALRTRST bit is cleared. Read-only.

D11 0 ALRTCOMMSEL1Indicates that the UART has placed the lower-port receiver in single-ended mode based on the first preamble received after POR. This bit is not set until the ALRTRST bit is cleared. Read-only.

D10 0 ALRTCOMMSEU2 Same as ALRTCOMMSEU1 (redundant alert) except that it sets before ALRTRST is cleared. Read-only.

D9 0 ALRTCOMMSEL2 Same as ALRTCOMMSEL2 (redundant alert) except that it sets before ALRTRST is cleared. Read-only.

D8 0 ALRTVDDL3 Indicates VDDL3 < VVDDL_OC. This bit is not set until the ALRTRST bit is cleared and cleared only by writing to logic-zero. Writing to a logic-one has no effect.


D6 0 ALRTGNDL2 Indicates an open circuit on the GNDL2 pin. This bit is not set until the ALRTRST bit is cleared and cleared only by writing to logic-zero. Writing to a logic-one has no effect.

D5 0 ALRTBALSW Bit-wise logical OR of ALRTBALSW[15:0]. Read-only.

D4 0 ALRTTEMPIndicates that TDIE > 115°C (120°C typical) or that the diagnostic measurement did not have sufficient settling time (< 50µs) and therefore may not be accurate. Cleared only by writing to logic-zero. Writing to a logic-one has no effect.

D3 0 ALRTHVUV Indicates VHV < VHVUV. This bit is not set until the ALRTRST bit is cleared and cleared only by writing to logic-zero. Writing to logic-one has no effect.






ALRTCELL Register (address 0x04)

ALRTOVCELL Register (address 0x05)

BIT POR NAME DESCRIPTIOND15

0 Reserved Always reads logic-zero.D14D13 0 ALRTAIN1 Logical OR of ALRTOVAIN1 and ALRTUVAIN1. Read-only.D12 0 ALRTAIN0 Logical OR of ALRTOVAIN0 and ALRTUVAIN0. Read-only.D11

0 ALRTCELL [12:1] ALRTCELL[n] is the logical OR of ALROVCELL[n] and ALRTUVCELL[n]. Read-Only.

D10D9D8D7D6D5D4D3D2D1D0



D13 0 ALRTOVAIN1 Indicates VAIN1 > AINUT (cold). Cleared at next acquisition if the condition is false. Read-only.

D12 0 ALRTOVAIN0 Indicates VAIN0 > AINUT (cold). Cleared at next acquisition if the condition is false.Read-only.

D11

0 ALRTOV[12:1] ALRTOV[n] indicates VCELLN > VOV (OVTHRSET threshold) if ALRTOVEN[n] = 1. Cleared at next acquisition if the condition is false. Read-only.




ALRTUVCELL Register (address 0x07)

ALRTBALSW Register (address 0x08)



D13 0 ALRTUVAIN1 Indicates VAIN1 < AINOT (hot). Cleared at next acquisition if the condition is false.Read-only.

D12 0 ALRTUVAIN0 Indicates VAIN0 < AINOT (hot). Cleared at next acquisition if the condition is false.Read-only.

D11

0 ALRTUV[12:1] ALRTUV[n] indicates VCELLn < VUV (UVTHRSET threshold) if ALRTUVEN[n] = 1. Cleared at next acquisition if the condition is false. Read-only.



0 Reserved Always reads logic-zero.D14D13D12D11

0 ALRTBALSW [11:0]

ALRTBALSW[n] indicates the corresponding measurement result exceeds the threshold specified by BALSWDIAG[2:0]. Cleared at next acquisition if the condition is false. Read-only.




MINMAXCELL Register (address 0x0A)

FMEA2 Register (address 0x0B)



Fh MAXCELL[3:0]Cell number of the maximum cell voltage currently in the measurement registers. If multiple cells have the same maximum value, this field contains the highest cell number with that measurement. Read-only.

D10D9D8D7


Fh MINCELL[3:0]Cell number of the minimum cell voltage currently in the measurement registers. If multiple cells have the same minimum value, this field contains the highest cell number with that measurement. Read-only.

D2D1D0


D15

0 Reserved Always reads logic-zero.

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2 0 ALRTHVHDRM Indicates that VHV - VC12 was too low during the acquisition for an accurate measurement. Cleared only by writing to logic-zero. Writing to a logic-one has no effect.

D1 0 Reserved Always reads logic-zero.

D0 0 ALRTHVOV Indicates that VHV - VDCIN > VHVOV. This bit is not set until the ALRTRST bit is cleared and cleared only by writing to logic-zero. Writing to a logic-one has no effect.



ID1 Register (address 0x0D)

ID2 Register (address 0x0E)


xxxxh DEVID[15:0] The two least-significant bytes of the 24-bit factory-programmed device ID. A valid device ID has two or more bits set to logic-one. Read-only.

D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0


xxh ROMCRC[7:0] 8-bit CRC value computed from the onboard read-only memory. Read-only.

D14D13D12D11D10D9D8D7

xxh DEVID[23:16] Most-significant byte of the 24-bit factory-programmed device ID. A valid device IDhas two or more bits set to logic-one. Read-only.

D6D5D4D3D2D1D0



DEVCFG1 Register (address 0x10)


D15

0 Reserved Reads back the written value.

D14

D13

D12

D11

D10

D9

D8

D7 0 FORCEPOR Enables hard POR by pulling down SHDNL internally. If cleared before the POR occurs, it will disable the active pulldown on SHDNL.

D6 0 ALIVECNTEN Enables inclusion of alive-counter byte at end of all write and read packets.

D5 0 ADCTSTEN Enables the ALU test mode. This mode feeds 12-bit data from the ADCTEST registers directly into the ALU instead of from the ADC conversion.

D4 0 SCANTODIS Disables the acquisition watchdog but does not clear the SCANTIMEOUT flag in the SCANCTRL register if it is set.

D3 0 DBLBUFEN

Enables the double-buffer mode. This mode automatically transfers data from the ALU to the data registers at the start of the next acquisition instead of at the end of the acquisition. This mode can be used in conjunction with the DATAMOVE bit so the host can start an acquisition and then start reading the previous acquisition (during the current acquisition), even if the read cycle takes longer than the acquisition.

D2 0 NOPEC Disables packet-error checking (PEC).

D1 1 ADDRUNLOCK Disables write-protection of device address DA[4:0]. Cleared only by HELLOALL command (write-protected).

D0 0 SPOR Enables soft POR. Writing to a logic-zero has no effect. Always reads logic-zero.



GPIO Register (address 0x11)

MEASUREEN Register (address 0x12)


0 DIR[3:0] Setting DIR[n] enables GPIOn as an output. Default state is high-impedance input.D14D13D12D11

0 RD[3:0]Indicates the current logic state of each GPIOn pin input buffer. The logic state is sampled at the end of the parity bit of the register address byte during a read of this register. Read-only.

D10D9D8

D7 0 GPIO3TMR

Enables the GPIO3 timer mode. This mode overrides DIR[3] and DRV[3] and drives GPIO3 to logic-one when the timer is counting, and drives to logic-zero when the timer times out. Emergency-discharge mode (EMGCYDCHG=1) automatically enables the GPIO3 timer mode.

D60 Reserved Always reads logic-zero.D5

D4D3

0 DRV[3:0] Setting DRV[n] sets GPIOn to logic-one if DIR[n] is set.D2D1D0


D15 0 BLKCONNECT Connects the voltage-divider to the VBLKP pin. Must be enabled prior to theVBLOCK measurement.

D14 0 BLOCKEN Enables measurement of the VBLKP input in the acquisition mode.D13 0 AIN2EN Enables measurement of the AUXIN2 input in the acquisition mode.D12 0 AIN1EN Enables measurement of the AUXIN1 input in the acquisition mode.D11

0 CELLEN[12:1] Enables measurement of the respective cell in the acquisition mode. Disabledchannels result in a measurement value of 0000h.




SCANCTRL Register (address 0x13)


D15 0 SCANDONEIndicates the acquisition has completed. Cleared only by writing it to logic-zero to detect completion of the next acquisition. Writing to logic-one has no effect. A new acquisition will not commence if this bit is set.

D14 0 SCANTIMEOUT

Indicates the acquisition did not complete in the expected period of time. The timeout depends on the oversampling configuration. Cleared only by writing it to logic-zero to allow detection of future timeout events. The acquisition watchdog can be disabled by setting SCANTOEN in the DEVCFG1 register.

D13 0 DATARDY

Indicates the measurement data from the acquisition has been transferred from the ALU to the data registers and may now be read. Data for all measurement registers and MIN/MAX/TOTAL is transferred at the same time. Cleared by writing it to logic-zero to allow detection of the next data transfer. Writing to logic-one has no effect.


D11

D10

0 BALSWDIAG [2:0]

Configures the cell-balancing switch diagnostic modes per table below. When selected, these modes effectively override the BALSWEN, MEASUREEN, ALTMUXSEL, and POLARITY configurations during the acquisition mode and update the ALRTBALSW register per the BALHIGHTHR and BALLOWTHR thresholds. Refer to Diagnostic section for details.

D9

D8

BALSWDIAG[2:0] DIAGNOSTIC TEST

000 None

001 Balancing Switch Short

010 Balancing Switch Open

011 None

100 None

101 Cell Sense Open Odds

110 Cell Sense Open Evens

111 None

D7 0 POLARITY Enables bipolar mode for ADC (input range is -2.5V to 2.5V). Default is unipolar mode (input range is 0 to 5V)



SCANCTRL Register (address 0x13) (continued)


0 OVSAMPL[2:0]

Configures for the number oversamples in the acquisition per table below: D5

D4

OVSAMPL [2:0] OVERSAMPLES000 1001 4010 8011 16100 32101 64110 128111 128

D3 0 0 Always reads logic-zero.

D2 0 SCANMODE Enables top-down scan mode. Default is pyramid scan mode.

D1 0 DATAMOVEInitiates transfer of measurement data from ALU to data registers (manual transfer) and sets DATARDY. ALU data is preserved until a new acquisition is started. Always reads logic-zero. Ignored in acquisition mode.

D0 0 SCANEnables the acquisition mode and (if in double-buffer mode) transfers previous acquisition data from ALU to data registers. Acts as a strobe bit and therefore does not need to be cleared. Always reads logic-zero. Ignored in acquisition mode.

ALRTOVEN Register (address 0x14)


0 Reserved Always reads logic-zero.D14D13 0 AINOVALRTEN1 Enables the AIN1 overvoltage alertD12 0 AINOVALRTEN0 Enables the AIN0 overvoltage alertD11

0 OVALRTEN [12:1]

Enables the overvoltage alert for the respective cell. Clearing also clears the associated cell alert.




ALRTUVEN Register (address 0x15)



D14

D13 0 AINUVALRTEN1 Enables the AIN1 undervoltage alert

D12 0 AINUVALRTEN0 Enables the AIN0 undervoltage alert

D11

0 UVALRTEN [12:1]

Enables the undervoltage alert for the respective cell. Clearing also clears the associated cell alert.

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0



WATCHDOG Register (address 0x18)

BIT POR NAME DESCRIPTIOND15 0 Reserved Always reads logic-zero.

D14

0 CBPDIV[2:0]

Sets the step size of the cell-balancing timer LSB per table below:

D13 CBPDIV[2:0] STEP SIZE TIMEOUT RANGE

D12

000 Disabled No timeout

001 1s 1–15s

010 4s 4–60s

011 16s 16–240s

100 64s 64–960s

101 128s 128–1920s

110 256s 256–3840s

111 256s 256–3840s

D11

0 CBTIMER[3:0]

Watchdog timer for the cell-balancing switches. The timer counts down at a rate set by CBPDIV. When the timer reaches 0, all cell-balancing switches are disabled by a signal separate from the BALSWEN bits. The timer should be periodically rewritten with a timeout value to keep the cell balancing switches enabled. When the timer value is read, the value reported is latched during the stop bit time following the ACQCFG UART register address of the READALL command. If the GPIO3TMR configuration is enabled, the GPIO3 pin is driven high while CBTIMER[3:0] is nonzero and is driven low when the timer value is zero. The cell-balancing timer is reset to zero when EMGCYDCHG =1.

D10

D9

D8

D7


D6

D5

D4

D3

D2

D1

D0



ACQCFG Register (address 0x19)



D14

D13

D12

D11

D10

D9

0 THRMMODE [1:0]

Sets the step size of the cell-balancing timer LSB per table below:

D8

THRMMODE[1:0] OPERATION

00 Auto mode (on in acquisition mode)

01 Auto mode (on in acquisition mode)

10 Manual mode, THRM switch off

11 Manual mode, THRM switch on


D6

D5

0 AINTIME [5:0]

Configures the pre-conversion settling time for each enabled AUXIN input from 6µs (default) up to 384µs (6µs/bit). This is to allow extra settling time if the application circuit requires it since the THRM voltage is not driven out until the start of the acquisition (in auto mode).

D4

D3

D2

D1

D0



BALSWEN Register (address 0x1A)


D15


D13

D12

D11

0 BALSWEN [11:0] BALSWEN[n-1] enables the balancing switch (conducting) between SWn and SWn-1.

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0



DEVCFG2 Register (address 0x1B)


D15 0 LASTLOOP

Enables UART loopback mode, which internally connects upper-port transmitter to upper-port receiver. The loopback mode allows the host to locate a break in daisy-chain communication whether or not the last daisy-chained device uses an external wire loopback wire or the internal loopback.


D13

D12 0 DBLBUFSEL Enables alternate double-buffer mode. Contact Maxim Applications for details; otherwise, leave in default state.

D11 0 TXLIDLEHIZEnables High-Z idle mode, which causes the TX drivers of the lower UART to idle in the high-Z state instead of idling in the logic-zero state (default mode). Leave in default state for normal operation.

D10 0 TXUIDLEHIZEnables High-Z idle mode, which causes the TX drivers of the upper UART to idle in the high-Z state instead of idling in the logic-zero state (default mode). Leave in default state for normal operation.

D9 0 RESERVED Reserved for future use. Reads the written value.

D8 0 EMGCYDCHG Set to enable emergency-discharge mode (configured by BALSWDCHG).

D7


D6

D5

D4

D3

D2

D1

D0 0 HVCPDISDisables the HV charge pump. Used for ALRTHVUV diagnostic. If the HV charge pump is disabled in normal operation, measurement errors will result due to VHVundervoltage.



BALDIAGCFG1 Register (address 0x1C)



D14

D13 0 ALTMUXSEL_M Mirror for ALTMUXSEL bit.

D12 0 POLARITY_M Mirror for POLARITY bit.

D11

0 CELLEN_M [12:1]

Mirror for CELLEN[12:1] in the MEASUREEN register. Writing to this field also updates CELLEN[12:1]. Reading this field reflects CELLEN[12:1].

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0



BALSWDCHG Register (address 0x1D)


D15

0 DCHGWIN [2:0]

Configuration for emergency-discharge mode (EMGCYDCHG = 1). Sets the duty cycle for each discharge cycle (even or odd) per the table below:D14

D13

DCHGWIN[2:0] (LSb = 7.5s) BEHAVIOR

0h Switches on for 7.5s, off for 52.5s

1h Switches on for 15s, off for 45s

… …

7h Switches on for 59.94s, off for 62.5ms


D11

0 DCHGCNTR [3:0]

Discharge counter that can be read to verify operation of the emergency-discharge mode (EMGCYDCHG = 1). During the emergency-discharge mode, the discharge counter counts at 2Hz rolling over at Fh to 0h and continuing until the emergency-discharge mode terminates. Read-only.

D10

D9

D8

D7

0 DCHGTIME [7:0]

Write to set the timeout value of the emergency-discharge mode (EMGCYDCHG = 1) per the table below. Writing to 00h disables the timer and terminates the emergency-discharge mode. The timer starts when EMGCYDCHG = 1 (and DCHGTIME[7:0] ≠ 00h) and stops when it reaches the timeout. The timer is reset when EMGCYDCHG = 0.

D6

D5

D4 DCHGTIME[7:0] (LSb = 2 hours) TIMEOUT

D3 00h Discharge mode disabled

D2 01h Discharge mode disabled after 4 hours

D1 02h Discharge mode disabled after 6 hours

D0… …

FFh Discharge mode disabled after 512 hours



TOPCELL Register (address 0x1E)

CELLn Register (addresses 0x20 to 0x2B)



D14D13D12D11D10D9D8D7D6D5D4D3

Ch TOPCELL[3:0]Configures the top-cell position if less than 12 channels are used. This is to properly mask the ALRTBALSW diagnostic alerts. TOPCELL[3:0] = 0h is not a valid configuration and is identical to the default, Ch (12d).

D2D1D0


0 CELLn[15:0] CELLn[15:2] contains the 14-bit measurement result for CELLn. CELLn[1:0] always reads logic-zero. Read-only.




VBLOCK Register (address 0x2C)


0 VBLOCK[15:0] VBLOCK[15:2] contains the 14-bit measurement result for VBLKP. VBLOCK[1:0] always reads logic-zero. Read-only.


AIN1 Register (address 0x2D)


0 AIN1[15:0] AIN1[15:4] contains the 12-bit measurement result for AUXIN1. AIN1[3:0] always reads logic-zero. Read-only.




TOTAL Register (address 0x2F)


0 SUM[15:0] 16-bit sum of all cell voltages CELLn[15:4] that are enabled by MEASUREEN. Read-only.


AIN2 Register (address 0x2E)


0 AIN2[15:0] AIN2[15:4] contains the 12-bit measurement result for AUXIN2. AIN2[3:0] always reads logic-zero. Read-only.




OVTHCLR Register (address 0x40)


FFFCh OVTHCLR [15:0] 14-bit overvoltage-clear threshold. UVTHCLR[1:0] always reads logic-zero.


OVTHSET Register (address 0x42)


FFFCh OVTHSET [15:0] 14-bit overvoltage-set threshold. UVTHCLR[1:0] always reads logic-zero.




UVTHCLR Register (address 0x44)


0 UVTHCLR [15:0] 14-bit undervoltage-clear threshold. UVTHCLR[1:0] always reads logic-zero.


UVTHSET Register (address 0x46)


0 UVTHSET [15:0] 14-bit undervoltage-set threshold. UVTHSET[1:0] always reads logic-zero.




MSMTCH Register (address 0x48)


FFFCh MSMTCH [15:0] 14-bit voltage threshold for ALRTMSMTCH. MSMTCH[1:0] always reads logic-zero.


AINOT Register (address 0x49)


0 AINOT [15:0]

12-bit undervoltage (overtemperature) threshold for AUXIN alerts. AINOT[3:0] always reads logic-zero.




AINUT Register (address 0x4A)


FFF0h AINUT[15:0] 12-bit overvoltage (undertemperature) threshold for AUXIN alerts. AINUT[3:0] always reads logic-zero.


BALSHRTTHR Register (address 0x4B)


0 BALSHRTTHR [15:0]

14-bit voltage threshold for the balancing-switch short-circuit diagnostic test. The ADC results in this test mode are compared against the threshold. If any result is below the threshold, it is flagged as a balancing-switch alert. Results above the threshold are considered normal. The threshold should be set by the system controller prior to making a diagnostic measurement. BALSHRTTHR[1:0] always reads logic-zero.




BALLOWTHR Register (address 0x4C)


0 BALLOWTHR [15:0]

14-bit low-voltage threshold for the balancing-switch conducting and cell-sense wire diagnostic tests. The ADC results in this test mode are compared against the threshold. If any result is below the threshold, it is flagged as a balancing-switch alert. Results above the threshold are considered normal. The threshold should be set by the system controller prior to making a diagnostic measurement. BALLOWTHR[1:0] always reads logic-zero.


BALHIGHTHR Register (address 0x4D)


0 BALHIGHTHR [15:0]

14-bit high-voltage threshold for the balancing-switch conducting and cell-sense wire diagnostic tests. The ADC results in this test mode are compared against the threshold. If any result is above the threshold, it is flagged as a balancing-switch alert. Results below the threshold are considered normal. The threshold should be set by the system controller prior to making a diagnostic measurement. BALHIGHTHR[1:0] always reads logic-zero.




DIAG Register (address 0x50)


0 DIAG[15:0] DIAG[15:2] contains the 14-bit measurement result for the diagnostic selected by DIAGCFG[2:0]. DIAG[1:0] always reads logic-zero. Read-only.


DIAGCFG Register (address 0x51)


D15

0 CTSTDAC[3:0]

Configures the current level for all enabled test sources per the table below (either 6.25µA or 3.125µA per bit):D14

D13 CTSTDAC3:0]TEST-SOURCE CURRENT

Cn, AUXINn HVMUX

D12

0h 6.25µA 3.125µA

1h 12.5µA 6.25µA

2h 18.75µA 9.375µA

… …. …

Dh 87.5µA 43.75µA

Eh 93.75µA 46.875µA

Fh 100µA 50µA

D11 0 CTSTSRC Configures the cell-input test-current sources to either source current from VAA (logic-one), or sink current to AGND (logic-zero).




DIAGCFG Register (address 0x51) (continued)


D9 0 AUXINTSTEN [2:1]

Enables the test-current sources connected to the corresponding AUXIN input for diagnostic testing. The current level is configured by the CTSTDAC[3:0] and the current direction is configured by CTSTSRC.D8 0

D7 0 MUXDIAGBUS

Selects the HVMUX output to which the HVMUX test-current source is connected, if MUXDIAGPAIR is enabled, as shown below:

MUXDIAGBUS HVMUX OUTPUT

0 Output used for even cells, C0, and AGND

1 Output used for odd cells and REF, and ALTREF

D6 0 MUXDIAGPAIRConfigures a single HVMUX test-current source to be connected to only one HVMUX output (as selected by MUXDIAGBUS). In the default configuration (MUXDIAGPAIR = 0), both HVMUX test-current sources are connected to both HVMUX outputs.


D4 0 MUXDIAGEN Enables the HVMUX test-current source(s). The current level is configured by CSTDAC[3:0] and the connectivity is configured by MUXDIAGPAIR, and MUXDIAGBUS

D3 0 ALTMUXSEL Enables cell measurements on the SWn inputs (ALTMUX data path) instead of the Cn inputs (HVMUX data path). Refer to the Diagnostics section.

D2

0 DIAGSEL [2:0]

Selects the diagnostic measurement for the acquisition per table below:

D1 DIAGSEL[2:0] DIAGNOSTIC MEASUREMENT

D0

0b000 No measurement

0b001 VALTREF

0b010 VAA (with ADC reference = VTHRM)

0b011 LSAMP Offset

0b100 Zero-scale ADC output (000h)

0b101 Full-scale ADC output (FFFh)

0b110 Die temperature

0b111 No measurement



CTSTEN Register (address 0x52)

ADCTEST1A Register (address 0x57)


D15


D13

D12

0 CTSTEN [12:0]

Enables the current sources connected to the corresponding cell input for diagnostic testing. The current level is configured by the CTSTDAC[3:0] and the current direction is configured by CTSTSRC in the DIAGCFG register.

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0


D15


D13

D12

D11

ADCTEST1A [11:0]

User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into the ALU during the first conversion of odd-numbered samples (e.g., first sample).

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0



ADCTEST1B Register (address 0x58)

ADCTEST2A Register (address 0x59)


D15


D13

D12

D11

0 ADCTEST1B [11:0]

User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into the ALU during the second conversion of odd-numbered samples (e.g., first sample).

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0


D15


D13

D12

D11

0 ADCTEST2A [11:0]

User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into the ALU during the first conversion of even-numbered samples in oversampling mode.

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0



ADCTEST2B Register (address 0x5A)

CALx Registers (addresses 0xC0–0xCA, 0xCF)


D15


D13

D12

D11

0 ADCTEST2B [11:0]

User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into the ALU during the second conversion of even-numbered samples in oversampling mode.

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0


D15

xxh CALx[15:0] Contains factory-calibration data. Read-only.

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0



Ordering Information Package InformationFor the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.+Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive-qualified part.

PART TEMP RANGE PIN-PACKAGE

MAX17823HGCB/V+ -40°C to +105°C 64 LQFP

PACKAGE TYPE

PACKAGE CODE

OUTLINE NO.

LAND PATTERN NO.

64 LQFP C64+13 21-0083 90-0141



http://www.maximintegrated.com/packages

http://pdfserv.maximintegrated.com/package_dwgs/21-0083.PDF

http://pdfserv.maximintegrated.com/land_patterns/90-0141.PDF

Revision HistoryREVISION NUMBER

REVISION DATE DESCRIPTION PAGES

CHANGED

0 8/18 Initial release —

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


© 2018 Maxim Integrated Products, Inc. 129

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Benefits and Features - Maxim Integrated

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