BCH Code Based Multiple Bit Error Correction in GF ... n A B... cted ty error 4 . Hardware...
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3/11/2011 1 BCH Code Based Multiple Bit Error Correction in GF Multiplier Circuits P. Mahesh 1 & A. M . Jabir : Oxford Brookes University J. Mathew 2 & D. K . Pradhan : Bristol University S. P . Mohanty 3 : University of North Texas E-mail: [email protected] 1 , [email protected] 2 , [email protected] 3 Presented by: Oleg Garitselov : University of North Texas
Transcript of BCH Code Based Multiple Bit Error Correction in GF ... n A B... cted ty error 4 . Hardware...
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BCH Code Based Multiple Bit Error
Correction in GF Multiplier Circuits
P. Mahesh1 & A. M . Jabir : Oxford Brookes University
J. Mathew2 & D. K . Pradhan : Bristol University
S. P . Mohanty3 : University of North Texas
E-mail: [email protected], [email protected],
Presented by:
Oleg Garitselov : University of North Texas
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Overview
Motivation
Background
Galois Arithmetic Circuits
BCH Code Based Error
Correction
Design Steps
Experimental Results
Conclusion & Future Work
Motivation
Fault attacks on Crypto. Hardware
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Previous Work
Ref: M. Nicoliadis , “Carry checking/parity prediction adders and ALUs ”, IEEE
Trans. VLSI Systems, vol. 11, Oct. 2003
LogicParity Prediction
A B
...
Predicted
parity
error
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Hardware Redundancy (TMR)
Voter
M1
M2
M3
Input 1
Input 2
Input 3
Output
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Finite Field
• Also called Galois Field, denoted by GF(N)
• N = pk, p is a prime number, and k is an
integer
• Each element is a k-tuple
• There are exactly N elements in the field (0,
1,…, N-1) or (0, 1, , 2 , 3 ,... , N-2) where ,
is a primitive element
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Finite Field
• Two operators
• ‘+’ called addition operation forming
Abelian Group
• ‘.’ called multiplication operation forming
Abelian group.
• Additive and multiplicative identities 0 and 1
respectively
• Additive and multiplicative inverse exists for
each element
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GF(4) Elements
[0, 1, , 2 ] = [0, 1, , ]
Elements can be represented in GF(2n) as
2-tuples over GF(2).
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Example GF(4)
GF(4)
2-tuple of GF(2)
a1 a0
Polynomial
Representation
a1 x + a0
0 0 0 0
1 0 1 1
1 0 x
1 1 (x+1)
Let 2 =
Thus we have 4 elements 0, 1, and
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Addition and Multiplication
• Addition and Multiplication in GF(4)
+ 0 1
0 0 1 1 1 0
0 1
1 0
* 0 1
0 0 0 0 0
1 0 1
0 1
0 1
is multiplicative inverse of , and vice versa.
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Generation of GF(2m)
• Let us generate GF(8) with PP p(x) = x3 + x + 1.
• Let be a root of p(x), i.e. p() = 0.
• Then 3 + + 1 = 0, i.e. 3 = + 1.
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1
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1
0
]1,0,0[1
]1,0,1[1
]1,1,1[1
]0,1,1[
]1,1,0[1
]0,0,1[
]0,1,0[
]0,0,0[0
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Multiplication
Multiplication is done by using polynomial mod a
primitive polynomial P(x). i.e. (x) • (x) mod P(x)
Let P(x) = x2 + x + 1
Thus • = x (x + 1) = x2 + x
(x2 + x) mod x2 + x + 1 = 1
• =1
So
and are inverse of each other
-1 = , - 1 =
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Example
a0 a1 b0 b1
Figure:2 GF(4) multiplier
EXOR gate
)( 11000 babac
)( 1101101 bababac
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Multiple Bit Error Correction Using BCH Codes
Proposed Approach
Multiple Bit Error Correction Using BCH
Codes: The Design Architecture
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Transient error
Corrected outputs
Multiple Bit Error Correction Using BCH
Codes: Synd. Generator and BCH Decoder
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Multiple Bit Error Correction Using BCH
Codes
)(mod)()( xgxMxxP kn
)()()( xPxMxxE kn
BCH (n,k), where n, k are code length &
message length respectively
Generate parity,
Codeword,
Syndrome,
where „t ‘is # bits to be corrected tii xExS 2....,2,1
|)()(
Find the error bit location by
efficient parallel Chien-search
Corrected bits at output
End!
BCH Algo:
Experiments & Results
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Experiments & Results
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Area comparison with
other techniques
Modelsim simulation
results
[10] Fault Tolerant Bit Parallel Finite Field Multipliers Using LDPC Codes, J. Mathew, J. Singh, A. M .Jabir, M. Hosseinabady, D. K .Pradhan, IEEE 2008.
[12] Single Error Correctable Bit Parallel Multipliers Over GF(2^m), J. Mathew, A. M . Jabir, H. Rahaman, D. K .Pradhan, IET Computer Digital Tech., Vol. 3, Iss. 3, pp. 281-288, 2009.
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Conclusion & Future Work
Multiple bit error correction with compromise
over slightly higher area
For a fixed number of bits to be corrected,
percent area overhead reduces with larger
and more practical multipliers
Highly parallel and efficient Chien-search
block
This scheme can be easily extendable to GF
multiplier of any size
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Questions?
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