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BCD SPAD imager with reconfigurable macropixels
for photon counting, timing and coincidence detection
F. Villa, D. Portaluppi, M. Sanzaro, E. Conca, F. Zappa
[email protected], February 27th, 2018
Outline
Motivations and design goals
SPAD imager architecture
“Macropixel” design
TDC structure
32x32 array
Chip characterizations
TDC preliminary tests
SPAD characterization
Conclusions
2
[email protected], February 27th, 2018
Outline
Motivations and design goals
SPAD Imager architecture
“Macropixel” design
TDC structure
32x32 array
Chip characterizations
TDC preliminary tests
SPAD characterization
Conclusions
3
[email protected], February 27th, 2018 4
1024 smart pixels
30-µm diameter SPADs
(3.14% fill-factor)
10-bit in-pixel TDCs
for “photon-timing” (TOF 3D ranging, FLIM)312 ps LSB, 320 ns FSR
6-bit in-pixel counters
for “photon-counting” (2D imaging)
100,000 frames/s
PoliMi 32×32 SPAD+TDC array chip
F. Villa et al., JSTQE, 2014
[email protected], February 27th, 2018
Single-photon camera
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SPAD+TDC array chip carrier board
Analog interface board
(for interfacing the chip and handlingtriggering and synchronizationinput/output signals)
Digital processing board
(FPGA for data processing, storage, andUSB3 communication link)
Power supply board
(power supplies generation, includinguser-selectable SPAD bias)
R. Lussana et al., OE, 2015
[email protected], February 27th, 2018
Many applications
• 3D ranging at short-distance
• Satellite 3D ranging
• First-photon 3D ranging
• Quantum physics (Weak measurements)
6
[email protected], February 27th, 2018
Main limitation of previous camera
• low PDE in the NIR
• low fill-factor
• low timing resolution
• no simultaneous counting/timing
• no hardware gating
• low TDC duty-cycle
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300 400 500 600 700 800 900 10000
10
20
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40
50
60
70
CMOS SPAD
Thick Junction SPAD
Red-Enhanced SPAD
Thin Junction SPAD
Photo
n D
ete
ction E
ffic
iency (
%)
Wavelength (nm)
[email protected], February 27th, 2018
New design specifications
Imager features:
• Hardware-gating and free-running modes
• In-pixel counters and TDC
• Multiple gates within 1 frame
• High flexibility: 2D imaging, 3D LIDAR, FLIM…
Best-in-class performance:
• SPADs with high PDE
• Fill Factor (> 5%)
• Timing resolution (< 100 ps)
• Scalability
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[email protected], February 27th, 2018
Outline
Motivations and design goals
SPAD Imager architecture
“Macropixel” design
TDC structure
32x32 array
Chip characterizations
TDC preliminary tests
SPAD characterization
Conclusions
9
[email protected], February 27th, 2018
• 32 mm square SPAD, 100 mm pitch, 9.6% fill factor
• 160 nm BCD technology
Macropixel architecture
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MEMORYBANKS
READOUT CONTROL
MEMORYBANKS
+TDC
COUNTER
EVENT COUNTERS
OUTPUTBUS
DRIVERS
TDC INTERPOLATOR
DISCRIMINATOR
2 xVLQC
2 xVLQC
READOUT
[email protected], February 27th, 2018
Single-photon mode (preserve spatial information)
• TDC is shared with no loss of X-Y resolution
• Each SPAD has its own storage register
Two-photon mode (ambient light suppression)
• Discrimination among multiple detectors, allowing 2×2 mini-SiPM operation
Macropixel operating modes
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Two synchronous detections one TDC conversion
[email protected], February 27th, 2018
Two-photon mode
Single-photon mode
SNR = 46
Two-photon mode
(1 ns coincidence)
SNR = 105
10 Mcps background, 10% PDP
Pro:
Uncorrelated noise suppressionCon:
Halved spatial resolution(like a mini-SiPM)
[email protected], February 27th, 2018
TDC architecture
• 75 ps LSB, 12 bit
(300 ns FSR)
• 415 MHz ref clock
• 7 bit coarse counter
+ 5 bit interpolator
(STOP)
• Global electronics:
START interpolator,
DLL clock gen.
• Sliding scale
• Single-hit within gate,
but multi-gate frame
[email protected], February 27th, 2018
Innovative TDC features
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• In-pixel gate counter up to 64 gate windows per frame
• Rising- and falling-edge sensitive interpolator:
½ clock lines (reduced area occupation and power consumption)
50% duty-cycle needed
STANDARDINTERPOLATOR
[email protected], February 27th, 2018
Innovative TDC features
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• In-pixel gate counter up to 64 gate windows per frame
• Rising- and falling-edge sensitive interpolator:
½ clock lines (reduced area occupation and power consumption)
50% duty-cycle needed
DUAL-EDGESENSITIVE
INTERPOLATOR
[email protected], February 27th, 2018
Multiphase clock generator
• 150 ps phase delay from DLL
• Clock edge interpolators to achieve 75 ps resolution
• Adjustable buffers for calibration
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[email protected], February 27th, 2018
Edge interpolator
• Constant current C discharge
• Robust vs. process variations
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.9
1.8
Inpu
ts (
V)
IN 1
IN 2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Time (ns)
0
0.9
1.8
Outp
uts
(V
)
OUT 1
OUT 2
OUT 3
T. Saeki et al., JSSC, 2000
[email protected], February 27th, 2018
Dummy guard traces
• Crosstalk between clock phases results in non-linearity
• Routing within clock generator is critical
• Dummy phases added to global clock routing
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0 8 16 24 31
TDC bin (a.u.)
30
40
50
60
70
Bin
wid
th (
ps)
No dummy phases
With dummy phases
[email protected], February 27th, 2018
Clock driver performance (post layout)
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Vdd = 1.8 V Near end Far end
𝑇𝑅𝐼𝑆𝐸20−80 120 ps 202 ps
𝑇𝐹𝐴𝐿𝐿20−80 90 ps 170 ps
Vdd = 1.5 V Near end Far end
𝑇𝑅𝐼𝑆𝐸20−80 146 ps 221 ps
𝑇𝐹𝐴𝐿𝐿20−80 108 ps 182 ps
Power consumption 1.8V driver 1.5V driver
Overall clock-related power4.93 W 3.92 W
( - 20% )
power consumption / performance trade-off
favorable for lower supply voltage
[email protected], February 27th, 2018
Single column select readout
[email protected], February 27th, 2018
In-pixel readout logic
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• 3 static control signals: FAST, COUNT, FIRST_ONLY
• Distributed «one-hot» shift register plus combinatorial logic
• Maximizes bus precharge time, reduces number of global lines, offers great readout flexibility
[email protected], February 27th, 2018
Available operation modes
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Mode Outputs # cycles
Single-photon
normal readout4 timing (one per SPAD), 4 counters 4
Single-photon
fast readoutFirst event timing, WHO, 4 counters 2
Single-photon
first timing onlyFirst event timing, WHO 1
Counting only 4 counters 1
Double-photon
full readout
First 4 event timing, double event counter
[3 SPAD single event counters]4
Double-photon
first onlyFirst event timing, double event counter 1
[email protected], February 27th, 2018
Global routing constraints
Power supplies
• Thick top metal
TDC clocks
• 5 bit interpolator (32 phases @ 415 MHz)
• Thick top metal
Row readout
• 23 bit bus
• Metal 3 (thin)
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[email protected], February 27th, 2018
16x16 macropixel array
Macropixel
• 4 SPADs, VLQCs, gating
• TDC and event counters
Array
• 16x16 macropixels (32x32 SPADs)
• Clock generation
• Global readout electronics
• Power distribution
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RO
WSE
LEC
TOR
Frequency Multiplier +Delay Locked Loop
16 clock phases
REF CLK
16+223
[email protected], February 27th, 2018
Fabricated chips
Stand-alone TDC
75 ps LSB, 300 ns FSR (extendable),
1.6 x 1.6 mm2
32 x 32 SPAD array
9.6% fill factor,
1 mm2 total active area,
4.2 x 4.6 mm2
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[email protected], February 27th, 2018
Outline
Motivations and design goals
SPAD Imager architecture
“Macropixel” design
TDC structure
32x32 array
Chip characterizations
TDC preliminary tests
SPAD characterization
Conclusions
28
[email protected], February 27th, 2018
TDC preliminary characterization
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Single shot precision = 115 ps FWHM
[email protected], February 27th, 2018
SPAD PDE and uniformity
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M. Sanzaro et al., JSTQE, 2018
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P
DE
(%
)
Wavelength (nm)
CMOS 0.35 mm
BCD wafer A
BCD wafer B
BCD wafer C
Custom thin SPAD
[email protected], February 27th, 2018
SPAD DCR
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0 10 20 30 40 50 60 70 80 90 10010
0
101
102
103
104
0.18 cps/mm2 @ 5 V
0.14 cps/mm2 @ 4 V
DC
R (
cp
s)
SPAD diameter (mm)
0.1 cps/mm2 @ 3 V
M. Sanzaro et al., JSTQE, 2018
[email protected], February 27th, 2018
SPAD DCR
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240 250 260 270 280 290 300 310 320 330 340 350 360 37010
-2
10-1
100
101
102
103
104
105
106
SPAD diameter = 30 mm
excess bias = 5 V
wafer A
wafer B
wafer C
DC
R (
cp
s)
Temperature (K)M. Sanzaro et al., JSTQE, 2018
[email protected], February 27th, 2018
SPAD timing (FWHM)
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0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.010
-4
10-3
10-2
10-1
100
32.5 ps
FWHM
29.8 ps
FWHM
No
rmalized
co
un
ts (
a.u
.)
Time (ns)
31.4 ps
FWHM
wafer A wafer B wafer C
M. Sanzaro et al., JSTQE, 2018
[email protected], February 27th, 2018
SPAD timing (diffusion tail)
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0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.010
-4
10-3
10-2
10-1
100
219 ps
FW1/100M
= 48 ps = 107 ps
359 ps
FW1/100M
wafer Cwafer B
N
orm
ali
ze
d c
ou
nts
(a
.u.)
Time (ns)
wafer A
= 93 ps
306 ps
FW1/100M
[email protected], February 27th, 2018
Outline
Motivations and design goals
SPAD Imager architecture
“Macropixel” design
TDC structure
32x32 array
Chip characterizations
TDC preliminary tests
SPAD characterization
Conclusions
35
[email protected], February 27th, 2018 36
Parameter Value Units
SPAD number 32 × 32
TDC number 16 × 16
SPAD pitch 100 µm
SPAD side 32 µm
Fill-factor 9.6%
Operating mode Only timing / Only counting
Simultaneous timing and counting
SPAD activation HW gate
Free running
TDC resolution 75 ps
TDC FSR 300 ns
TDC number of bit 12 bit
TDC single-shot precision 115 ps (FWHM)
Counter number of bit 5 bit
SPAD PDE 60% (@500nm), 12% (@800nm)
SPAD DCR 150 cps
SPAD time jitter 60 ps (FWHM)