Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Signal Processing for Nuclear Detectors,...

Bavarian Forest,Bavarian Forest, 24 April 2009D. AlbertoD. Alberto

Signal Processing for Nuclear Detectors

Bavarian Forest,, 24 April 2009

Dipartimento di Fisica Generale

M.P. Bussa, L. Ferrero, A. Grasso, M. Greco, M. Maggiora,

Diego ALBERTO


Outline

Introduction

Simulated Transmission Chain

Simulated WGN Noise

SNR and Peak Distortion

Simulation Filtering Results

Towards FPGA

Our Real Transmission Chain

Future works


The detector

detector

1


Detector

iE

fE

if EEE

time

Eamplitude

The signal generated by the passage of a ionizing particle appeares as a voltage or current pulse

This pulse amplitude is proportional to the energy released by the particle inside the detector

“Baseline Shift”, “Pulse Pile-Up”, “Ballistic Deficit”, “Noise”

During the signal analysis we must pay attention to all those phenomena that can modify time and amplitude measures:

Introduction

2


Simulated Transmission Chain

IIR / FIR

Noise

Filter

Simulated Signal

i(t)

Preamp /Integrator

Analog Shaper /

Antialias filter

PZ comp

WGN

White Gaussian Noise

++

ADC

samplerquantizer

PZ

pPZ s

sk

1

1

p

p

s

k

1 nAS

AS

s

k

1

3


Noise

Causes of noise in an electronic acquisition chain:

Thermal noiseThermal noise: is generated by the thermal agitation of the charge carriers inside an electrical conductor and depends on the bandwidth, a larger bandwidth implies a larger noise.

Shot noiseShot noise: consists of random fluctuations caused by the fact that the current is carried on by discrete charges that pass through a potential barrier.

Flicker noiseFlicker noise: low frequency noise, typical on electronic devices, it depends on the generation and recombination processes on the material surface.

4


Simulation: WGN

We started to represent all these kind of noises as an additive White Gaussian Noise (WGN) to the input signal

Our aim is the reduction of this noise using digital filters

We are now studing other more realistic kinds of noise as the pink one

Time [ns]

Am

plitu

de

Standardvs

Adaptive

5


SNR and Peak Distortion

The Signal to Noise Ratio (SNR) is the ratio between the Signal Power and the Noise Power, usually expressed in dB. In general the power of a digital signal x[n] of N samples is evaluated as:

N

nx nx

NP

1

2][

1

3 3.5 4 4.5 5 5.5

x 10-7

0.85

0.9

0.95

1

1.05

Shaped Quantized Noised Signal vs desired vs filtered

time [s]

ampl

itude

X= 3.7002e-007Y= 1.0824

desired

Butterw III With Peak Distortion we intend the relative difference between the desireddesired peak value and the filteredfiltered one, it is expressed in percentage

Es: Butt. III LP → PD = 8.24 %

6


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10-6

-0.2

0

0.2

0.4

0.6

0.8

1

time [s]

ampl

itude


noised

desired

Butterw III

Simulation: Standard Butterw III ord.

Butterworth III ord. Transfer Function: Infinite Impulse Response ( IIR )

321

321

087.0515.0827.01

075.0226.0226.0075.0

zzz

zzzzH

SNR: 5.76 dB

PD: 8.24%

7


The update coefficients equation )(1 neww nn

Simulation: Adaptive Least Mean Square

)(

)(

)(

0

0

0

nnv

nnd

nnx

)()()( nvndnx

LMSAdaptive FIR Filter

-+

)(ne

)(ˆ nd

0nz

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10-6

-0.2

0

0.2

0.4

0.6

0.8

1

time [s]

ampl

itude


noised

desired

LMS

best results µ = 0.18

SNR: 6.57 dB

PD: 0.06% 8


Simulation: Butterw vs LMS filtering

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10-6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2Butterw vs LMS ( = 0.18 )

time [s]

Nor

mal

ized

Vol

tage

Uni

t

noised

desiredButter

LMS

This analysis has been published on Nuclear Instruments and Methods sect. A 594 (2008), pp.382-388 DOI information: 10.1016/j.nima.2008.06.032

9


Towards FPGA

10


12 bits10 bits for the binary point

System Generator and ISE (Butt. III LP)

FIR sectioncorrectlyimplementedwith the HW JTagCosimulation

This retroaction chain could not be automatically implemented with the HW JTag Cos

11


VHDL

12

For this reason we started to study VHDL

We used Xilinx ISE tool

We described in VHDL language some different standard filter structure

With ChipeScope we could get the signal filtered by our ML402 Virtex 4 FPGA


FPGA elaboration

Translating the filter structures into VHDL code written by ourselves we obtained good results with standard filters

0 200 400 600 800 1000 1200 1400 1600 1800 2000-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2Filtering Comparison

time [ns]

ampl

itude

[nv

u]

noisy input

Butt. III ord MatlabModelSim filt

ChipScope filt

# utilized Flip-Flop 315 / 30720 H 1% # 4 inputs LUT 346 / 30720 H 1% # occupied slices 333 / 15360 H 2% max frequency 70-80 MHz

13

250 300 350 400 450 500

0.9

0.95

1

1.05

1.1

Filtering Comparison

time [ns]

ampl

itude

[nv

u]


Analog ChainAnalog Chain

Qδ(t)

Detector

i(t)

Preamp/Integr

Analog Shaper

PZ comp

PZ

pPZ s

sk

1

1

p

p

s

k

1 nAS

AS

s

k

1

Q Q Q

ADC IIRvsFIR

Noise

Filtersamplerquantizer

Digital ChainDigital Chain

Q

Transmission Chain

14


Transmission Chain

PC Xilinx Virtex 4 ML402 FPGA our analog board LeCroy 6100A programmable pulse generator

Our real transmission chain is composed of a:

15


Future Works

16

To cope with the implementation of LMS algorithms on FPGA

Take into account faster algorithms (as the sign LMS )

To study different and more realistic kinds of noise


Thank you for the

Attention

!!

Bavarian Forest,Bavarian Forest, 24 April 2009D. AlbertoD. Alberto 2020

Simulink Schematics: Butterworth III LP

Sys. Gen.Butterworth


1z

][nx

1z

827,0

515,0

226,0

226,0

087,0 075,0

075,0 ][ny

1z

Direct Form II Butt. III LP

Butterworth III ord. Transfer Function: Infinite Impulse Response ( IIR )

321

321

087.0515.0827.01

075.0226.0226.0075.0

zzz

zzzzH


System Generator and ISE

The filter structure has been synthesized with System Generator (only the Netlist)

We had: to learn VHDL language and Xilinx ISE Tool to write and manage PIN location, alimentations, filter connections

The VHDL code has been included in an ISE project

Input ROM Filter Output RAM

FPGA Board


Model Sim code simulation

Output Ram


Simulations comparison

Simulating the filtering with Matlab and Model Sim we obtained:

Considered the quantization there is a very good matching

0 200 400 600 800 1000 1200 1400 1600 1800 2000-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

time [ns]

ampl

itude

[nv

u]

Butterw III order: noisy vs Matlab filtered vs FPGA filtered

Noisy input ROM

Matlab filtFPGA filt out RAM ModelSim


ADCADC

DACDAC

P/Z compP/Z comp

PreamplPreampl

An. ShaperAn. Shaper

ADCADC

FilterFilter

Test Board SchematicsTest Board Schematics


PANDA Test Board PANDA Test Board

ORCAD layoutORCAD layout Our boardOur board


First results

Input

Analog Shaper Output (seen after our DAC, it

passed in the FPGA )

Digital Shaper Output

Higher Noise in Digital Shaper Output ??

Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Signal Processing for Nuclear Detectors,...

Documents

Transcript of Bavarian Forest, Bavarian Forest, 24 April 2009 D. Alberto Signal Processing for Nuclear Detectors,...