Basic Structure of Computer
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Transcript of Basic Structure of Computer
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Basic Structure of Computer
• Introduction of computer system & its sub-modules
• Basic organization of computer & block level description of the functional units
• Von Neumann model• Introduction to buses & connecting I/O devices
to CPU & memory• Asynchronous & synchronous bus, PCI, SCSI
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Computer Organization & Architecture
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Structural/functional view of a computer
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Data
movement
apparatus
Control
mechanism
Data
processing
facility
Data
storage
facility
Operating environment
(source & destination of data)
Fig: A Functional View of the Computer
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COMPUTER
•Storage
•Processing
Com
munication
Lines
Perip
heral
s
Fig: The Computer
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Input/
Output
Main
Memory
Central
Processing
unit
System
interconnection
COMPUTER
COMPUTER
Fig: The Computer: Top-level Structure
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Registers Arithmetic &
Logic unit
Control
unit
Internal CPU
interconnection
CPU
CPU
I/OMemory
System
bus
COMPUTER
Fig: The Central Processing Unit (CPU)
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Sequencing
logic
Control
memory
Control unit
Registers &
decoders
CONTROL
UNIT
Control unit
RegistersALU
Internal
bus
CPU
Fig: The Control Unit
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Von Neumann Model
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Interconnection Structures
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Fig: Computer Modules
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The interconnection structure must support the
following types of transfers:• Memory to Processor• Processor to Memory• I/O to Processor• Processor to I/O to or from memory
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Fig: Bus Interconnection Scheme
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Control Bus
Used to control the access to & the use of data & address lines
Typical control lines include
• Memory read/write
• I/O read/write
• Transfer ACK
• Bus request/grant
• Interrupt request/ACK
• Clock
• Reset
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Multiple-Bus hierarchies
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Fig: High-performance architecture
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Elements of Bus design
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Type Bus Width
Dedicated Address
Multiplexed Data
Method of Arbitration Data transfer Type
Centralized Read
Distributed Write
Read-modify-write
Timing Read-after-write
Synchronous Block
Asynchronous
Elements of Bus Design
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Synchronous Timing Diagram
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Asynchronous Timing
• Occurrence of one event on a bus follows & depends on the occurrence of previous event.
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Asynchronous Timing – Read Diagram
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Asynchronous Timing – Write Diagram
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PCI
(Peripheral Component Interconnect)
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• 50 optional signal lines, divided into following groups:
• Interrupt pins: not shared, each PCI device has its own interrupt line to an interrupt controller.
• Cache support pins: support a memory on PCI that can be cached in the processor or another device.
• 64-bit bus extension pins: 32- additional time-multiplexed lines for address & data, plus lines to interrupt & validate these, and to provide agreement between two PCI devices on use of these.
• JTAG/boundary scan pins: support testing procedures defined in IEEE Standard 1149.1.
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PCI Commands
• Interrupt Acknowledge• Special Cycle• I/O Read• I/O Write• Memory Read• Memory Read Line• Memory Read Multiple
• Memory Write• Memory Write and
Invalidate• Configuration Read• Configuration Write• Dual Address Cycle
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SCSI
Small Computer System Interface
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Introduction
The Small Computer System Interface (SCSI) is a parallel I/0 bus and protocol that permits the connection of a variety of peripherals including disk drives, tape drives, modems, printers, scanners, optical devices, test equipment, and medical devices to a host computer.
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The SCSI Bus
The SCSI bus connects all parts of a computer system so that they can communicate with each other.
The bus frees the host processor from the responsibility of I/O internal tasks.
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The SCSI protocol
The SCSI protocol is a peer-to-peer relationship: one device does not have to be subordinated to another device in order to perform I/0 activities.
A total of eight devices can be connected to the bus simultaneously. Only two of these devices can communicate on the bus at any given time.
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• A unique SCSI device ID (7-0) is assigned to the SCSI host adaptor and to each device controller.
• One of the devices on the bus must be the initiator (usually the host adaptor). The other device is the target (usually the peripheral device controller).
• When two devices communicate on the bus, one device initiates the communication to the target, and the target performs the task.
• SCSI devices usually have a fixed role as an initiator or a target, although some devices can perform both roles.
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Fig: SCSI Configuration
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SCSI Bus signals
The SCSI bus uses eighteen signals. Nine are control signals used to develop logical bus phases, and nine are data signals, including parity, for messages, commands, status, and data.
The state of the SEL, BSY, and I/O signals and the sequence of the phases determine when the Bus Free, Arbitration, Selection, and Reselection phases are entered.
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Table 1: SCSI Bus Signals
SignalDescription
BSY(BUSY) An 'OR-tied signal which indicates that the bus is being used.
SEL(SELECT) A signal used by an initiator to select a target, or by a target to reselect an initiator.
C/D (CONTROL/DATA)
A signal drven by a target to indicate whether or not control or data information is on the data bus. True indicates control.
I/0 (INPUT/OUTPUT)
A signal driven by a target to control the direction of data movement on the data bus. True indicates input to the initiator. This signal is also used to distinguish between selection and reselection phases.
MSG (MESSAGE) A signal driven by a target during the Message phase.
REQ (REQUEST) A signal driven by a target to request a REO/ACK data transfer handshake.
ACK (ACKNOWLEDGE)
A signal driven by an iniüator to acknowledge a REO/ACK data transfer.
ATN (ATTENTION)A signal driven by an inifiator to indicate the Atterifion conditioti (inidator has a message for the target).
RST (RESET) An 'OR-tied' signal and hard Res.et condition.
DB (7-0,P) (DATA BUS)
Eight data-bit(DB) signals, plus a parity-bit signal that form a Data Bus. DB(7) is the most significant bit and has the highest phohty during the Arbitradon phase. Bit number, significance, and priority decreaso downward to DB (0). A data bit is defined as one when the signal value is true, and defined as zero when the signal value is false. Data parity DB(P) shall be odd, but parity is undefined during the Arbitradon phase.
NOTE
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Fig: SCSI Bus Phases
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Bus operation
• An arbitration scheme is used to determine which devices can transfer data at a given time.
• Initiator- SCSI device that initiates transaction
• Target: the responding device
• 8 different bus phases
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SCSI Bus phases
• Bus free phase: The initiator begins a transaction by testing BSY & SEL signals. When these are inactive, bus is free.
• Arbitration phase: The unit that wants to control the bus, activates the BSY & data bit corresponding to its SCSI ID.
• Selection phase: SEL line is made active & SCSI address bits corresponding to initiator & target are placed on data lines.
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SCSI Bus phases
• Reselection phase: Once target receives a command, it carries that command out without intervention from initiator. Once the task is finished, the target, remembering initiator’s ID, reestablishes connection using arbitration & selection phases.
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SCSI Bus phases
• Command phase: Device specific commands are sent to the target from the initiator.
• Data phase: Data transfer may occur asynchronously or synchronously.
• Message phase: Various messages can be exchanged between Initiator & Target. Eg: command complete, terminate I/O
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SCSI Bus phases
• Status phase:
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Questionnaire
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Explain structure of computer defined by Sir Von Neumann. Distinguish between computer architecture and computer
organization with the help of appropriate examples. Write short note on PCI bus. Explain the different element considered while designing the
bus interconnection architecture. Explain the five elements of bus design. Explain the bus interconnection structure with the help of
data, address & control lines. Explain the PCI bus structure.
Questionnaire