Basic Digital Electronics - Unit 6

8/12/2019 Basic Digital Electronics - Unit 6

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At the end of the lesson, students should be able to:

1. Differentiate between half-adders and full-adders.

2. Implement a parallel binary adder

3. Construct and test a logic functions ICs

4. Troubleshoot common fault in logic function

6 LOGIC FUNCTION


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UNIT 6: LOGIC FUNCTION

Fatma Syazana ZainiIKM Besut, 2010

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INTRODUCTION

In this topic students will learn about several types of combinational logic circuits areintroduced including adders, comparators, decoder, encoder code converters, multiplexers(data selectors), de-multiplexers and parity generators checkers. Examples of Fixed-Functions IC devices are included.

Adders are important in computers and also in other types of digital systems in which

numerical data are processed. An understanding of the basic adder operation isfundamental to the study of digital systems.

Half-Adder

These operations are performed by a logic circuit called a half-adder.

The half-adder accepts two binary digits on its inputs and produces two binarydigits on its outputs, a sum bit and a carry bit.

Input bits Outputs

Figure 6.1 : Logic symbol for a half-adder

6.1 BASIC ADDER

0 + 0 = 00 + 1 = 11 + 0 = 11 + 1 = 10

A

B Cout

Sum


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Cout = AB

From the operation of the half-adder as stated in table 6.1, expressions can bederived for the sum and the output carry as functions of the inputs.

INPUTS OUTPUTSA B Cout

1 1

1 1

1 1 1

= sumCout = output carry

A and B = input variables (operands)

Table 6.1 : Half adder truth table

The output carry (C out) is a 1 only when both A and B are 1s; therefore, C out canbe expressed as the AND of the input variables.

The sum can be expressed as the exclusive-OR of the input variables.

From the Equations C out = AB, and = A B, the logic implementation requiredfor the half-adder function can be developed.

The output carry is produced with an AND gate with A and B on the inputs, andthe sum output is generated with an exclusive-OR gate.

= A B


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Figure 6.2 Half adder logic diagram

Full-Adder

The full adder accepts three inputs including an input carry and generates a sumoutput and an output carry.

The basic difference between a full adder and half-adder is that the full-adder accepts an input carry.

Figure 6.3 : Full adder logic Symbol

Table 6.2 Full adder truth Table

A B Cin Cout 0 0 00 0 1 1

0 1 0 1

0 1 1 1

1 0 0 11 0 1 1

1 1 0 1

1 1 1 1 1

A

BCin Cout

Sum

OutputCarryInput

Carry

= A B

COUT = AB


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The full adder must add the two input bits and the input carry. From the half-adder we know that the sum of the input bits A and B is the exclusive-OR ofthose two variables, A B.

For the input carry (C in) to be added to the input bits. It must be exclusive-ORed with A B, yielding the equation for the sum output of the full-adder.

Two 2-input exclusive-OR gates can be used to implement the full-adder sumfunction.

Figure 6.4: Complete logic circuit for a full-adder

Arrangement of two half-adder to from a full-adder (Figure 6.5)

Figure 6.5 : Full-adder implemented with half-adder

= (A B) C in

Cout = A B + (A B) Cin

= (A B) Cin

A

B

A

Half-Adder Half-Adder

A

B Cout

A

B Cout

= (A B) Cin

Cout = A B + (A B) Cin

Input carry,Cin


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Two or more full-adders are connected to form parallel binary adders.

A single full-adder is capable of adding two 1-bit numbers and an input carry.

To add binary numbers with more than one bit, additional full-adders must be used.

Example:1 carry bit from right column 1 1

+ 0 1

1 0 0carry bitfrom second columnbecome a sum bit

To implement the addition of binary numbers, a full adder is required for each bitin the numbers. For 2 bit numbers, two adders are needed, for 4 bit numbers, fouradders are needed.

Basic 2-bit parallel adder;

General format, addition of two 2-bit numbers.

A2 A1+ B2 B13 2 1

Figure 6.6 Block diagram of a basic 2-bit parallel adder

A2 B2 A1 B1

A B Cin A B Cin

(MSB) 3 2 1 (LSB)

6.2 PARALLEL BINARY ADDER


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74LS83 4-BIT Parallel Adder

A group of for bits is called a nibble. A basic 4-bit parallel adder isimplemented with four full-adder stages.

The LSBs (A1 and B1) in each number being added go into the right-mostfull-adder; the higher-order bits are applied as shown to the successivelyhigher-order adders, with the MSBs (A 4 and B4) in each number beingapplied to the left-most full adder.

The carry o/p of the next higher-order as indicated. These are calledinternal carries

Figure 6.7: Block diagram of a 4-bit parallel adder

Figure 6.7 Logic symbol of a 4-bit parallel adder

6.3 CONSTRUCT AND TEST OF ICs


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In keeping with most manufacturers data sheets, the input labeled C 0 is theinput carry to the least significant bit adder; C 4 in the case of four bits, isthe output carry of the most significant bit adder, and (LSB) through (MSB)

are the sum outputs.

Cn 1 A n Bn n Cn 0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

n represent the adder bits and can be 1,2,3 or 4Cn-1 the carry from the previous adder carriers C1, C2, C3 are

generated internally.C0 is an external carry i/pC4 an o/p

Table 6.3 Truth Tablefor a 4-bit parallel adder


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Example:

Use the 4-bit parallel adder truth table to find the sum and o/p carry forthe addition of the following two 4-bit numbers if the i/p carry (C n-1) is 0.

A4 A3 A2 A1 = 1100 and B4 B3 B2 B1 = 1100

Solution ;

For n=1 A 1=0, B 1=0, and C n-1 = 0From the 1 st row of the table1 = 0 and C1 = 0.

For n = 2 A 2=0, B 2=0, and C n-1 = 0From the 1 st row of the table2 = 0 and C2 = 0.

For n = 3 A 3=1, B 3=1, and C n-1 = 0From the 4 th row of the table3 = 0 and C3 = 1.

For n = 4 A 4 =1, B 4 =1, and C n-1 = 1From the last row of the table4 = 1 and C4 = 1.

C4 becomes the output carry, the sum of 1100 and 1100is 11000.


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7485 4-BIT ( Comparator )

Basic function of comparator is to compare the magnitudes of two binaryquantity to determine the relationship of those quantity.

A comparator circuit determines whether two numbers are equal.

Ex-OR gate can be used as a basic comparator because its output is a 1 ifthe two input bits are not equal and a 0 if the i/p bits are equal.

Ex-OR gate as a 2 bit comparator

The i/p bits are equal

The i/p bits are not equal

The i/p bits are not equal

The i/p bits are equal

00

0

01

11

11


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Example:Apply each of the following sets of binary numbers to the comparator i/p infigure below, and determines the o/p by following the logic level throughthe circuit.

a) 1 0 and 1 0

b) 1 1 and 1 0

74154 4-LINE-TO-16 ( Decoder )

Basic function of decoder is to detect the presence of a specifiedcombinational of bits (code) and its inputs end to indicate the presence of

that code by a specified output level.

A decoder has n input lines to handle n bits and from one to 2 n output linesto indicate the presence of one or more n-bit combinations.

The 74HC154 is a good example of an IC decoder. The logic symbol is shownin figure 6.8.

A0 0

B0 0

A1 0

B1 0

0

A0 1

B0 0

A1 1

B1 1

0

equal

Not equal


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There is an enable function ( EN ) provided on this device, which isimplemented with a NOR gate used as a negative-AND. A LOW level on eachchip select input, and , is required in order to make the enable gateoutput ( EN ) HIGH.

Figure 6.8 Pin diagram and logic symbol for the 74HC154 1-of-16 decoder

The enable gate output is connected to an input of each NAND gate in thedecoder, so it must be HIGH for the NAND gates to be enabled. If the gateis not activated by aLOW on both inputs, then all sixteen decoder outputs(Y ) will be HIGH regardless of the states of the four input variables, A

0, A

1,

A2 and A3.

This device may be available in other CMOS or TTL families.

Applications of 74HC154

o Decoders are used in many types of applications. One example is incomputers for input/output selection as depicted in the general diagram offigure 6.9

o Computer must communicate with a variety of external devices calledperipherals by sending and/or receiving data through what is known asinput/output (I/O) ports.


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Figure 6.9 : A simplified computer I/O port system with a port address decoder with only fouraddress line shown

o

These external devices include printers, modems, scanner, external diskdrives, keyboard, video monitor and other computers.

o A decoder is used to select the I/O port as determines by the computer sothat data can be sent or received from a specific external device.

o Each port has number, called an address, which uniquely identifies it.

o When the computer wants to communicate with a particular device, it issuesthe appropriate address code for the I/O port to which that particulardevice is connected. This binary port address is decoded and the appropriatedecoder output is activated to enable the I/O port.


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7442A BCD-to-Decimal

Figure 6.10 The 74HC42 BCD-to-decimal decoder

The BCD-to-Decimal decoder converts each BCD code (8421 code) into oneof ten possible decimal digit indications. It is frequently referred as a 4- line-10-line decoder or a 1-of-10 decoder.

The method of implementation is the same as for the 1-of-16 decoder. TheBCD code represents only the ten decimal digits 0 through 9.

Table 6.5 show a list of BCD code and their corresponding decodingfunctions.

Table 6-5 BCD decoding function


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Each of these decoding functions function is implemented with NAND gatesto provide active-LOW outputs. If an active-HIGH output is required, ANDgates are used for decoding. The logic is identical to that of the first tendecoding gate in the 1-of-16 decoder.

BCD-to-SEVEN Segment

Figure 6.11: Logic symbol for a BCD-to-7-segment decoder

The BCD-to-7-segment decoder accepts the BCD code on its input andprovides outputs to drive 7-segment display devices to produce a decimalreadout. The logic diagram for a basic 7-segment decoder is shown in figure6.11.

The 74LS47 is an example of an IC device that decodes a BCD input anddrives a 7-segment display. In addition to its decoding and segment drivecapability, the 74LS47 has several additional features as indicated by theLT, RBI, BI/RBO functions in the logic symbol of figure 6.12

BCD

Inputs

A0

A1

A2

A3

BCD/7-SEG

a

b

c

d

Output lines connectto 7-segment displaydevices


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Figure 6.12 :Pin diagram and logic symbol for the 74LS47 BCD-to-7-segmentdecode/driver

IC 7447 drive common-anode 7-segmentLT lamp test : When a LOW is applied to the LT input and

the BI/RBO is HIGH, all of the 7 segments in thedisplay are turned on. Lamp test is used to verifythat no segments are burned out.

RB1 ripple blanking inputB1/RB0 blanking input / ripple blanking output

Decimaldigit

BCD Input Segmentsactivated

0 0000 a,b,c,d,e,f1 0001 b,c2 0010 a,b,d,e,g3 0011 a,b,c,d,g4 0100 b,c,f,g

5 0101 a,c,d,f,g6 0110 a,c,d,e,f,g7 0111 a,b,c8 1000 a,b,c,d,e,f,g9 1001 a,b,c,d,f,g

f b

a

d

g


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The 74LS 138 was used as a DEMUX in the data transmission system. Now the74HC138 is used as a 3-line-to-8-line decoder (binary-to-octal) in Figure 6.13 toillustrate how glitches occur and how to identify their cause.

The A2A1A0 inputs of the decoder are sequenced through a binary count, and theresulting waveforms of the inputs and outputs can be displayed on the screen of alogic analyzer, as shown in Figure 6.13. A2 transitions are delayed from A1transitions and A1 transitions are delayed from A0 transitions. This commonlyoccurs when waveforms are generated by a binary counter,

Figure 6.13 : Decoder waveforms with output glitches

The output waveforms are correct except for the glitches that occur on some ofthe output signals. A logic analyzer or an oscilloscope can be used to displayglitches, which are normally very difficult to see. Generally, the logic analyzer ispreferred, especially for low repetition rates (less than 10 kHz) and/or irregularoccurrence because most logic analyzers have a glitch capture capability.Oscilloscopes can be used to observe glitches with reasonable success, particularly

if the glitches occur at a regular high repetition rate (greater than 10 kHz). The points of interest indicated by the highlighted areas on the input waveforms in

Figure 6.13 are displayed as shown in Figure 6.14. At point 1 there is a transitionalstate of 000 due to delay differences in the waveforms.

This causes the first glitch on the 0 output of the decoder. At point 2 there aretwo transitional states, 010 and 000. These cause the glitch on the 2 output of thedecoder and the second glitch on the 0 output, respectively.

6.4 TROUBLESHOOT COMMON FAULTS IN LOGIC FUNCTION


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At point 3 the transitional state is 100, which causes the first glitch on the 4output of the decoder. At point 4 the two transitional states, 110 and 100, result inthe glitch on the 6 output and the second glitch on the 4 output, respectively.

One way to eliminate the glitch problem is a method called strobing , in which thedecoder is enabled by a strobe pulse only during the times when the waveforms arenot in transition. This method is illustrated in Figure 6.15.

Figure 6.14 : Decoder waveform displays showing how transitional input statesproduce glitches in the output waveforms

Figure 6.15 : Application of a strobe waveform to eliminate glitches on decoder outputs


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In this topic, students have learned about the principles of half-adder and full-adder byusing Boolean equation. Student should be able to use full-adder to implement multibitparallel binary adder.

Student also learned how to construct and test the 4-bit logic ICs including BCD todecimal circuit and BCD to seven segment. Student must know how to troubleshootcommon faults in logic function

1. What is the function of Half-Adder and Full- Adder?

2. What is the application of Half-Adder and Full- Adder?

3. A 4-bit parallel adder can add ____ bit binary number.

4. Two 4-bit numbers (1100 and 1011) are applied to a 4-bit parallel adder. The inputcarry is 1. Determine the sum () and the output carry.

5. How many 74HC154 1-of-16 decoders are necessary to decode a 6-bit binarynumber?

6. Define the term strobe ?

7. A half-adder is characterized by ______ input and ________ output

8. A BCD-to-7 segment decoder has 0100 on its inputs. The active outputs are

SUMMARY

EXERCISE


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Fatma Syazana Zaini

9. Show he decoding logic for each of the following codes if an active-HIGH (1) outputis required:

a) 1101 b) 1000 c) 11011

d) 101010 e) 111110 f) 1110110

10. A 3-line-to-8-lene decoder can be used for octal-to-decimal decoding. When abinary 101 is on the inputs, which output line is activated?

1. Digital System Principle And Applications, Tocci, R.J, Prentice Hall international

2. Digital Fundamentals, Floyd T.L, Merrill Publishing.

3. BPL(K) Module : TFV 2033 Digital Electronics 1.

4. Digital Electronics Teaching Module, KUITHO

REFERENCE

Basic Digital Electronics - Unit 6

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