BASIC BLOCKS : PASSIVE COMPONENTS 1. PASSIVE COMPONENTS: Capacitors Junction Capacitors Inversion...

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BASIC BLOCKS : PASSIVE COMPONENTS 1

Transcript of BASIC BLOCKS : PASSIVE COMPONENTS 1. PASSIVE COMPONENTS: Capacitors Junction Capacitors Inversion...

Page 1: BASIC BLOCKS : PASSIVE COMPONENTS 1. PASSIVE COMPONENTS: Capacitors  Junction Capacitors  Inversion Capacitors  Parallel Plate Capacitors Resistors.

BASIC BLOCKS : PASSIVE COMPONENTS

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PASSIVE COMPONENTS:

•CapacitorsJunction CapacitorsInversion CapacitorsParallel Plate Capacitors

•ResistorsPoly ResistorsDiffused ResistorsSwitched capacitors as resistorsActive Load

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CAPACITORS

The desired characteristics for capacitors used are given below:· Good matching accuracy· Low voltage-coefficient· High ratio of desired capacitance to Parasitic capacitance· High capacitance per unit area

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This structure uses the Gate to Source and gate to Drain Capacitances to realise the required Capacitances. This capacitance achieves a large capacitance per unit area and good matching but suffers from high voltage dependent parasitic capacitance to ground.

Poly- SiO2 – Channel Capacitance

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Poly – SiO2 – Poly Capacitor

This is one of the best configurations for high performance capacitors.

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MOS Accumulation Capacitor

This has a high capacitance per unit area and used where grounded capacitors re required.

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Capacitors realized using various inter connect layersThis gives the method to obtain capacitors by appropriate choice of plates and connection between various metal and Poly Si layers available. It should be mentioned that each interconnect layer is insulated from the others by a SiO2 layer. Of the various structure shown, the four layer structure has the least parasitic capacitance.

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As processes migrate toward finer line widths and higher speed performance, the oxide between metals increases while the allowed space between metals decreases. For such processes, samelayer, horizontal, capacitors can be more efficient than different-layer vertical capacitors. This is due to the fact that the allowed space between two M1 lines, for example, is less than the vertical space between M1 and M2.

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The capacitor plate with the smallest parasitic associated with it is referred to as the top plate. It is not necessarily physically the top plate although quite often it is. In contrast, the bottom plate is that plate having the larger parasitic capacitance associated with it. Schematically, the top plate is represented by the flat plate in the capacitor symbol while the curved plate represents the bottom plate.

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While designing for matched capcitors or ratioed capacitors, a technique of common centroid lay out is used. The concept is best illustrated with an example.

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VICINITY EFFECTS

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RESISTORS

The diffused resistor is normally formed with source/drain diffusion. The sheet resistance of such resistors are normally in the range of 50 to 100/ for non salicide process and about 5-15/ for sallicide processes. These resistance have a voltage dependence in the range of 100-500 ppm/V range and also a high parasitic capacitance to ground.

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The poly Si resistor has a sheet resistance in the range of 30-200 / depending on the doping of the poly Si layer. For a polysilicide process the resistance is about 10/.

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The n-well resistance has a resistance of 1-10K/ along with a high voltage sensitivity. In cases where accuracy is of no concern this structure is very useful.

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ACTIVE (ac) RESISTORS

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SWITCHED CAPACITOR RESISTOR

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AMPLIFIERS

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DSn2

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2k

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SMALL SIGNAL PARAMETERS

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COMMON SOURCE AMPLIFIERS

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gm = gm1 and RL = R ||l rds1 for Resistance load amplifier

gm = gm1 and RL = rds1 ||l rds2 ||l 1/gm2 for Active load amplifier

gm = gm1 and RL = rds1 ||l rds2 for Current source load amplifier and

gm = gm1 + gm2 and RL = rds1 ||l rds2 for Push Pull Amplifier.

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Ain = gm1 (R ||l rds1) for Resistance load amplifierAin = gm1 (rds1 ||l rds2 ||l 1/gm2) = for Active load amplifier.Ain = gm1 (rds1 ||l rds2) = for Current source load amplifier Ain = (gm1 + gm2) (rds1 ||l rds2) = for Push Pull amplifier.

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The capacitor at the input CIN = CGS1 for Active Load and Current Source Load Amplifier and CIN = CGS1 + CGS2 for the Push Pull amplifier. The bridging capacitor C = CGD1 for Active Load and Current Source Load Amplifier and C = CGD1 + CGD2 for the Push Pull amplifier. The capacitor at the output CL = CLoad + CGS2 + CBD1 + CBD2 for the Active Load amplifier and is CL = CLoad + CBD1 + CBD2 for the Current Source Load and Push Pull Amplifiers. 28

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1

1Lm

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A

MS

2m

LL1

21

21Lm

s

out

CR1

andCg

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wheress

z/s1Rg

vv

A

CM is the Miller Capacitance seen at the input.

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COMMON DRAIN AMPLIFIER

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loadsourcecurrentforgggg

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g

2ds2m1ds1mbs1m

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1m

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COMMON GATE AMPLIFIER

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LSS1ds1mb1m1ds

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CASCODE AMPLIFIER

C1 = Cgd1, C2 = Cdb1 + Csb2 + Cgs1, C3 = Cgd2 + Cdb3 + Cdb2 + Cgd3

and 2 = gmbs2/gm2. 35

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1gd3ds

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1m1gd2in1m1gdin

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g1

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g1Crg1Cv

v1CC

Since in the presence of a signal source with a source impedance RS, the pole contributed by the Miller Capacitance seen by the Cascode amplifier will be farther than the Common Source Amplifier with nearly the same gain and input and output impedances.

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In cascode amplifier we have used a simple current source load. However, to obtain a larger gain we can use a cascade of current mirror load. It should be mentioned here that a single current source is represented as a single transistor with a bias while we have represented a cascade current source with two transistors in series with appropriate gate bias.

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2ds

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gg

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gm2 ≈ gm3, gds2 = gds3 = gds1 = gds5

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A

TELESCOPIC CASCODE AMPLIFIER

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2ds

23ds3m

2m2in r

rg1

g1

r ||l 1/gds5

ds

1m

1

1ds2in

1min

11 g2

gg

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2m

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FOLDED CASCODE AMPLIFIER

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