Baseband Systems for Long Term Evolution (LTE) · 3G Long Term Evolution (LTE) ... PUSCH PRACH UCI...
Transcript of Baseband Systems for Long Term Evolution (LTE) · 3G Long Term Evolution (LTE) ... PUSCH PRACH UCI...
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PN106
Baseband Systems for Long Term Evolution
Nov 2008
Aureus ShumSystem and Application Engineering
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Contents
►Introduction and motivation
►LTE standard overview• SC-FDMA / OFDMA• Channel overview• Signal processing chains
►MIMO overview• Background• Implementation approaches
►Implementation proposal on MSC8144 plus MSBA8100, and on MSC8156
• Device overview• Use case definition• System Architecture
►Summary
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3G Long Term Evolution (LTE)
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Broadband Wireless Technology Timelines
Source: Rysavy Research
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LTE vs. WiMAX 802.16e
3GPP LTE (ongoing) WiMAX 802.16e
Base standard Currently v8.4.0 IEEE® 802.16e-2005
Duplex method FDD/TDD TDD (FDD optional)
Downlink OFDMA OFDMA
Uplink SC-FDMA OFDMA
Channel BW (MHz) 1.4, 3, 5, 10,15, 20 5, 7, 8.75, 10 (1.25~20 opt)
Frame size 10 ms 5 ms
Modulation DL QPSK/16QAM/64QAM QPSK/16QAM/64QAM
Modulation UL QPSK/16QAM/64QAM QPSK/16QAM
Channel Coding DL Turbo / CC CTC Turbo / CC
Channel Coding UL Turbo / CC CTC Turbo / CC
Throughput (DL/UL) 100/50 Mbps (20 MHz) ~40 shared (10 MHz, TDD)
HARQ Incremental redundancy Chase combining
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duration TS
f2
f1
f0
OFDM Basics
S/P
X(k) x(n)
CyclicPrefix
Frequency Domain Time Domain
Orthogonal Subcarriers !
f
1/TS
f0 f1 f2
A
t
IFFT P/S
Basic ideas valid for variousmulticarrier techniques:► OFDM – Orthogonal Frequency
Division Multiplexing► OFDMA – Orthogonal Frequency
Division Multiple Access
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Motivation for Multi-carrier Approaches
►Multi-carrier transmission offers various advantages over traditional single carrier approaches
• Highly scalable• Simplified equalizer design in the frequency domain, also in cases of
large delay spread• High spectrum density• Simplifies the usage of MIMO• Good granularity to control user data rates• Robustness against timing errors
►Weaknesses of multi-carrier systems• Increased peak to average power ratio (PAPR)• Impairements due to impulsive noise• Impairements due to frequency errors
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Single Carrier FDMA (SC-FDMA)
► The symbol mapping in OFDM happens in the frequency domain.
► In SC-FDMA, the symbol mapping is done in the time domain.
► Appropriate subcarrier mapping in the frequency domain allows to control the PAPR
► SC-FDMA enables frequency domain equalizer approaches like OFDMA
S/P
X(k) x(n)
CyclicPrefix
Frequency Domain Time Domain
IFFT P/S
SubcarrierMapping
X(k)x(n)
CyclicPrefix
Frequency Domain
Time Domain
IFFT P/SDFT
Time Domain
OFDMA
SC-FDMA
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LTE L1 PHY Specification
► 36.104-830: Base Station (BS) radio transmission and reception► 36.211-840: Physical Channels and Modulation► 36.212-840: Multiplexing and channel coding► 36.213-840: Physical layer procedures► 36.214-840: Physical layer – Measurements
http://www.3gpp.org/ftp/Specs/2008-09/Rel-8/36_series/
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LTE Signal Spectrum (20 MHz case)
• The LTE standard uses an over-sized FFT. The actual used bandwidth is controlled by thenumber of used subcarriers. 15 kHz subcarrier spacing is the constant factor!
• 18 MHz out of 20 MHz is used for data, 1 MHz on each side is used as guard band
• LTE used spectrum ratio = 90%
• WiMAX used spectrum ratio = 82%
Transmit Band = 20 MHz
Guard Band = 1 MHz Guard Band = 1 MHz
Used Band = 1200 * 15kHz = 18 MHz
Sampling Frequency = 2048 * 15kHz = 30.72 MHz
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LTE L1 Channel Overview
DL
UL
Data ControlDL-SCH PCH BCH MCH
PDSCH PBCH PMCH
CFI HI DCI
PHICH PDCCHPCFICH
UL-SCH RACH
PUSCH PRACH
UCI
PUCCH
Transport ChannelsPhysical Channels
Dir Transport Channel
Physical Channel
Usage Coding
DL DL-SCH PDSCH DL data channel
Paging channel for call initialization
Broadcast channel for general cell information
Multicase channel
Control format indicator, encodes the number of DL-CCH OFDMA symbols
HARQ feedback channel
DL control channel with subframe scheduling information
UL data channel
Random access channel for UE connection init
UL control channel for CQI and HARQ feedback
Turbo 1/3
PCH PDSCH Turbo 1/3
BCH PBCH Conv. 1/3
MCH PMCH Turbo 1/3
CFI PCFICH Block Code 1/16
HI PHICH Repet. 1/3
DCI PDCCH Conv. 1/3
UL UL-SCH PUSCH Turbo 1/3
RACH PRACH FFS
UCI PUCCH FFS
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FDD Frame Structure (Type 1)
Description Name Value
Radio Frame length Tf
Subframe length Tsf 1 ms
Ts
Subcarrier spacing Δf 15 kHz (constant)
Sample frequency (time unit) Ts 1/(15k*2048) = 32.6 ns
OFDMA Symbol length ~ 70 us
Resource block 12 subcarriers
10 ms
Slot length 0.5 ms
• 2 slots form one subframe = 1 ms
• For FDD, in each 10ms interval, all 10 subframes are available for downlink transmission and uplink transmissions.
• For TDD, a subframe is either allocated to downlink or uplink transmission. The 0th and 5th subframe in a radio frame is always allocated for downlink transmission.
#0 #1 #2 #3 #19
One slot, Tslot = 15360×Ts = 0.5 ms
One radio frame, Tf = 307200×Ts=10 ms
#18
One subframe
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TDD Frame Structure (Type 2)
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LTE FDD vs TDD (c.f. on 36.211 and 36.212)
► Type1 frame vs Type2 frame• Significantly different in system partitioning, scheduling, timing handling
and multi-core framework design• May affect Channel Estimation design
► 36.212 Transport Channel Signal Processing: • DCI (DL control info) format: UL index, HARQ process, DL assignment
index• DL Rate Matcher
► 36.211 Physical Channel: • Sounding Reference Signal• Guard Period Handling• PRACH Random Access Preamble Parameters (format4 for TDD)• PHICH for HARQ indicator and corresponding resource mapping• UL-DL Timing relation• Primary/Secondary Synchronization Mapping
FDD TDD Signal ProcessingKernel
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Downlink Subframe Structure
PDSCH, PMCH
RS
/ Control
RS
/ Data
RS
/ Data
l=0 l=1 l=2 l=3 l=4 l=5 l=6
DL Subframe, 1 ms
OFDMA Symbol
l=0 l=1 l=2 l=3 l=4 l=5 l=6
Slot, 0.5 ms Slot, 0.5 ms
PDSCH, PMCH mixed with RSPDCCH, PHICHPDCCH, PHICH mixed with RS
PCFICH
PBCH
RS
/ Data
RS
/ Data
RS
/ Data
RS
/ Data
One Resource Block12 Subc * Nsym
Broadcast Channel72 Subc * Nsym
R1R1
R1
R1
R1
R1
R1
R1
Reference SymbolPattern per RB
Nsc
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Uplink Subframe Structure
► The subframe duration is 1ms. Each subframe contains 2 slots and 14 OFDMA symbols.
► The reference symbols (RS) are located in the middle of each slot and occupy the entire bandwidth
One Resource Block12 Subc * Nsym
RS
RS
l=0 l=1 l=2 l=3 l=4 l=5 l=6
OFDM Symbol
l=0 l=1 l=2 l=3 l=4 l=5 l=6
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Transport Block Processing
110 ,...,, −Aaaa
110 ,...,, −Bbbb
( )110 ,...,, −rKrrr ccc
( ))(
1)(
1)(
0 ,...,, iDr
ir
ir r
ddd −
( )110 ,...,, −rErrr eee
110 ,...,, −Gfff
applies to • DL-SCH• PCH• MCH
Downlink Tx
Transport block CRC attachment
Code block segmentationCode block CRC attachment
Channel coding
Rate matching
Code block concatenation
Data and Control multiplexing
Channel coding
110 ,...,, Aaaa
110 ,...,, Bbbb
110 ,...,,rKrrr ccc
)(1
)(1
)(0 ,...,, i
Dri
ri
r rddd
110 ,...,,rErrr eee
110 ,...,, Gfff
110 ,...,, Hggg
110 ,...,, Oooo
110 ,...,, Qqqq
Channel Interleaver
110 ,...,, H+Qhhh
Channel coding
ACKQ
ACKACKACK
qqq 110 ,...,,
][or ][ 010ACKACKACK ooo
Channel coding
RIQ
RIRIRI
qqq 110 ,...,,
][or ][ 010 oooRI RI RI
RI
Uplink Tx
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Physical Channel Processing
► Scrambling: Scrambles binary information
► Modulation Mapper: Maps groups of 2,4 or 6 bits onto QPSK, 16QAM and 64QAM symbol constellation points
► Transform Precoder: Slices the input data vector into a set of symbol vectors and performs DFT transformation
► Resource Element Mapper: Maps the the complex constellation points into the allocated virtual resource blocks and performs translation into physical resource blocks
► SC-FDMA Signal Generation: Performs the IFFT processing to generate final time domain signal for transmission
DL Tx:
UL Tx:
ScramblingModulation
mapperTransform precoder
Resource element mapper
SC-FDMAsignal gen.
Scrambling Modulation mapper
Layermapper Precoding
Resource element mapper
OFDM signal generation
Resource element mapper
OFDM signal generationScrambling Modulation
mapper
layers antenna portscode words
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Channel Estimation & MMSE Detector)(1
3 fS
⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛
+×⎟⎟
⎠
⎞⎜⎜⎝
⎛
++
⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛
+×⎟⎟
⎠
⎞⎜⎜⎝
⎛
++−
−
)()(
)1()(
)1()1()()(
)()(
)1()(
)1()1()()(
1,1
0,131
31
1
13
03
13
03
1,0
0,030
30
1
13
03
13
03
fHfH
fRfR
fSfSfSfS
fHfH
fRfR
fSfSfSfS
)(03 fS
600
sbc
FFT1024
sbc
600
sbc
FFT1024
sbc
f
Cazac Matrix Inversion & mult with received vector1
)(03 fR
)(13 fR
f
Per coefficient H Low Pass Filtering2
⎟⎟⎠
⎞⎜⎜⎝
⎛
)()()()(
1,10,1
1,00,0
fHfHfHfH
))
))
Inter – Slot interpolation of matrices H (VehA channel only)3
1
1
0*
1
0
1,10,1
1,00,0
*
1,10,1
1,00,0
00
00
)()()()(
)()()()(
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
⎟⎟⎠
⎞⎜⎜⎝
⎛×⎟⎟
⎠
⎞⎜⎜⎝
⎛+⎟
⎟⎠
⎞⎜⎜⎝
⎛×⎟
⎟⎠
⎞⎜⎜⎝
⎛=
nn
nn
fHfHfHfH
fHfHfHfH
Gmmse ))
))
))
))
Gmmse computation4
Equalization:5
RHGmmseS ××= *)
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► Ways to increase the maximum data rate:
• Improve coding schemes (from CC to Turbo / LDPC)
• Improve scheduling/adaptation (from fixed modulation to adaptive modulation coding schemes in EDGE, WiMAX, LTE)
• Increased transmitted S/N : unpractical, due to regulations on max power emission on mobile side, battery lifetime, RF cost etc.
• Increased signaling bandwidth W. Can be done by either:
widen the signaling banduse spatial diversity (MIMO) to add new “bandwidth“ dimension
Maximizing the Data Rate
► S/N is the received signal to noise ratio in dB
► W is the available signaling band in Hz
► C is the capacity limit in Hz
► Any data rate R ≤ C can in theory be transmitted over the channel with bandwidth W without errors (not taking into account the required complexitiy of the coding etc.)
)/1(log 2 NSWC +=
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Multiple Transmit Antennas
►Spatial Multiplexing:• Goal is to maximize data rate• Send as much independent data as possible
over different antennas• Detection requires some sort of matrix
inversion• Works only if number of receiver antennas
is greater or equal to number of transmitantennas (i.e. less suitable for DL)
►Space-Time Coding:• Maximize divesity gain, i.e. maximize
received SNR• Two main approaches:
STTC : Space time trellis codeSTBC: Space time block code (for exampleAlamouti as used in WiMAX STC)
• Simple decoding approach
Encoder
De cod er
Tx Rx
Channel
Encod er
De cod er
Tx Rx
Channel
sisoh
SISO/SIMO: (1xM)
MIMO: (ex. 2x2, 2x4, 4x4,..)
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Multi User (MU) - MIMO
►Each UE is transmitting with one single antenna
►The data rate per UE staysconstant
►Both UE transmit in the same time / frequency domain, hence createda received signal composed of twouser signals
►The two combined user streamsneed to be decomposed in the receiver
►The overall cell capacity can beincreased
)0(~),1(~),2(~),3(~... 0000 ssss
UEb
UEa
)0(~),1(~),2(~),3(~... 1111 ssss
RS
RS
l=0 l=1 l=2 l=3 l=4 l=5 l=6
UL Subframe, 1 ms
OFDM Symbol
l=0 l=1 l=2 l=3 l=4 l=5 l=6
Slot, 0.5 ms Slot, 0.5 ms
RS
RS
l=0 l=1 l=2 l=3 l=4 l=5 l=6
UL Subframe, 1 ms
OFDM Symbol
l=0 l=1 l=2 l=3 l=4 l=5 l=6
Slot, 0.5ms Slot, 0.5 ms
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MIMO Detector Options
►Maximum likelihood (ML) detector• High performance• High complexity
►Near-optimal• Sphere decoding
►Sub-optimal detectors• Decision feedback equalizer (DFE)• Nulling-canceling• QRDM• V-BLAST
►Linear equalizers• Zero-forcing (ZF)• Minimum mean-square error (MMSE)
2
},...,{ 1minargˆ k
TNCkHxrx
xxx−=
∈
YHNNHHX *1** )(~ −+=
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Freescale High Performance DSP for 3G Long Term Evolution (LTE)
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High Level View of a Base Station
Control
Radio L1Physical
Layer
Radio L2MAC Layer
Transport(Network)Interface
Node B /BTS
RNC,aGW
…
IP/ATM
Backplane sRIOGigE
► Channel Coding► Tx Modulation ► Rx Advanced Receiver► Multi-Antenna MIMO ► Remote Antenna Interface
► Frame Protocol Processing► Link Control► Retransmission / ARQ► Scheduling / QOS► Control and Data Plane
► IP Packet Processing► Multi-Transport termination► Network Security► Synchronisation► Network Quality of Service
► Management/Control► Admission Control► Configure/Track/Maintain► OAM
Baseband
U/DConv./ DPD
RFSmallSign
RFPA
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MSC8144/E/EC Multicore DSP
CLA
SS –N
on-Blocking Sw
itch Fabric
CLA
SS –N
on-Blocking Sw
itch Fabric
DDR 1/2 Memory
Controller
SharedL2
I-Cache128 KB
32b 400MHz
SharedM2
Memory512 KB
CLASS – Non-Blocking Switch Fabric
SecurityProcessing Engine(8144E and EC only)TDM Highway
8 ports2k channels
SERDES
SharedM3
Memory
10 Mbyte
H/W Semaphores
On-Chip Network
1x SRIO x4/x1
I²C, UART, GPIOs
CLA
SS –N
on-Blocking Sw
itch Fabric
CLA
SS –N
on-Blocking Sw
itch Fabric
32 ch. DMA Engine
PCI
QUICCEngine®2 RISCs
2x 10/100/1000 Ethernet,
UTOPIA /POS-PHY,SPI
4 lanes 3.125Gbaud Dual SGMII Utopia 16b 50MHz PCI bus 32b 66MHzTDM
SC3400 core
16KBI-Cache
32KBD-Cache
SC3400 core
16KBI-Cache
32KBD-Cache
SC3400 core
16KBI-Cache
32KBD-Cache
SC3400 core
16KBI-Cache
32KBD-Cache
► 4x SC3400 core subsystems(up to 4/GHz/16GMACs), each with
• SC3400 DSP core at 1GHz (4GMACs 16b or 8GMACs 8b)• 16 Kbyte I-cache, 32Kbyte D-cache, MMU, PIC
► Internal Memories/Caches• 10 MB shared M3 unified memory (eDRAM) • 512 KB shared M2 unified memory (SRAM)• 128 KB shared L2 I-Cache
► CLASS – Chip-Level Arbitration & Switching Fabric• Non-Blocking, fully pipelined at low-latency accesses• Operates at 400MHz
► High Speed Interconnects• x4/x1 Serial RapidIO – 1.25/2.5/3.125 Gbaud
► Dual RISC QUICCEngine® supporting:• Dual SGMII/RGMII Gigabit Ethernet ports or Dual RMII/SMII
Fast Ethernet ports• Utopia 16b/50Mhz supporting AAL-0/2/5 in firmware• POS-PHY in firmware• Operates at 400MHz, Eth./ATM protocols and sRIO offload
► DDR Memory Controller• DDR1/2 SDRAM 400MHz, 32/16 bit w/ECC
► TDM Highway• 2048 DS-0 ch., divided into 8 ports 256 each
► PCI 32b/66MHz► DMA Engine 32 unidirectional ch.► 8 Hardware Semaphores► Security Engine (SEC 2.x) (8144E and EC only)
• Data and Code Protection (8144EC only)► Other Peripheral Interfaces
• SPI, UART, I2C, 32 GPIO, 16 Timers, 96KB boot ROM, JTAG► Technology
• 90nm SOI• 1V Core, 3.3/2.5/1.8 V I/O• 783 pins, FCBPGA (29x29), 1mm pitch, RoHS
In Production
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► MAPLE-B – Baseband Accelerator• 333MHz Multi-accelerator platform engine for BaseBand processing.• Turbo/Viterbi Decoder up to 120/85 Mbps for LTE
Multi Standard: 3G/3GLTE/WiMAX/CDMA2K• FFT/DFT Accelerators
up to 200 Msps FFT2048 and 130 Msps DFT1536• Dual RISC based programmable system i/f• Embedded DMA engine• Rate De-matching, de-puncturing and HARQ support
► Internal Memory• 512 kByte M2 memory (SRAM)
► DDR Memory Controller• DDR1/DDR2 SDRAM 333Mbps, 32 bit
► CLASS – Chip-Level Arbitration & Switching Fabric• Non-Blocking, fully pipelined at low latency accesses
► Interfaces• Dual 4x/1x Serial RapidIO at 1.25/2.5/3.125 Gbaud• PCI 32b/66MHz
► Technology• 90nm SOI• 1V Logic, 3.3/2.5/1.8/1.0 V I/O• 783 pins, FCBPGA (29x29), 1mm pitch, RoHS
Samples: June 08
MSBA8100 – Multi-Standard Baseband Accelerator
CLASS
M2 Memory512KByte
Turbo/Viterbi
MAPLE-B
FFT/iFFT
DFT/iDFT
PC
I SerialRapidIO
Serial RapidIOSubsystem
RMU
DMA
SerialRapidIO
Serial RapidIOSubsystem
RMU
DMA
DDR2 32/16bit
RISC RISC
DMA
DDR Controller
Clocks
I/O InterruptConcentrator
Reset
MSBA8100 Block Diagram
PCI bus 32-bit @ 66MHz 4 x 3.125Gbaud 4 x 3.125Gbaud
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System Architecture10 MHz, FDD, 2UL&2DL antenna, 1 sector
DDR
sRIO to
RF I/F
GbE
MPC8548GbE
sRIO
4x
4x
4x
4x
4x
sRIOSwitch
Tsi568A
RF
DD
R
DD
R2
GbEGbE
sRIO
DD
R
DR
2
GbEGbE
sRIO
4xDD
R
DD
R2
MSBA8100
sRIO
sRIO
MSC8144
DSP
MSC8144
DSPRGMII
RGMII
DL Device:From transport block
encoding down tophysical channel
mapping
UL Device:Channel estimation,
MIMO Detector,Equalization,
LLR calculation
Accelerator Device:DL IFFT UL FFTUL DFT
UL Turbo Decoding
►L1 processing based on 3 MSC8144 devices + one MSBA8100 accelerator.
►All devices connected over 4x sRIO.
►Dual 4x sRIO connectivity for MSBA8100 to separate antenna data and DSP traffic
DD
R
DR
2
GbEGbE
sRIOMSC8144
DSP
Remark:Estimation bases on PDSCH, PUSCH, DLSCH, ULSCH library and excludes framework,
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Unified AMC™ Rapid Development platform for Base Stations
►Features and Benefits• Scalable and flexible AMC-based platform• Serial RapidIO®/Ethernet backplane
interconnect• Industry-leading processing platforms
Modular AMC platform
MPC8568
MPC8548
MSC8144
FPGA for Fibre To RH Antenna
PowerQUICC® processorControl
Radio L1Physical
Layer
Radio L2MAC Layer
NetworkInterface
U/DConv.
RFSmallSign
RFPA
μTCA Chassis
Network Interface &
Control Card(MPC8568)
Radio Layer 2 Processing
Card(MPC8548)
Radio Layer 1 Baseband DSP Card
(MSC8144)
Antenna Card
LTE Integrated Layer 1 & 2 Uplink
LTE Network Interface
WiMAX Layer 1 plus 3rd party AMAS smart Antenna
MSBA8100LTE/Wimax Coprocessor
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MSC8156E – Broadband Wireless DSP • 6 SC3850 Cores Subsystems (up to 6GHz/48GMACS) each
with:• SC3850 DSP core at up to 1GHz (8GMACs 16b or 8b)• 512 Kbyte unified L2 cache / M2 memory. • 32 Kbyte I-cache, 32Kbyte D-cache, WBB, WTB, MMU, PIC
• Internal/External Memories/Caches• 1056 KByte M3 shared memory (SRAM)• Two DDR 2/3 64-bit SDRAM interfaces at up to 800 MHz
• CLASS – Chip-Level Arbitration & Switching Fabric• Non-Blocking, fully pipelined, low latency• Full fabric 12 masters to 8 slaves, up to 512 Gbps throughput
• MAPLE-B – Baseband Accelerator• Turbo/Viterbi Decoder up to 160 (8 iter.)/100 (K=7 Tailbit)
Mbps, supporting: 3G-LTE, 802.16, 3G, CDMA2K standards• FFT/DFT accelerator up to 280/180 Msps DFT
• Security Engine (Talitos 3.1)• Data and Code Protection (AES, SHA, Kasumi, SNOW3G)
• High Speed Interconnects• Dual 4x/1x Serial RapidIO at 1.25/2.5/3.125 Gbaud• PCI-e 4x/1x
• Dual RISC QUICCEngine® supporting• Dual SGMII/RGMII Gigabit Ethernet ports • Eth. L1 Protocols, Talitos control and sRIO offload
• TDM Highway• 1024 ch., 400Mbps, divided into 4 ports of 256
• DMA Engine 16 bi-directional channels w/ external req/ack• 8 hardware semaphores• Other Peripheral Interfaces
• SPI, UART, I2C, 32 GPIO, 16 Timers, 96KB boot ROM, JTAG/SAP, 8 WDT
• Technology• 45nm SOI, 1V core, 2.5, 1.8/1.5V I/O• FCBPGA (29x29) 1mm pitch, RoHS
SharedMemory1056 KB
DDR 2/3 Memory
Controller
CLASS – Non-Blocking Switch Fabric
6 cores
SC3850 core
32KB L1I-Cache
32KB L1D-Cache
512KB Unified M2/L2
H/W Semaphores
I²C, UART, GPIOs
CLA
SS –N
on-Blocking Sw
itch Fabric
CLA
SS –N
on-Blocking Sw
itch Fabric
DMA Engine
MAPLE-BBasebandAccelerator
SerDes x4
On-Chip Network
2x SRIO 4x/1x,1x PCIe 4x/1x
2x Gigabit Ethernet, SPI
SecurityProcessing
Engine
SerDes x4
SC3850 core
32KB L1I-Cache
32KB L1D-Cache
512KB Unified M2/L2
SC3850 core
32KB L1I-Cache
32KB L1D-Cache
512KB Unified M2/L2
SC3850 core
32KB L1I-Cache
32KB L1D-Cache
512KB Unified M2/L2
SC3850 core
32KB L1I-Cache
32KB L1D-Cache
512KB Unified M2/L2
SC3850 core
32KB L1I-Cache
32KB L1D-Cache
512KB Unified M2/L2
TDM Highway4 ports
DDR 2/3 Memory
Controller
ExecutionSampling – Q1-09
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Mid LTE Solution Targeted : 20MHz, 2x2 UL/DL, 1 Sector
200 VoIP Users per SectorPlus Data uses three TCP packet types (Large, medium & Small)Remark:
Estimation bases on PDSCH, PUSCH, DLSCH, ULSCH library and excludes framework.
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Summary
►The quad core MSC8144 general purpose DSP together with the accelerator chip MSBA8100 offer a cost-effective quick startup platform for a LTE L1 implementation in software.
►The six-core MSC8156 baseband DSP provides excellent performance upgrade
►The different cores of the DSP can be used for concurrent steps in the UL and DL processing chain which will reduce overall latency.
►The FFT / DFT acceleration along with the high capacity Turbo and Viterbi blocks help to further decrease the software load and improve processing latency throughput.
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Related Session Resources
SessionsSession ID
DemosPedestal ID
PN116 RF Power Amplifier Solutions for WiMAX and LTE
PN107 Multicore Solutions and Applications
Title
502 Baseband Accelerator Performance Demo
Demo Title
Session Location – Online Literature Libraryhttp://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=052577903644CB
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