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AMC2000

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AMC2000

Barrier Layers Technology

Prof. Yosi Shacham-Diamand

Department of Physical Electronics

Tel-Aviv University,

Tel-Aviv 69978 ISRAEL

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Outline

Introduction Copper Interconnect technology Barrier layers - overview Process development and integration Barrier layers modeling Barrier analysis, testing & monitoring Summary

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Introduction Structure of Microchips ULSI metallization technology Metallization roadmap Downscaling issues

Performance issues Manufacturing issues

Where is the bottom ?

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Copper multi-level metallization

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IBM CMOS 7S process

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Copper chips... IBM power PC 750 Mitsubishi Electric eRAMTM family AMD K7(Athalon) UMC 0.18 m process Motorola 333MHz SRAM Lucent & Chartered 0.16 m process

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IBM PowerPC 750

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Structure of microchips

Silicon substrate (600-800 m)

Active devices layer ( 1-2 m)

Interconnect network - 6-7 layers of metallization

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ULSI metallization technology

אינטל 2000

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Gate and Interconnect delays

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Delay modeling - the barrier effect

The specific resistance (b ) of the barrier layers is higher than that of the Cu, (Cu)

Without barrier:HW

LCuρR w/o

L)b2tW(Hb2t

Bρ1

L)b2t(H)b2t(W

Cuρ1

WR1

With barrier (tb: barrier thickness)

H

W

L: line length

Assumption: complete barrier coating

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Cu Damascene interconnect resistivity

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Effect of the barrier layer on the interconnect delay

Interconnect delay Tint ~ Rint*Cint - including the barrier.

In the case of a Damascene technology:

1

)2)((1barrier w/oint,

int

TT

Cub

WHbtWbtH

Cub

For b >> Cu we get the the interconnect delay increases as the ratio between the actual copper line cross section and the total cross section.

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Barrier layers - overview

Why do we need barriers ?

Requirements from barriers

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Barrier layers for Cu metallization

Why do we need barrier layers? Copper affects Si properties Cu affects SiO2 properties Cu affect most insulators properties Cu adheres poorly to bottom and side ILD

Why do we need a top barrier (capping layer) Cu corrodes Cu adheres poorly to top ILD

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Requirements from barrier layers

• Step coverage on high aspect ratio holes and trenches

•Low thin film resistivity

•Adhesion to the ILD

•Adhesion to Cu

•Stable at all process temperatures

•Process compatible to the ILD

•Process compatible to CMP

•Act as a good barrier

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Barrier layers - types

Sacrificial Stuffed - impurities in the grain

boundaries Amorphous - no grain boundaries

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Diffusion barrier - classification of the candidates for barriers that has been investigated in the last 15 years

transition metals transition metal alloys transition metal - silicon transition metal nitrides, oxides, or borides Miscellaneous: ternary alloys, -carbon,

etc.

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Summary of barrier layer classification

Transition metals fail as barrier at lower temperatures than their nitrides

transition metal silicides fail due to the reaction of the Si with the Cu. The reaction is most likely to happen at the grain boundaries

Amorphous barriers offer very high reaction temperatures, however, they have very high specific resistivity

The barrier properties depend also on the deposition method.

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Process development and manufacturing

considerations

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Step coverage issues

Barrier layer too thick

Barrier layer too thin

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Coverage issues

Nonuniform sidewall deposition:

• agglomeration

• Bad coverage at the bottom corner - can be amplified if the bottom corner has some overetch of the layer below

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The effect of pre-deposition clean on the barrier integrity

Physical process in Ar+ ions Reactive clean

Problems• Damage to the barrier • Damage to the dielectric• Barrier metal and Cu• Sputtering and re-deposition on the sidewalls

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Copper patterning

Dry etch Difficult, expensive Conventional equipment

Dual Damascene Fully planar, lower cost, New technology

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Cu process options

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Electroplating solutions

• Cu ions - Cu sulfate

• Acid - H2 SO4 for pH adjustment

• HCl - Affects Cu surface adsorption; Halide ad-layer drives Cu growth. It also acts as a surfactant and stabilizes grain growth. Cu deposition is driven by the desorption of the halides.

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Electroplating Based Process Sequence

Simple, Low-cost, Hybrid, Robust Fill Solution

Pre-clean IMP barrier + Copper Electroplating CMP

25 nm 10-20 nm + 100-200 nm

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• PVD Ta,TiN, and TaN Neutrals sputtering

Collimated & Non collimated Ions sputtering

RF ionizedHCM- Hollow Cathode Magnetron

• CVD of TiNIodine or Chlorine based chemistry

• CVD of Ta and TaN (or both)Bromide based chemistry

• MOCVD of TiNTDMAT & TDEAT

Diffusion barrier for Copper (I)

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PVD barrier technologies

RF

Target

Substrate

DC magnetron sputtering

Target

Substrate

Collimated sputtering

Target

Substrate

Bias

IMP - Ionized Metal Plasma

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Diffusion barrier comparison, (M. Mossavi et al., IITC 98)

Properties Ta - IMP TaN - IMP TiN - CVD

Resistivity 170 .cm 250 .cm 130 .cm

Stress +350 MPa +1500 MPa -750 MPa

Barrierperformance

6x1016 at/cm3 6x1017 at/cm3 1017 at/cm3

Sidewall/bottomcoverage(0.3m)

20%/40% 40%/40% 100%/100%

CMP selectivityvs. Cu

23 20 1

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Vias with IMP TaN

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Sputtered WxN barrier

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MOCVD TiN Precursors: Tetrakis-dimethylamino Titanium

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Other Novel barriers

RuO2 =40-250 cm

TaSiN,TiSiN =200-600 cm

WBN =300-10000 cm

CoWP =20-120 cm

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Electroless barriers

Wet activation (Pd activation)

on Si

Dry (Ion beam sputtered

seed) on SiO2/Si

1. PdCl2 activation 2. Copper on titanium

3. Cobalt on titanium

Surface activation methods

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Advantage of Electroless barriers Conformal Low cost Good quality - low , low stress can be integrated with electroless copper

Barrier

Cu

ILD

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Co(W,P) barrier layer

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Specific resistivity vs. solution composition

[W-ion]/[Co++]

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35

log

()

4e-5

5e-5

6e-5

7e-5

8e-5

9e-5

1e-4

1-as deposited film

2 - 100oC annealing

3 - 200oC annealing

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Barrier layers modeling

•Diffusion models - kinetics

•Reaction models - thermodynamics

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Equilibrium thermodynamics of diffusion barriers (C.E. Ramberg et al., Microelectronics Microengineering, 50

(2000) 357-368)

Cu makes silicides with silicon Barriers include transition metal+metaloid (Si,B,or N)

Binarysystem

Solidsolution

Crystalstructure

Tendencyto phase

Conductivity

TM-N Broad Simple Poor Good

TM-Si Narrow Moderate Fair VariableTM-B Narrow Complex Good Good

Si-N,BN

Narrow Complex Very good Poor

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Ternary phase diagrams

Cu Ta

N

TaN

Ta2N

TiCu Cu4Ti Cu4Ti3 CuTi CuTi2

N

TiN

Ti2N

•The lack of Ta-Cu compounds yield a broad range of compositions in equilibrium with Cu.

•Ti-rich compositions are expected to react with Cu

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Barrier Analysis & monitoring

Materials science techniques: AES, SIMS, RBS, SEM

Electrical characterization: I-V C-V & C-t

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ID: Sample Final Structure:

MOS1 Reference capacitors Al/SiO2/Si No barrier at all,Al metallization

MOS2 Reference capacitor Barrier/SiO2/Si Just the barrier

MOS3 Test device Barrier/Cu/Barrier/SiO2/Si Copper betweentop and bottombarrier layers

Electrical characterization: MOS capacitors

Capacitance measurements:

CV: Flat band voltage, interface states

Ct : minority carrier lifetime, surface recombination velocity

IV &It: metal/insulator integrity.

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-4 -3 -2 -1 0 1 2 3 4 5

0.0

0.2

0.4

0.6

0.8

1.0

High Frequency capacitance Low Frequency capacitance

C/C

OX

Voltage (Volt)

Ideal MOS capacitance-voltage curve. Solid curve - High f , Dotted curve Low frequencies.

Oxide thickness is 140. NA = 1·1015 cm-3.

High frequency

High frequency - fast sweep

Relaxation

Low frequency

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Example:

test of CoWP barrier layers

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CV characteristics of MOS capacitor with a. Co(W,P)/Co and b. Co(W,P)/Cu/Co(W,P)/Co metallization after 300ºC 30 min.

and 520ºC for 2 hours anneal. (A= 3.57·10-4 cm2).

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 60.0

0.2

0.4

0.6

0.8

1.0

(a)

Voltage (Volts)

C/C

ox

After 300C, 30’After 520C, 30’

(b)

0.0

0.2

0.4

0.6

0.8

1.0

C/C

ox-6 -5 -4-3 -2 -1 0 1 2 3 4 5 6

Voltage (Volts)

After 300C, 30’After 520C, 30’

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C-t curves of Co(W,P)/Cu/Co(W,P)/Co/SiO2 capacitors annealed at 400C, 500C and 520C. Device area is 3.57·10-4 cm2.

0 50 100 150 200 250 300 350 400 450 500 550 6004.4E-12

4.6E-12

4.8E-12

5.0E-12

5.2E-12

5.4E-12

5.6E-12

5.8E-12

6.0E-12

Time (sec)

Cap

acit

ance

[F

]

400C, 30 min. 500C, 30 min520C, 2 hourshours

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Generation lifetime, g (sec), and Surface Recombination velocity, So, (cm/sec)

Al/Co CoWP/Co CoWP/Cu/CoWP/CoAnneal

conditions

g

(s)So

g

(s)So

g

(s)So

As-deposited 65 3.2 74 2.1 58 1.2300 C, 30’ 55 1.6 63 0.9 62 1.3

400 C, 30’ - - - - 52 2

500 C, 30’ - - - - 17 0.9

520 C, 2 hr - - 46 1.3 8 1.3

600 C, 4 hr - - - - 1-2 0.8

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Copper profiles as measured by AES. The sputtering rate was: 12A/min for Co(W,P) on Cu, 25 A/min for Cu, 10A/min for Co(W,P)

on Co, 8A/min for the sputtered Co.

0 10 20 30 40 50 60 70 80 90 100 110 120 130 1400

5

10

15

20

25

30

35

40

Con

cent

ratio

n (

Arb

.)

Sputtering Time (min)

Co(W,P) Cu Co(W,P) Co SiO2 Si

600C, 4hr.

As deposited

520C, 2hr

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Barrier monitoring techniquesX-Ray fluorescence (XRF) -

thickness and composition (accurate, 5-10 points / min)

X-Ray reflection:

Thickness

(Most accurate, 2-5 points / min))

Ellipsometry:

Thickness (low accuracy, fast)

Resistivity

Others…….?..?

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X-Ray reflectivity - Sputtered TiNdBarrier=30.5 nm, =5.2 gr./cm3

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References

Shi-Qing Wang, “Diffusion barriers for Cu metallization on Silicon”, Proceedings of the advanced metallization conference, MRS publications, San-Diego, 1993.

The proceedings of the Advanced metallization conferences from 1993 to 1999

The proceedings of the Workshop for Advanced Metallization (MAM) from 1997 and 1999

Papers in various journals such as the Journal of electrochemical society, Journal Vac. Sci.Tech., J. of Appl. Phys., J. Material research and more.

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Conclusions

Dominant barriers for Cu technology are Ta (IMP), TaN (IMP) & TiN (CVD)

There are still problems, especially in high aspect ratio features

Other barriers are under study (amorphous, electroless, etc.)

Barrier technology is an enabling technology for ULSI metallization