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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010 827

Pseudo-Two-Dimensional Model for Double-GateTunnel FETs Considering the Junctions

Depletion RegionsMarie Garcia Bardon, Herc P. Neves, Member, IEEE, Robert Puers,Senior Member, IEEE, and

Chris Van Hoof,Member, IEEE

AbstractThis paper presents a pseudo-2-D surface poten-tial model for the double-gate tunnel field-effect transistor(DG-TFET). Analytical expressions are derived for the 2-D po-tential, electric field, and generation rate, and used to numeri-cally extract the tunneling current. The model predicts the devicecharacteristics for a large range of parameters and allows gaininginsight on the device physics. The depletion regions induced insidethe source and drain are included in the solution, and we show

that these regions become critical when scaling the device length.The fringing field effect from the gates on these regions is alsoincluded. The validity of the model is tested for devices scaled to10-nm length with SiO2 and high-dielectrics by comparison to2-D finite-element simulations.

Index TermsAnalytical modeling, band-to-band tunneling,gated p-type-intrinsic-n-type diode, Poissons equation, tunnelfield-effect transistor.

I. INTRODUCTION

TRANSISTORS based on the tunneling current ap-

pear as promising candidates to replace the conven-

tional MOSFETs for low-power applications. Contrary to

MOSFETs, the subthreshold slope of tunneling field-effecttransistors (FETs) is not limited to 60 mV/dec [1], allowing

further reduction in the supply voltage. In addition, tunnel field-

effect transistors (TFETs) should show a very small leakage

current, in the range of femtoamperes [2], due to the large

tunneling barrier formed when the device is turned off. The use

of a double-gate configuration and the replacement of the gate

oxide by high-dielectrics were proposed to boost the currentin the O N-state [3], [4].

So far, the performance of these devices is mostly predicted

on the basis of finite-element simulations [5][7]. Analytical

models would be useful to provide fast results, together with

Manuscript received August 12, 2009; revised December 10, 2009. Firstpublished February 17, 2010; current version published April 2, 2010. Thereview of this paper was arranged by Editor D. Esseni.

M. G. Bardon is with the Interuniversity MicroElectronics Center, 3001Leuven, Belgium, and also with the Katholieke Universiteit Leuven, 3000Leuven, Belgium (e-mail: [email protected]).

H. P. Neves and C. Van Hoof are with the Interuniversity MicroElectronicsCenter, 3001 Leuven, Belgium.

R. Puers is with the Katholieke Universiteit Leuven, 3000 Leuven, Belgium.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TED.2010.2040661

Fig. 1. Schematic representation of the DG-TFET modeled in this paper. ThePoissons equation is solved on the three regions R1, R2, and R3, correspondingto the intrinsic region (R2) and to the depletion regions induced by the junctionsinside the source and drain (R1 and R3). The figure shows the conventionadopted for thex- andy-axis and for the nodes between regions.

further insight on the working principle of the device, and to

allow circuit simulations. However, few analytical models have

been proposed for the TFET [8][10]. One of the reasons is thatthe conduction in TFETs is fundamentally different than that in

MOSFETs [7], [11], and new modeling approaches have to be

proposed.

In a double-gate TFET (DG-TFET), as shown in Fig. 1,

electrons tunnel from the valence band in the p-doped source

to the conduction band in the intrinsic body and then move

toward the n-doped drain by drift diffusion. Tunneling occurs

in regions of high electric field, where the local band bending

reduces the width of the forbidden band gap. This bending

is achieved by increasing the gate voltage, which pushes the

energy bands downward in the intrinsic region (Fig. 2). It was

shown that the current generation does not uniformly happenalong the sourcebody interface but mainly occurs in the areas

close to the gates [9], [12]. It was also shown that the drain

voltage does not influence the tunneling, provided that the

device is long, but starts degrading the characteristic if the gate

length is reduced [13].

Previous work on TFET modeling is based on the 1-D

solution of the Poissons equation along the tunneling path [8]

or on the pseudo-2-D solution [10]. Pseudo-2-D solutions have

extensively been used for MOSFETs in which 2-D effects have

to be considered [14][16] but not applied to the TFET before

[10]. In both approaches, the domain of resolution is limited to

the silicon intrinsic body. These models do not provide simple

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828 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

Fig. 2. Energy band diagrams of the DG-TFET in the OFF-state (Vg =0 V,top) and in the ON-state (Vg = 1.2 V, bottom) from Medici simulations. Thedepletion regions extending in the drain and source have a nonnegligible length,compared with the intrinsic region, and must be taken into account.

expressions for the currentvoltage characteristics and cannot

explain the impact of the drain.

This paper develops a model for the potential, electric field,

and current in the DG-TFET. The potential and electric field

are calculated using the pseudo-2-D solution of the Poissons

equation. The domain of resolution is not limited to the intrinsic

body but extended to include the junction depletion regionsinside the source and the drain. The current is derived from

the electric field using Kanes model. This paper is structured

as follows: In Section II, we analyze the potential and electric

field distributions from 2-D finite-element simulations in order

to get a better understanding of the device and define the

model assumptions. In Section III, we solve the 2-D Poissons

equation on three regions, i.e., the intrinsic region and the

two depletion regions inside the source and the drain, taking

into account the fringing field effect from the gate electrodes.

The validity and applicability of the model are examined in

Section IV for different sets of parameters. In particular, the

impact of scaling and high-dielectrics is studied.

II. OBSERVATIONSF ROM S IMULATIONS

The simulations are performed with the device simulator

Medici. In all simulations, we used the doping values proposed

in [3]: the doping concentration is N1= 1020 cm3 in the

p-type source, N2= 1017 cm3 in the intrinsic region, and

N3= 5 1018 cm3 in the n-type drain, with abrupt doping

profiles. Since a doping concentration of 1017 cm3 was used

for the intrinsic region to avoid convergence problems in the

simulations, we will not refer to this region as an intrinsic region

further in the text but as a lightly doped region or as a silicon

body (with the term intrinsic usually referring to dopingconcentrations of up to 1016 cm3). However, the results for

lower doping concentration are similar. This silicon body has

a thicknessts = 10 nm, and the gate dielectric has a thicknesstr =3 nm. The gate work function ism = 4.5 eV. Dependingon the simulation, the silicon body has a length of 50, 20, and

10 nm, and the gate dielectrics has a dielectric constant r =3.9orr =21. Band-gap narrowing is enabled.

By looking at the 2-D distribution of the potential and theelectric field in Fig. 3 obtained by finite-element simulations,

several observations can be made.

1) Along the y-axis, the potential varies near or acrossthe junctions, whereas it is constant in the middle of

the silicon body [13]. When the device is turned on

[Fig. 3(b)], the potential variation is localized near the

tunneling junction. As a consequence, there is a lateral

electric fieldEyacross the two junctions when the deviceis off, whereas a peak value appears at the tunneling

junction when the device is on, and there is no lateral field

elsewhere. The zone of constant potential in the silicon

body is due to the gates and differentiates the TFET from

the p-i-n junction (the same device without gates), which

would have a constant lateral electric field between the

p-source and n-drain.

2) The profile of the lateral electric field Eystays unchangedin the depth of the device. Hence, knowing Ey(y) on across section taken at any depthx is sufficient to deducethe lateral field for the full film depth Ey(x, y).

3) The voltage Vgon the gates mainly affects the global levelof the potential in the silicon body, increasing the field

across the tunneling junction. Vg induces only a slightbending of the potential through the depth of the device

(along thex-axis), which is a bending that is more impor-tant at the junctions, as visible from the vertical electric

fieldEx. This bending cannot be neglected, because thetwo components of the electric field (i.e., Ex and Ey)have similar values at the junction edge; hence, both are

responsible for the current generation. The shape of the

potential between the two gates is parabolic.

4) Because of this parabolic shape, the maximum of the

vertical electric field Ex is attained near the interfacewith the dielectrics. The maximum total electric field is

therefore localized at the sourcebody interface near the

gates, explaining that tunneling mainly happens in these

points. Because of the magnitude ofEx, the current flowwill partially be directed toward the gates [3].5) There is a vertical electric field within the source and the

drain, suggesting that there is also some control of the

gates on these regions.

6) The potential does not abruptly reach the drain Fermi

level at the end of the lightly doped zone but continues

to vary inside the drain, showing that the length of the de-

pletion region is not negligible. (The edge of the depletion

region is where Eyreaches zero, and the potential reachesa constant value.) The extension of the depletion region

is significant because of the low doping level used in the

drain to make the device unipolar. This is also visible in

Fig. 4, which shows the potential along a cross sectionin the device length. When the gate voltage is increased,

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BARDON et al.: PSEUDO-TWO-DIMENSIONAL MODEL FOR DOUBLE-GATE TUNNEL FETs 829

Fig. 3. Two-dimensional distribution of the potential(x, y), of the vertical component of the electric field Ex, and of the lateral component of the electric field

Ey(inverted for a better visualization) in the TFET at (a)Vg = 0 V and (b) Vg =1.2 V from finite-element simulations. The lightly doped region has a length of50 nm, the dielectric constant isr =21, and the drain voltage is Vd = 1 V.

Fig. 4. Front surface potential for gate voltages ramping fromVg =0 V toVg =1.4 V in steps of 0.2 V (L2 = 50 nm, r =3.9, and Vd = 1 V). Thevertical lines show the limits of the three regions of resolution R1 (the depletionregion inside the source), R2 (lightly doped region), and R3 (the depletionregion inside the drain) corresponding to Vg = 0 V.

the length of the depletion region in the drain reduces,

whereas the depletion in the source enlarges.

III. MODELD ERIVATION

We solve the 2-D Poissons equation on the three regions

R1, R2, and R3, as defined in Fig. 1 for the potential and

electric field. We then calculate the lengths of depletion regions

R1 and R3. Finally, we extract the current from the tunneling

generation rate.

A. 2-D Poissons Equation

We want to predict the characteristic of the device from

the OFF-state to the onset of the ON-state. In this regime, themobile charge has a negligible influence on the electrostatics

of the device [10]. The Poissons equation can therefore be

written as

2(x, y)

x2 +

2(x, y)

y2 =

qNss

(1)

where(x, y)is the electrostatic potential in the substrate mea-sured with respect to the bulk Fermi level.Ns is the film effec-tive doping used to simplify the calculations and is equal to N1in the p-type source (region R1), N3 in the n-type drain (re-gion R3), and N2in the lightly doped region R2 (with the signindifferent for low doping).s is the silicon dielectric constant.

The gate does not overlap the source and drain in the pro-

posed structure. However, the simulations showed that the po-

tential significantly varies on the depletion regions, particularly

on the drain side. We also suppose that these regions can be

under the influence of the gates through fringing field effects.

Therefore, we solve the Poissons equation in two dimensions

on three regions, i.e., the lightly doped region and the two

depletion regions. Seeing the parabolic shape of the potential

in depth, the potential can be approximated by the second-

order polynomial, an approximation previously verified for

double-gate devices [17], [18]

(x, y) =a0(y) +a1(y)x+a2(y)x2. (2)

Four vertical boundary conditions have to be fulfilled on each

of the region to ensure the continuity of the potential and of the

electric displacement at the surfaces of the thin film (at x = 0andx = ts)

(0, y) =s(y)

(ts, y) =b(y)

Ex(0, y) =

ts(G s(y))

Ex(ts, y) = ts

(b(y) G) . (3)

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In these equations, s(y) =(0, y) is the front-side sur-face potential, and b(y) =(ts, y) is the back-side surfacepotential. The gate potential G is referred to the substrateFermi level, so that G = Vg m++Eg/2. ( and Egare the electron affinity and the band gap of the silicon body,

respectively.) We define a parameter = Cr/Cs, i.e., the ratio

between the gate capacitance Cr and the thin-film capacitanceCs= s/ts. The gate-oxide capacitance is Cr =r/tr in thelightly doped region R2. On the depletion regions R1 and R3,

the fringing field effect is taken into account by conformal

mapping techniques asCr =2/ r/tr [18].Applying the boundary conditions to (2), the coefficients a0,

a1, and a2 can be rewritten as a function of the front-gatesurface potentials(y), i.e.,

a0(y) = s(y)

a1(y) =

ts(s(y) G)

a2(y) =

t2s

(s(y) G) .

Using the polynomial in (2), the 2-D Poissons equation is

transformed into the following 1-D differential equation in s:

s(y) k2s(y) = k

2d (4)

with

k=

2/t2s

d= t2s2

qNss

2

t2sG

.

The parameters k and d have a particular value on each

of the regions R1, R2, and R3 due to the different dopingand gate capacitances. 1/kis the characteristic length or decaylength in each region, and d is equal to the solution ofthe 1-D approximation of the Poisson equation (long-channel

approximation).

B. 2-D Potential and Electric Field

On each segment [yi1, yi] delimiting the region Ri, asdefined in Fig. 1, the front surface potential is the solution of

(4) and has the general form

si(y) =bieki(yyi1) +cie

ki(yyi1) +di. (5)

The coefficients bi andci can be expressed in terms of thelength of the regionLi = yi yi1and of the boundary valuesof the potentiali1 and i at each side of the segment

bi = 1

2 sinh(kiLi)

i1e

kiLi di(1 ekiLi) + i

ci =

1

2 sinh(kiLi)

i1e

kiLi +di(1 ekiLi) i

. (6)

The boundary values of the potential at source end 0 anddrain end n are the Fermi potential levels of the source andthe drain, i.e.,

0= kT/qln(N1/ni)3= (kT/q)ln(N3/ni) +Vd

whereVd is the drain voltage. The intermediate potentials 1and2are found by continuity of the lateral electric field at thesurface and given in compact form in the Appendix.

The potential in the substrate (x, y) is obtained from thesurface potential through (2). The vertical electric field Ex andthe lateral electric field Ey are found by analytic derivation of

the potential as

Ex(x, y) = a1(y) +2a2(y)x

Ey(x, y) = kibieki(yyi1) kicie

ki(yyi1). (7)

Following our observations, we consider that the lateral

electric field is uniform in the depth of the film and equal to

its surface value.

C. Length of the Depletion Regions

We now calculate the lengths of regions R1 and R3 due to

the charge depletion inside the source and drain regions. The

space charge is due to the sourcebody and bodydrain diodes.In a diode, the length of the depletion can be calculated from

the potential drop across the junction [19]. Since the TFET

is a gate diode, the potential in the body is modulated by the

gate voltage. To consider the influence of the two terminals on

each other, ideally, L1and L3should be calculated by imposingEy =0 aty = y0andy = y2before deriving the continuity po-tentials2 and 3, but the calculation would be cumbersome.A good approximation is made, separately considering the two

junctions. The length of the depletion regions therefore depends

on d2, which is the potential in the silicon body due to thegates without influence of the junctions. L1 and L3 are thencalculated as

L1=

2s(d2 0)/ (q|N1|)

L3=

2s(3 d2)/ (q|N3|). (8)

We see that L1 andL3 depend on the gate voltage throughd2. When Vg increases,L1 increases, whereasL3 decreases,as suggested by our initial observations. The drain voltage

influencesL3through3, and whenVdincreases, the depletionat the drain side increases.

D. Current

The current Id is found by integration of the band-to-bandgeneration rateGbtbon the volume of the device

Id= q

GbtbdV. (9)

The Medici simulator uses Kanes model [20] to evaluate the

band-to-band generation rate according to the following:

Gbtb= A|E|2

Egexp

B

E3/2g

|E|

. (10)

In this expression, |E| is the magnitude of the electricfield, and Eg is the energy band gap. The parameters A

and B used are the default parameters of Medici (A= 3.5 1021 eV1/2/cm s V2 andB = 22.5 106 V/cm (eV)3/2).

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Fig. 5. Comparison of the results obtained from (dots) simulations and (lines)our model for the vertical electric field at the surface (front side) forVg = 0 V

andVg = 1.2 V(L2 = 50 nm, r =3.9, Vd = 1 V).

The local band-to-band tunneling model was employed, so

that Gbtb is calculated from the magnitude of the electricfield at each node. We use the same approach to calculate the

generation rate from the analytical expression of the magnitude

of the electric field |E| =

E2x+E2y , with Ex andEy given

by (7). Finally, the current at the source and drain terminals is

calculated by numerical integration ofGbtb. Although the mo-bile charge was neglected in the model derivation, the current

can be predicted with this approach, because (10) depends on

the electric field distribution in the device. From the OFF-state

to theON -state, this field distribution is mainly controlled by thefixed charge and is therefore accurately predicted by our model,

as verified in the next section.

IV. MODELE VALUATION

The model is tested against the simulation results for dif-

ferent sets of parameters. We verify that the potential and

the components of the electric field are well predicted for

different biasing conditions. The validity is further tested when

scaling the gate lengths (50, 20, and 10 nm) and for different

gate dielectrics (r =3.9 and r =25). Finally, we extract therecombination rate and the current.

A. Validation of Potential, Electric Field, and Current

The model is first tested on a TFET with a body of

50-nm length and with SiO2 as gate dielectric, under a change

in gate voltage. The accurate prediction of the potential and

fields at low gate voltage is critical since it will condition the

OFF-current and the subthreshold slope, which are the two key

parameters for the TFET used as switch. Fig. 4 shows the

surface potential for a variation of the gate voltage from 0 to

1.4 V by a step of 0.2 V. As the gate voltage increases, the

potential in the lightly doped region increases. The length of the

depletion region inside the drain is important at low gate voltageand decreases as the gate voltage increases. The variation of

Fig. 6. Comparison of the results obtained from (dots) simulations and (lines)our model for the lateral electric field at the surface (front side) for Vg = 0 VandVg =1.2 V(L2 = 50 nm, r =3.9, Vd = 1 V).

Fig. 7. IdVg characteristics predicted by finite-element simulations and byanalytical model for various lengths of the silicon body L2 of 50, 20, and10 nm (Vd = 1 V, r = 3.9).

the surface potential is accurately predicted not only along

the body but also inside the drain due to the inclusion of the

depletion region R3. Figs. 5 and 6 show how the model can

predict the vertical and lateral components of the electric field

forVg =0 V andVg =1 V.The resulting drain current is shown in Fig. 7. The results

predicted by the model are in agreement with the simulations

and predict the characteristic of the device with 50-nm length

for the subthreshold slope and the O N-current. The O FF-current

is slightly overestimated. We now consider the impact of scal-

ing and gate dielectric material on the device.

B. Scaling

TFETs are expected to stand scaling better than MOSFETs

since the barrier formed by the forbidden band gap should

prevent tunneling to happen in the OFF-state. The OFF-current

Ioff is hence supposed to be limited to the leakage current

of the reverse-biased sourcebody diode. Contrary to theseexpectations, it was observed that shrinking the device leads

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Fig. 8. Influence of the scaling on the energy band diagrams in the OFF-state (Vg = 0 V and Vd = 1 V) in a horizontal cross section of the bodyat the surface (front side) for two different gate lengths L2= 50 nm andL2= 20 nm(r =3.9). Results are from (dots) simulations and (continuous

lines) model. The vertical lines show the limits of the two lightly doped zones.

Fig. 9. Vertical and lateral electric fields at the surface of a device withL2=20 nm for Vg =0 V and Vg =1.2 V (Vd = 1 V, r =3.9), as predicted by(dots) simulations and by (continuous lines) our model.

to an increasedIoffand a degradation of the subthreshold slope[13], [21], as shown in Fig. 7. It also leads to a higher slightly

higherO N-current [13]. Our analytical model is able to describe

these effects.Fig. 8 shows the energy band diagrams of TFETs with 50-

and 20-nm lengths in the OFF-state (Vg =0 V), with SiO2as dielectric. The bands are taken at the surface of the front

side, the valence band is found from s(y) Eg/2, and theconduction band is found from s(y) +Eg/2. For the 50-nmdevice, there is a zone with almost constant potential inside the

silicon body. For the 20-nm device, the drain starts having an

influence on the potential distribution in the silicon body: the

drain pulls the bands downward. There are two consequences:

1) There is no longer a plateau in the potential inside the lightly

doped zone. (b) The width of the barrier is slightly reduced

at the tunneling junction because of the change in slope. The

disappearance of the flat zone will cause a global increase inthe current, because a lateral electric field Ey is now present on

Fig. 10. Vertical and lateral electric fields at the surface of a device with L2=10 nm for Vg =0 V and Vg =1.2 V (Vd = 1 V, r =3.9), as predicted by(dots) simulations and by (continuous lines) our model.

Fig. 11. Surface potential for an increasing drain voltage (Vd = 0 V, 0.4 V,0.8 V, 1.2 V, 1.6 V; L2= 20 nm,r =3.9, and Vg =1 V). The vertical linesshow the limits of the three regions of resolution R1, R2, and R3 for Vd =1.6 V.

the full device length at any gate voltage, as shown in Fig. 9

for L2= 20 nm and in Fig. 10 for L2= 10 nm. Hence, theconduction is increased by drift after the current generation at

the junction, and this effect becomes more important as the

device scales. This current increase is slightly visible on Fig. 7and is in agreement with the observations from [3].

The change in the barrier width on the tunneling junction

will, on the contrary, only impact the O FF-current. The change

in the slope is reflected in an increased peak value of the lateral

electric field atVg =0 V: the peak value ofEy is 1.1 V/cm forthe 20-nm device (Fig. 9) and 1.5 V/cm for the 10-nm device

(Fig. 10). The probability of tunneling to occur increases for

lowVg and explains the degradation of the leakage current inFig. 7. WhenVg =1 V, on the contrary, there is no differencein the peak value ofEy between the two devices.

To further study the impact of the drain, Fig. 11 shows how

Vd influences the potential on the tunneling junction for the

20-nm device. AsVd increases, the lightly doped zone receivespart of the potential variation, and the slope at the tunneling

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Fig. 12. Influence of the dielectric material on the energy band diagramsin the OFF-state and comparison between the simulation and the model. Thehigh-dielectric constant material(= 21)provides better control on the siliconbody, compared with the SiO2(= 3.9).

junction is affected, whereas, for a long-channel device, the

bodydrain junction was absorbing the increase in Vd (this isthe case in Fig. 4 forVd = 1 V). The prediction of the impact ofthe drain voltage is possible, because the drain depletion region

is included in the domain of resolution.

C. High-Dielectrics

The degradation of the characteristics with scaling is due to

a loss of control of the gate: the gate loses control on the lightly

doped region and can no longer be able to properly turn the

device off [13]. As the gate loses control, the zone of constantpotential in the silicon body disappears, and the potential dis-

tribution becomes more and more similar to a p-i-n junction.

To maintain this flat region also for short device lengths, the

gate control can be improved using high-dielectrics, in placeof SiO2 [3]. Fig. 12 compares the band diagrams of a device

in the OFF-state using a gate dielectric with dielectric constant

r =3.9 or r =21. The device with the high- reintroducesthe zone of constant potential, increasing the bending on the

junctions edges. Our model predicts well the change in bands

induced by the high-. The extension of the depletion regionsinside both the source and the drain increases because of the

change in potential induced by the gates inside the lightly dopedregion.

V. CONCLUSION

In this paper, analytical expressions have been derived for the

2-D electric potential and electric field of the DG-TFET based

on the pseudo-2-D solution of the Poissons equation. The

components of the electric field have been used to analytically

calculate the distribution of the tunneling generation rate and

numerically extract the tunneling current. We have shown that

the models predict the device characteristics on a large range

of parameters and permit to gain insight on the device physics.

The inclusion of the drain depletion region in the domain ofresolution allows predicting the impact of the drain on the

tunneling junction, which is an effect that becomes important

when scaling down the device length. The model can also

predict the improved control of the gate on the intrinsic region

when using high-dielectrics.

APPENDIX

The intermediary potentials i between the segment i andthe segmenti+ 1are fixed by the continuity of the electric field

dsidy

y=yi

=ds(i+1)

dy

y=yi

(i= 1, . . . , n 1).

The boundary potentials are a function of the potentials on

the source and drain 0 and3, of the lengths of the regionsLi, of the coefficientki, and of the potential di, as defined inthe text. By defining for each region i (i= 1, 2, 3)an equivalentpotentialVi and a coefficientsi

Vi = [1 cosh(kiLi)] di

si = ki/ sinh(kiLi)

and for(i= 1, 2)a weighti

i = kicoth(kiLi) +ki+1coth(ki+1Li+1)

the intermediary potentials can be written in the following

compact form:

1= 1

[2s1(0 V1) + (2+s2)s2V2+s2s3(3 V3)]

2= 1

[s1s2(0 V1) + (1+s2)s2V2+1s3(3 V3)]

where

=12 s22.

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Marie Garcia Bardonreceived the M.Sc. degree inelectromechanical engineering from the UniversitCatholique de Louvain, Louvain-la-Neuve, Belgium,in 2004. She is currently working toward thePh.D. degree at the Katholieke Universiteit Leuven,

Leuven, Belgium, in collaboration with the Interuni-versity Micro-Electronics Centre (IMEC), Leuven,working on the fabrication, characterization, andmodeling of suspended-gate transistors (SG-FETs).

She is also a Research Scientist with the Technol-ogy Aware Design Group at IMEC, where her work

involves compact modeling of advanced devices for digital circuit applications.Her research interests include the simulation and compact modeling of newdevice architectures.

Herc P. Neves (M92) received the Ph.D. degree inmicroelectronics from the University of Edinburgh,Edinburgh, U.K., in 1991, for his work on hot carriereffects.

He has held academic positions at the Depart-ment of Electronics Engineering and Department ofPhysics, Federal University of Minas Gerais, BeloHorizonte, Brazil; the School of Electrical Engi-

neering and Department of Biological and Envi-ronmental Engineering, Cornell University, Ithaca,NY; and Biomedical Engineering IDP, University of

California, Los Angeles. In 2003, he joined the Interuniversity MicroElectron-ics Center, Leuven, Belgium, as a Biomedical Microsystems Principal Scientist,where his work focuses on implantable microsystem technology. He is alsothe Coordinator of NeuroProbes, which is a project funded by the EuropeanCommission for the development of multifunctional probe arrays for cerebralapplications.

Robert Puers(M86SM95) was born in Antwerp,Belgium, 1953. He received the B.S. degree inelectrical engineering from the Universiteit Gent(UGent), in Ghent, Belgium, in 1974 and the M.S.and Ph.D. degrees from the Katholieke UniversiteitLeuven (KU Leuven), Leuven, Belgium, in 1977 and1986, respectively.

In 1980, he was a Research Assistant with theLaboratory ESAT, KU Leuven. In 1986, he becamethe Director (NFWO) of the clean room facilities forsilicon and hybrid circuit technology at the ESAT-

MICAS Laboratories, KU Leuven. He was a pioneer in the European researchefforts in silicon micromachined sensors, MEMS and packaging techniques,biomedical implantable systems, and industrial devices. In addition, his generalinterest in low-power telemetry systems, with the emphasis on low powerintelligent interface circuits and on inductive power and communication links,has promoted the research of the ESAT-MICAS Laboratory to internationalrecognition. He is currently a Full Professor with KU Leuven. He is the Editor-in-Chief of the IOP Journal of Micromechanics and Microengineering, and theAssociate Editor for Sensors&Actuators. He is the author or coauthor of morethan 400 papers on biotelemetry, sensors, MEMS, and packaging in reviewed

journals or international conference proceedings.

Dr. Puers is a Fellow of the Institute of Physics (U.K.), a Council Memberof the International Microelectronics and Packaging Society, a member of theElectron Device Society, and many others. He is an Associate Editor for theIEEE JOURNAL ON SENSORS.

Chris Van Hoof(M87) received the Ph.D. degree inelectrical engineering from the University of Leuven,Leuven, Belgium, in collaboration with the Interuni-versity MicroElectronics Center (IMEC), Leuven,in 1992.

He is currently the Director of the Integrated Sys-tems Department of the Microsystems, Componentsand Packaging Division, IMEC, Leuven. Since 2000,he has also been a Guest Professor with the Univer-sity of Leuven. At IMEC, he became the Head of the

Detector Systems Group (1998), the Director of theMicrosystems Department (2002), and the Director of the Integrated SystemsDepartment (2004). He has contributed to two cornerstone ESA flight missions.He is currently the promoter of eight doctoral theses. He has authored morethan 130 publications (with more than 70 based on peer review) and has given20 invited presentations. His research interests include several key ingredientsof autonomous sensor nodes (sensor front ends and energy scavenging) andadvanced packaging and interconnect technology (2-D and 3-D integration, andRF integration).

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