Balsa: A Language Tutorial
description
Transcript of Balsa: A Language Tutorial
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Balsa: A Language Tutorial
Dr. Doug Edwards
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Structural Iteration
constant n = 8
procedure buffer_n (input i : word; output o : word) is
local array 1 .. n-1 of channel c : word
begin
buffer (i, c[1]) || -- first buffer
buffer (c[n-1], o) || -- last buffer
for || i in 1 .. n-2 then -- i’th buffer
buffer (c[i], c[i+1])
end
end
declareconstant
internal arrayedchannels
parallelstructural iteration
compose n-2internal buffers
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Micropipeline Buffer
procedure buffer (input i : byte; output o : byte) is
local variable x : byte
begin
loop
select i then
x := i -- store the data
end;
o <- x
end
end
select enclosesassignment
select “chooses”a single input
resulting in input “i”being passive
select statementhas enclosed semantics
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Examples: Simple Counters
Circuits count handshakes on their I/Ps and produce an O/P count bundle
They illustrate:• strong data typing• data types
– arrays, records, enumeration
• control structures– if, case
• shared procedures
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Modulo-16 binary counter
procedure count16 (sync aclk; output count : nibble) is
local variable count_reg : nibble
begin
loop
sync aclk ;
count <- count_reg ;
count_reg := ( count_reg + 1 as nibble)
end
end
await h/son input
handshakeonly input
inc internalregister
cast result backto correct size
then output countfrom internal register
assign result backto internal variable
4-bitoutput
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Passive Input Counter
procedure count16 (sync aclk; output count : nibble) is
local variable count_reg : nibble
begin
loop
count <- count_reg ;
select aclk then continue end ;
count_reg := ( count_reg + 1 as nibble)
end
end
using select makesaclk a passive i/p
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Modulo-10 counter
procedure count10(sync aclk; output count: C_size) is
local variable count_reg : C_size
variable tmp : C_size
begin
loop
sync aclk ;
if count_reg /= max_count then
tmp := (count_reg + 1 as C_size)
else
tmp := 0
end || count <- count_reg ;
count_reg := tmp
end -- loop end
end
C_size andmax_count previously
declared
if then elseconstruct
temp variableupdated in parallel
with O/P assignment
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Nested if Statements
Balsa does not have an elseif keyword
if condition1 then
procA
else if condition2 then
procB
end
else
procC
end
Note the explicit sequencing
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Parallel Guard Evaluation
If the guards are mutually exclusive, conditions may be tested in parallel:
if condition1 then
procA
| condition2 then
procB
else
procC
end
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Loadable Decade Counter -1
Illustrates record data type:
-- count10b.balsa: an aysnchronous loadable decade counter
import [balsa.types.basic]
public
type C_size is nibble
constant max_count = 9
type In_bundle is record
ld_data : C_size ;
ld_ctrl : bit
end
in-linecomment
record data-structure
definition
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Loadable Decade Counter -2
procedure updown10 (input in_sigs: In_bundle; output count: C_size) is
local
variable count_reg : C_size
variable tmp : C_size
begin
loop
-- main procedure body
end
endbody in next slide
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Loadable Decade Counter -3
select in_sigs then
if in_sigs.ld_ctrl = 0 then
count_reg := in_sigs.ld_data
else
if count_reg /= max_count then
tmp := (count_reg + 1 as C_size)
else
tmp := 0
end || count <- count_reg ;
count_reg := tmp
end -- end if
end -- complete select H/S
enclosed select allowsmultiple reads from I/Pbundle without latches
Record selector
Record selector
increment countor wrap round
load counter
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Padding Record Structures
Records can be coerced to a fixed length:
type Flags is record
carry, overflow, zero, negative, int_en: bit
over byte
Flags is paddedto 8 bits
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Up/Down Counter
Add another bit to control direction of counting:
type C_size is nibble
constant max_count = 9
type In_bundle is record
ld_data : C_size ;
ld_ctrl : bit;
dir : bit
end
direction bit
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Up/Down Counter
case in_sigs.dir of 0 then -- counting down
if count_reg /= 0 then
tmp := (count_reg - 1 as C_size)
else
tmp := max_count
end || count <- count_reg
| 1 then -- counting up
if count_reg /= max_count then
tmp := (count_reg + 1 as C_size)
else
tmp := 0
end || count <- count_reg
end ; -- end case statement
casestatementcount down
or count up
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Enumeration
Up/down control signal could be defined as:
type dir is enumeration
down, up
end
Values may be aliased
type opcode is enumeration
ADD, ADC, SUB, SBC, AND, OR, LD, ST=LD, BR
over 3 bits
aliasedvalues
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Shared Procedures -1
type inc is 2 signed bits
procedure updown10 (input in_sigs: In_bundle; output count: C_size) is
local
variable count_reg : C_size
variable tmp : C_size
variable inc : inc
-- define shared procedure
shared update_ctr is begin
tmp := (count_reg + inc as C_size)
end
-- procedure body
inc takesvalues -1 and +1
sharedprocedure
cast resultto correct size
use shared hardwarefor counting up and down
inc can be +/- 1
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Shared Procedures -2
loop select in_sigs then
begin
if in_sigs.load_l = 0 then
count_reg := in_sigs.ld_data
else
case in_sigs.dir of
down then -- counting down
inc := ( -1 as inc);
if count_reg /= 0 then
update_ctr()
else
tmp := max_count
castrequired
callshared procedure
counting down:set inc to -1
similar codefor count up
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Arrays
Numerically indexed compositions of the same type
Typical use is in the specification of register banks
type RegData is 16 bits
variable RegBank : array 0..7 of RegData
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Register Bank Definition
type RegCtrl is record
Read0 : RegNo ;
Read1 : RegNo ;
Write : RegNo ;
DoRead0 : bit ; -- if true read port 0
DoRead1 : bit ; -- if true read port 1
DoWrite : bit -- if true write data
end
procedure RegBank (
input RegCtrl : RegCtrl;
input WritePort : RegData ;
output ReadPort0, ReadPort1 : RegData
) is local
variable RegBank : array 0..7 of RegData
bundle containingControl info
Control word
write dataread data
Registeridentifiers read/write
control bits
internal registers
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Register Bank Control
loop
select RegCtrl then
if RegCtrl.DoWrite then
select WritePort then
RegBank[RegCtrl.Write] := WritePort
end
else
if RegCtrl.DoRead0 then ReadPort0 <-
RegBank[RegCtrl.Read0] end ||
if RegCtrl.DoRead1 then ReadPort1 <-
RegBank[RegCtrl.Read1] end
end
end
end
write signalled-await data, thenupdate register
can’t read and writesimultaneously
two reads canoccur together
awaitcontrol word
read register& output to channel
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Array Operations
Arrays can be concatenated
variable a, b : byte
variable c: array 4 of byte
variable d : array 6 of byte
c:= {a,b,a,b} -- tuple construction
c:= {a,b} @ {a,b} -- array concatenation
d:= c @ {a,b}
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Array Operations
arrays can be sliced
variable x : array 0 ..7 of 4 bits
variable y : array 0.. 1 of 4 bits
y:= x[1..2] -- returns a slice of x of type-- array 0 .. 1 of 4 bits
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Instruction Decoder
type Word is 16 signed bits
type Imm5 is 5 signed bits
variable ICtrl is 8 signed bits
-- bottom 5 bits contain an immediate value
variable Imm16 : word
Im16:= (((ICtrl as array 0..7 of bit)[0..4] as Imm5) as Word)
5-bit field is extracted& sign-extended to 16 bits
Word and Imm5are signed bits
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Instruction Decoder
type Word is 16 signed bits
type Imm5 is 5 signed bits
variable ICtrl is 8 signed bits
-- bottom 5 bits contain an immediate value
variable Imm16 : word
Im16:= (ICtrl as array 0..7 of bit)
casts Ictrl into anarray of bits for slicing
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Instruction Decoder
type Word is 16 signed bits
type Imm5 is 5 signed bits
variable ICtrl is 8 signed bits
-- bottom 5 bits contain an immediate value
variable Imm16 : word
Im16:= (ICtrl as array 0..7 of bit)[0..4]
extract bottom5 bits
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Instruction Decoder
type Word is 16 signed bits
type Imm5 is 5 signed bits
variable ICtrl is 8 signed bits
-- bottom 5 bits contain an immediate value
variable Imm16 : word
Im16:= ((ICtrl as array 0..7 of bit)[0..4] as Imm5)
cast the extracted bitsinto a 5-bit signed number
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Instruction Decoder
type Word is 16 signed bits
type Imm5 is 5 signed bits
variable ICtrl is 8 signed bits
-- bottom 5 bits contain an immediate value
variable Imm16 : word
Im16:= (((ICtrl as array 0..7 of bit)[0..4] as Imm5) as Word)
sign-extend the 5-bitnumber to 16 bits
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The Select Statement
MUX:• Illustrates unbuffered choice
– Inputs assumed mutually exclusive
• No internal latches
procedure mux (input a, b :byte; output c :byte) is
begin
loop
select a then c <- a -- channel behaves like a variable
| b then c <- b -- ditto
end
end
endselect gives
choice
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Arbitrated Choice
public
procedure mux (input a, b :byte; output c :byte) is
begin
loop
arbitrate a then c <- a
| b then c <- b
end
end
endarbitrated
choice
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Parameterised Procedures
Facilitates libraries Ex: buffer with parameterised width
procedure Buffer ( parameter X : type ;
input i : X;
output o : X) is
local variable x : X
begin
loop
i -> x ;
o <- x
end
end
X is of type type
vars defined in termsof parameterised type
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Using Parameterised Modules
-- pbuffer1a.balsa - calling parameterised a procedure
import [balsa.types.basic]
import [pbuffer1]
public
-- instantiate a byte-wide single place buffer
procedure test (input a :byte ; output b : byte) is
begin
Buffer over type byte of a,b
end
invoke a buffer of width byte
Buffer definedpreviously
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Multiple Parameters -1
Consider a pipeline• with parameterised width• with parameterised depth
-- BufferN: a n-place parameterised, variable width buffer
procedure BufferN( parameter n : cardinal ;
parameter X : type ;
input i : X ;
output o : X) is
local procedure buffer is Buffer over type X
begin
-- body of procedure
end
type cardinal ranges over natural
numbers
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Multiple Parameters -2
if n = 1 then -- single place pipeline
buffer(i, o)
| n >= 2 then
local array 1 .. n-1 of channel c : X
begin
buffer(i, c[1]) || -- first buffer
buffer(c[n-1], o) || -- last buffer
for || i in 1 ..n-2 then
buffer(c[i], c[i+1])
end
end
else print error, “zero length pipeline specified”
end
Procedure Buffer8 is BufferN over 4, type bytetest for
special cases
test for special cases
define a 4-deepbyte-wide pipeline
body of procedure
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Recursive Procedures
Adding recursion to Balsa allows elegant specifications of many circuits
Consider circuit to generate n handshakes for each call
Divide circuit into odd and even cases• even case: call itself twice• odd case : issue preliminary h/s and then
call itself twice
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Handshake Generator -1
procedure Repeat (parameter n : cardinal; sync o ) is
begin
if n = 0 then
print error, “Repeat n must not be 0”
| n = 1 then
sync o
| n = 2 then
sync o ; sync o
else
-- main body of procedure
end
base cases
recursive definitionhere
procedure name “repeat”
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Handshake Generator -2
local
shared doNext is begin
Repeat over n/2 of (o)
end
begin
if (n as bit) then -- n is odd
sync o
end ;
doNext () ; doNext ()
end
end
Procedure Gen5 is Repeat over 5
define localshared procedure
recursive callof “repeat”
call shared proceduretwice
define a 5xgenerator
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Handshake Multiplier
-- MultHS: repeat: handshake on `o’ `n’ times for each input
import [balsa.types.basic]
import [GenHS]
public
procedure MultHS (parameter n : cardinal; sync i ; sync o ) is
begin
loop
select i then continue end ;
Repeat over n of (o)
end
end
-- Here is a x5 gnerator
procedure MultHS5 is MultHS over 5
procedure repeatdefined earlier
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An n-way multiplexer
Decompose MUX:
inp0
inp 1
inp n-2
inp n-1out 1
out 0
inp 0
inp n-1
inp n/2
outout
Before Decomposition After Decomposition
inp n/2-1
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An n-way multiplexer -1
-- Pmux1.balsa: A recursive parameterised MUX definition
import [balsa.types.basic]
public
procedure PMux ( parameter X : type;
parameter n : cardinal;
array n of input inp : X;
output out : X ) is
begin
-- procedure body
width of input
number of
inputseach input is a channeloutput
channel
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An n-way multiplexer -2
if n = 0 then print error,”Parameter n should not be zero”
| n = 1 then
loop select inp[0] -> inp then
out <- inp
end
end
| n = 2 then
loop
select inp[0] -> inp then
out <- inp
| inp[1] -> inp then
out <- inp
end
end
when data arrives oneither i/p, pass it to o/p
base cases
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An n-way multiplexer -3
else
local
channel out0, out1 : X
constant mid = n/2
begin
PMux over type X, mid of inp[0..mid-1],out0 ||
PMux over type X, n-mid of inp[mid..n-1],out1 ||
PMux over type X, 2 of {out0,out1},out
end
end
end
2 internalchannels
two half-size muxs& one 2:1 mux
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Systolic Counters -1
Kees van Berkel’s design:• Recursively split counter into a head cell &
a n/2 tail cell• Head cells may be be odd or even counts
head N div 2
a
b
a’
b’
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Systolic Counters -2
Example:• A modulo-11 counter may be constructed
11 = 1 + 2 * 5
11 = 1 + 2 * (1 + 2 * 2)
11 = 1 + 2 * (1 + 2 * (2 * 1))
CO CECO C1
a0 a1 a2 a3
b0 b1 b2 b3
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Systolic Counters -3
Count even cell:
procedure c_even(sync a_left, a_right, b_left, b_right) is
begin
loop
select a_right then
sync a_left ; sync a_left
| b_right then
sync b_left
end
end
end
Choose betweena or b h/s on right
elsepass b from right to left
if a then double
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Systolic Counters -4
Count odd cell
procedure c_odd(sync a_left, a_right, b_left, b_right) is
begin
loop
sync a_left;
select a_right then
sync a_left
| b_right then
sync b_left
end
end
end
first h/s on left
then choose bewteen a & band pass on
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Systolic Counters -5
Base case: count 1 cell
procedure c_1(sync a, b) is
begin
loop
sync a; sync b
end
end
copy handshakefrom a to b
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Systolic Counters -6
procedure countN (parameter N : cardinal ; sync a, b) is
local sync a_int, b_int
begin
if N = 0 then print error, “Parameter n should not be zero”
| N = 1 then c_1(a, b)
else
if (N as bit) then -- Odd
c_odd(a, a_int, b, b_int)
else
c_even(a, a_int, b, b_int)
end || countN over N/2 of a_int, b_int
end
end
-- OK instantiate an arbitrary counter
procedure Ctest is countN over 53
2 internal sync-only channels
plant either an oddor even channel
and compose withremainder of counter
this is how we useuse the counter definition
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Systolic Counters -7
The count even cell chooses between a and b with a handshake on its right
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Count-Even cell
Count even cell:
procedure c_even(sync a_left, a_right, b_left, b_right) is
begin
loop
select a_right then
sync a_left ; sync a_left
| b_right then
sync b_left
end
end
end
handshake right enclosesrest of handshakes
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Systolic Counters -7
The count even cell chooses between a and b with a handshake on its right
Since choice is implemented by the enclosed select, the handshake ripples down to the far end• poor cycle time
Need a Tangram style, buffered select• Better perfomance
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Tangram style select
procedure c_even(sync a_left, a_right, b_left, b_right) is
local variable x : bit
begin
loop
select a_right then
x := 0
| b_right then
x := 1
end ;
case x of
0 then sync a_left ; sync a_left
| 1 then sync b_left
end
end
end
Buffer allows h/sto complete
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Makefile Generation
balsamd automatically generates a makefile for a design• Generates rules for usual source
dependencies• Generates rules for making a lard
– model of balsa design– test harness for exercising the lard model
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Simulation
3 possibilities• default lard test-harness• balsa test program
– balsa is flexible enough to be able to specify many test sequences
• custom lard test program– write your own lard
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Example Simulation
Lard time view of a modulo-15 systolic counter
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Mod-16 Counter (all even)
Balsa style select
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Mod-16 Counter (all even)
Tangram Style select