Background for Leakage Current Sept. 18, 2006 March 4, 2008.
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Transcript of Background for Leakage Current Sept. 18, 2006 March 4, 2008.
![Page 1: Background for Leakage Current Sept. 18, 2006 March 4, 2008.](https://reader035.fdocuments.in/reader035/viewer/2022062511/551a7dda550346e0158b4840/html5/thumbnails/1.jpg)
Background for Leakage Current
Sept. 18, 2006March 4, 2008
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Power Challenge
Active power density increasing with device scaling and increased frequency Leakage power density increasing due to lower Vt and gate leakage Stressing packaging, cooling, battery life, etc. Complicates IDDq testing as well
Thinning gate oxides increase
gate tunneling leakageSource from Bergamaschi
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Problem Statement
• Power Analysis on CMOS Inverter
Input switching to '1' or '0'
charge
discharge
Input
Cload
V thn< Input < VDD- | Vthp|
Input
Input : '1' or '0' steady state
Input
(a) Capacitive Current (b) Short Circuit Current (c) Static Leakage Current
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Problem Statement• Dynamic Power
• Average Short Circuit Current
• Sub-threshold Leakage Current
P C VDD fswitching switching 2
IVDD
VDD V fSCin
th
122 3( )
gain factor
Threshold Voltage V V V
n p
thn thp th
_ : ,
_ :
I e eDSV V q nkT V q kTGS th DS ( ) / /( )1
K V V
V q k T
n kT
GS DS
th
: : , :
: : , : :
: ~ ( . )
function of technology, gate to source voltage drain to source voltage,
theshold voltage, electronic charge Boltzmann constance, temperature,
nonlinearity constance ,
1 2 0 0259
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Problem Statement• Domination of Leakage Current
Feature SizeFeature Size
Core VoltageCore Voltage
VTH(Threshold)VTH(Threshold)
Performance(AP)Performance(AP)
TR LeakageTR Leakage
Stand-by ModeStand-by Mode
Low PowerLow Power
> 0.25um> 0.25um
5.0/3.3/2.5V5.0/3.3/2.5V
> +/- 0.6V> +/- 0.6V
< 200MHz< 200MHz
NegligibleNegligible
PLL-off(Clock-off)PLL-off(Clock-off)
Focus on Operating PowerFocus on Operating Power
0.18/0.13/0.09um…0.18/0.13/0.09um…
1.8/1.2/1.0V …1.8/1.2/1.0V …
+/- 0.5, 0.4, 0.3V …+/- 0.5, 0.4, 0.3V …
300/400/533MHz, 1GHz300/400/533MHz, 1GHz
Exponential growing(SD/Gate)Exponential growing(SD/Gate)
V/MTMOS, High VTH/High VDDV/MTMOS, High VTH/High VDD
Focus on Operating/Stand-byFocus on Operating/Stand-by
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Active and Leakage Power with CMOS Scaling
• As CMOS scales down the following stand-by leakage current rises rapidly.– Source to drain leakage
(diffusion+tunneling) as Lg scales down
– Gate leakage current (tunneling) as Tox scales down
– Body to drain leakage current (tunneling) as channel doping scales up
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Two cases of Leakage Mechanism
Vg=0VTurn off
Vd=Vdd
Turn on
Vg=Vdd
Vd=0V
Sub-threshold Leakage
Source to drain tunneling
Drain to Body tunneling (BTB)
Gate oxide tunneling
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Gate Leakage Current Reduction with High-K Gate Dielectric
10-6
10-5
10-4
10-3
10-2
10-1
100
101
20 25 30 35 40
Cur
rent
Den
sity
(A
/cm2
)
Tox (A)
Gate leakage
Drain leakage
Ck A
Toxphysical
0
High-K gate dielectric
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Voltage Scaling for Low Power
Low Power
Low VDDLow VDD
Low Speed
Speed Up
Low VthLow Vth
P VDD2
I ds (VDD - Vth)1~2
I ds (VDD - Vth)1~2
High Leakage
I leakage e-C x Vth
Leakage Suppression
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Low-Leakage Solution – TechnologyD
ynam
ic p
ow
er[W
]
Leakage power[W]
VTH: 0.5V VTH: 0.25V
High speed
Low speed Low speed
VDD control
VTH control
High speedMTCMOS
VDD: 1.5V
VDD: 1.0V
VDD control
VTH control
100n
1
10
100
100p1p 10p 100n1n 10n
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VTCMOS & MTCMOSMulti-Threshold CMOSMulti-Threshold CMOS Variable-Threshold CMOSVariable-Threshold CMOS
Schem
atic Diagram
Schem
atic Diagram
principleprinciple
•On-off control of internal VDD or VSS•Special F/Fs, Two Vth’s
•On-off control of internal VDD or VSS•Special F/Fs, Two Vth’s
•Threshold control with bulk-bias•Triple well is desirable
•Threshold control with bulk-bias•Triple well is desirable
•Low leakage in stand-by mode.•Conventional design Env.
•Low leakage in stand-by mode.•Conventional design Env.
Merit
Merit
•Low leakage in stand-by mode.•Conventional design Env.
•Low leakage in stand-by mode.•Conventional design Env.
Dem
eritD
emerit
•Large serial MOSFET •ground bounce noise
•Ultra-low voltage region?(1V)
•Large serial MOSFET •ground bounce noise
•Ultra-low voltage region?(1V)
•Scalability? (junction leakage)•TR reliability under 0.1m
•Latch-up immunity, Vth controllability, Substrate noise, Gate oxide reliability
•Gate leakage current
•Scalability? (junction leakage)•TR reliability under 0.1m
•Latch-up immunity, Vth controllability, Substrate noise, Gate oxide reliability
•Gate leakage current
Low-Vth
VDD
GND
Hi-VthSleep
Low Vt
VDD
GND
VtControlcircuit
Vnb = 0 or V-
Vpb = VDD or V+
N-well
P-well
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MTCMOS : Reduce Stand-by Power with High Speed
• With High VTH switch, much lower leakage current flows between Vdd and Vss• High VTH MOSFET should have much lower ( >10X) leakage current compared to normal VTH
MOSFET
Vdd
Vss
0 0
Vdd
Vss
1 1
0
Without High VTH switch With High VTH switch (MTCMOS)
High VTH switch
Normal or Low VTH MOSFET
Virtual Ground
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Multi-Threshold CMOS (MTCMOS)• Mobile Applications
– Mostly in the idle state– Sub-threshold leakage Current
• Power Gating – Low VTH Transistors for High Performance Logic Gates– High VTH Transistors for Low Leakage Current Gates
Active Sleep Active
Sleep Control
(SC)Time
OperatingMode
CurrentCutoff-Switch(High Vth)
SC
VDD
VSSVGND
Low Vth
MOS
High Vth
MOS
Logic Component (Low Vth)
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CCS Sizing• The effect of CCS (current-controlled switch) size
– As the size decreases, logic performance also decreases.– As the size increases, leakage current and chip area also
increase.– Proper sizing is very important.– CCS size should be decided within 2% performance
degradation.
Vop = VDD - V
V must be sizedwithin 2% performance degradation.
VDD
GND
Low Vt
High Vt SwitchControl
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Leakage Current :Limiting Factor in VDSM
Technology
C.M.Kyung
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ITRS roadmap
• Scaling down allows the same performance with reduced voltage, leading to low power.
• From 0.18 micron down, building a transistor with a good active current(Ion) and a low leakage current (Ioff) is difficult. – high-speed TR’s ; low channel doping– low-leakage TR’s ; high channel doping
• Now three groups of TR’s;– High Performance (HP) ; high active current ; Thin Tox – Low Operating Power (LOP) ; low active current ; High Tox
– Low Standby Power (LSTP) ; low static current ; High Tox
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Device characteristics for HP, LOP, and LSTP Technologies
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Reference : Low-Power CMOS Circuits technology, logic design and CAD toolsBy Christian Piguet CRC Taylor and Francis 2005
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Bulk CMOS vs. SOI
• Buried oxide layer below active silicon layer -> electrical isolation of TR’s– Lower parasitic cap.
• PD(Partially Depleted) – Floating body effect increases speed
• Low threshold in dynamic mode
• or FD(Fully Depl)– Ideal subthresold swing of 60 mV/decade
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Reducing Subthreshold current in Bulk CMOS
• VTCMOS (Variable Threshold)– Tune substrate bias to adjust Vth
– Requires efficient DC-DC converter– For a given technology, there an optimum in VR , as
decreasing subthreshold leakage is accompanied by an increase in drain junction leakage
• When both High Vt and Low Vt TR’s are available,– MTCMOS (Multi-Threshold) ; Introduce high Vt power
switch to limit leakage in stby mode– Use low Vt for critical path– This can be coupled with multiple VDD’s
• Other tricks– Set up the logical internal states where the total leakage
is minimal.
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Five types of off-currents
• Tunneling through gate oxide– Fowler-Nordheim tunneling -> direct tunneling
• Subthreshold current• Gate-induced drain leakage (GIDL)
– Thermal emission– Trap-assisted tunneling– BTBT
• Reverse-biased pn junction current – -> band-to-band tunneling (BTBT) current
• Bulk punch-through
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Gate-induced drain leakage (GIDL)
• Gate-induced drain leakage (GIDL)– Thermal emission– Trap-assisted tunneling– BTBT
• Fig 3.12
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Leakage current due to QM Tunneling
• substrate and drain ; band-to-band tunneling ; – increases with E-field and dopant concentration
due to scaling• source and drain ;
– Surface punchthru due to DIBL– Punch-through at bulk
• gate oxide ;– SiO2 has been used as it has so low trap and
fixed charge density at the interface– Gate current is an exponential function of Tox
and Vox– Hole tunneling is 10% of that of electron due to
higher barrier height and heavier effective mass
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Gate Leakage Current Reduction with High-K Gate Dielectric
• As Tox scales gate leakage current increases exponentially due to exponential increase of tunneling probability with reduction of physical tunneling distance.
• Physically thicker gate dielectric allows lower leakage current but lower oxide capacitance reducing on-current
• Using high k (dielectric constant) material, both thicker physical thickness and higher oxide capacitance can be achieved.
• Applying high-k gate dielectric, several orders of magnitude lower gate leakage current can be achieved with similar oxide capacitance
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Approach 1 to reduce gate leakage ; High K materials
• To suppress gate tunneling current, use materials with – High K -> increases thickness (t)– Higher barrier height (h)
• Using high K– Increases short-channel effects due to thicker
gate dielectric (This sets an upper limit on K, lower limit coming from I tunnel)
– Mobility degradation due to poor interface quality
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Approach 2 to reduce gate leakage ; stop scaling the thickness of gate
oxide• Thicker gate oxide yields less control
of gate on channel conduction, i.e., higher short-channel effects and DIBL effects.
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Approach 3 to reduce gate leakage
• Multiple gates allows better control of channel by gate, and lets scaling continue without excessive short-channel effects– Double gate– FinFET– Triple gate– Quadruple or gate all-around
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